git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  18  * MA 02110-1301, USA.
  19  */
  20
  21 #include <common.h>
  22 #include <nand.h>
  23 #include <linux/err.h>
  24 #include <asm/io.h>
  25 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
  26         defined(CONFIG_MX51) || defined(CONFIG_MX53)
  27 #include <asm/arch/imx-regs.h>
  28 #endif
  29 #include "mxc_nand.h"
  30
  31 #define DRIVER_NAME "mxc_nand"
  32
  33 struct mxc_nand_host {
  34         struct mtd_info                 mtd;
  35         struct nand_chip                *nand;
  36
  37         struct mxc_nand_regs __iomem    *regs;
  38 #ifdef MXC_NFC_V3_2
  39         struct mxc_nand_ip_regs __iomem *ip_regs;
  40 #endif
  41         int                             spare_only;
  42         int                             status_request;
  43         int                             pagesize_2k;
  44         int                             clk_act;
  45         uint16_t                        col_addr;
  46         unsigned int                    page_addr;
  47 };
  48
  49 static struct mxc_nand_host mxc_host;
  50 static struct mxc_nand_host *host = &mxc_host;
  51
  52 /* Define delays in microsec for NAND device operations */
  53 #define TROP_US_DELAY   2000
  54 /* Macros to get byte and bit positions of ECC */
  55 #define COLPOS(x)  ((x) >> 3)
  56 #define BITPOS(x) ((x) & 0xf)
  57
  58 /* Define single bit Error positions in Main & Spare area */
  59 #define MAIN_SINGLEBIT_ERROR 0x4
  60 #define SPARE_SINGLEBIT_ERROR 0x1
  61
  62 /* OOB placement block for use with hardware ecc generation */
  63 #if defined(MXC_NFC_V1)
  64 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  65 static struct nand_ecclayout nand_hw_eccoob = {
  66         .eccbytes = 5,
  67         .eccpos = {6, 7, 8, 9, 10},
  68         .oobfree = { {0, 5}, {11, 5}, }
  69 };
  70 #else
  71 static struct nand_ecclayout nand_hw_eccoob2k = {
  72         .eccbytes = 20,
  73         .eccpos = {
  74                 6, 7, 8, 9, 10,
  75                 22, 23, 24, 25, 26,
  76                 38, 39, 40, 41, 42,
  77                 54, 55, 56, 57, 58,
  78         },
  79         .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
  80 };
  81 #endif
  82 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  83 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  84 static struct nand_ecclayout nand_hw_eccoob = {
  85         .eccbytes = 9,
  86         .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
  87         .oobfree = { {2, 5} }
  88 };
  89 #else
  90 static struct nand_ecclayout nand_hw_eccoob2k = {
  91         .eccbytes = 36,
  92         .eccpos = {
  93                 7, 8, 9, 10, 11, 12, 13, 14, 15,
  94                 23, 24, 25, 26, 27, 28, 29, 30, 31,
  95                 39, 40, 41, 42, 43, 44, 45, 46, 47,
  96                 55, 56, 57, 58, 59, 60, 61, 62, 63,
  97         },
  98         .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
  99 };
 100 #endif
 101 #endif
 102
 103 static int is_16bit_nand(void)
 104 {
 105 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
 106         return 1;
 107 #else
 108         return 0;
 109 #endif
 110 }
 111
 112 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
 113 {
 114         uint32_t *d = dest;
 115
 116         size >>= 2;
 117         while (size--)
 118                 __raw_writel(__raw_readl(source++), d++);
 119         return dest;
 120 }
 121
 122 /*
 123  * This function polls the NANDFC to wait for the basic operation to
 124  * complete by checking the INT bit.
 125  */
 126 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 127                                 uint16_t param)
 128 {
 129         uint32_t tmp;
 130
 131         while (max_retries-- > 0) {
 132 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 133                 tmp = readnfc(&host->regs->config2);
 134                 if (tmp & NFC_V1_V2_CONFIG2_INT) {
 135                         tmp &= ~NFC_V1_V2_CONFIG2_INT;
 136                         writenfc(tmp, &host->regs->config2);
 137 #elif defined(MXC_NFC_V3_2)
 138                 tmp = readnfc(&host->ip_regs->ipc);
 139                 if (tmp & NFC_V3_IPC_INT) {
 140                         tmp &= ~NFC_V3_IPC_INT;
 141                         writenfc(tmp, &host->ip_regs->ipc);
 142 #endif
 143                         break;
 144                 }
 145                 udelay(1);
 146         }
 147         if (max_retries < 0) {
 148                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
 149                                 __func__, param);
 150         }
 151 }
 152
 153 /*
 154  * This function issues the specified command to the NAND device and
 155  * waits for completion.
 156  */
 157 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
 158 {
 159         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
 160
 161         writenfc(cmd, &host->regs->flash_cmd);
 162         writenfc(NFC_CMD, &host->regs->operation);
 163
 164         /* Wait for operation to complete */
 165         wait_op_done(host, TROP_US_DELAY, cmd);
 166 }
 167
 168 /*
 169  * This function sends an address (or partial address) to the
 170  * NAND device. The address is used to select the source/destination for
 171  * a NAND command.
 172  */
 173 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
 174 {
 175         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
 176
 177         writenfc(addr, &host->regs->flash_addr);
 178         writenfc(NFC_ADDR, &host->regs->operation);
 179
 180         /* Wait for operation to complete */
 181         wait_op_done(host, TROP_US_DELAY, addr);
 182 }
 183
 184 /*
 185  * This function requests the NANDFC to initiate the transfer
 186  * of data currently in the NANDFC RAM buffer to the NAND device.
 187  */
 188 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 189                         int spare_only)
 190 {
 191         if (spare_only)
 192                 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
 193
 194         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 195                 int i;
 196                 /*
 197                  *  The controller copies the 64 bytes of spare data from
 198                  *  the first 16 bytes of each of the 4 64 byte spare buffers.
 199                  *  Copy the contiguous data starting in spare_area[0] to
 200                  *  the four spare area buffers.
 201                  */
 202                 for (i = 1; i < 4; i++) {
 203                         void __iomem *src = &host->regs->spare_area[0][i * 16];
 204                         void __iomem *dst = &host->regs->spare_area[i][0];
 205
 206                         mxc_nand_memcpy32(dst, src, 16);
 207                 }
 208         }
 209
 210 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 211         writenfc(buf_id, &host->regs->buf_addr);
 212 #elif defined(MXC_NFC_V3_2)
 213         uint32_t tmp = readnfc(&host->regs->config1);
 214         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 215         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 216         writenfc(tmp, &host->regs->config1);
 217 #endif
 218
 219         /* Configure spare or page+spare access */
 220         if (!host->pagesize_2k) {
 221                 uint32_t config1 = readnfc(&host->regs->config1);
 222                 if (spare_only)
 223                         config1 |= NFC_CONFIG1_SP_EN;
 224                 else
 225                         config1 &= ~NFC_CONFIG1_SP_EN;
 226                 writenfc(config1, &host->regs->config1);
 227         }
 228
 229         writenfc(NFC_INPUT, &host->regs->operation);
 230
 231         /* Wait for operation to complete */
 232         wait_op_done(host, TROP_US_DELAY, spare_only);
 233 }
 234
 235 /*
 236  * Requests NANDFC to initiate the transfer of data from the
 237  * NAND device into in the NANDFC ram buffer.
 238  */
 239 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 240                 int spare_only)
 241 {
 242         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
 243
 244 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 245         writenfc(buf_id, &host->regs->buf_addr);
 246 #elif defined(MXC_NFC_V3_2)
 247         uint32_t tmp = readnfc(&host->regs->config1);
 248         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 249         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 250         writenfc(tmp, &host->regs->config1);
 251 #endif
 252
 253         /* Configure spare or page+spare access */
 254         if (!host->pagesize_2k) {
 255                 uint32_t config1 = readnfc(&host->regs->config1);
 256                 if (spare_only)
 257                         config1 |= NFC_CONFIG1_SP_EN;
 258                 else
 259                         config1 &= ~NFC_CONFIG1_SP_EN;
 260                 writenfc(config1, &host->regs->config1);
 261         }
 262
 263         writenfc(NFC_OUTPUT, &host->regs->operation);
 264
 265         /* Wait for operation to complete */
 266         wait_op_done(host, TROP_US_DELAY, spare_only);
 267
 268         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 269                 int i;
 270
 271                 /*
 272                  *  The controller copies the 64 bytes of spare data to
 273                  *  the first 16 bytes of each of the 4 spare buffers.
 274                  *  Make the data contiguous starting in spare_area[0].
 275                  */
 276                 for (i = 1; i < 4; i++) {
 277                         void __iomem *src = &host->regs->spare_area[i][0];
 278                         void __iomem *dst = &host->regs->spare_area[0][i * 16];
 279
 280                         mxc_nand_memcpy32(dst, src, 16);
 281                 }
 282         }
 283 }
 284
 285 /* Request the NANDFC to perform a read of the NAND device ID. */
 286 static void send_read_id(struct mxc_nand_host *host)
 287 {
 288         uint32_t tmp;
 289
 290 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 291         /* NANDFC buffer 0 is used for device ID output */
 292         writenfc(0x0, &host->regs->buf_addr);
 293 #elif defined(MXC_NFC_V3_2)
 294         tmp = readnfc(&host->regs->config1);
 295         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 296         writenfc(tmp, &host->regs->config1);
 297 #endif
 298
 299         /* Read ID into main buffer */
 300         tmp = readnfc(&host->regs->config1);
 301         tmp &= ~NFC_CONFIG1_SP_EN;
 302         writenfc(tmp, &host->regs->config1);
 303
 304         writenfc(NFC_ID, &host->regs->operation);
 305
 306         /* Wait for operation to complete */
 307         wait_op_done(host, TROP_US_DELAY, 0);
 308 }
 309
 310 /*
 311  * This function requests the NANDFC to perform a read of the
 312  * NAND device status and returns the current status.
 313  */
 314 static uint16_t get_dev_status(struct mxc_nand_host *host)
 315 {
 316 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 317         void __iomem *main_buf = host->regs->main_area[1];
 318         uint32_t store;
 319 #endif
 320         uint32_t ret, tmp;
 321         /* Issue status request to NAND device */
 322
 323 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 324         /* store the main area1 first word, later do recovery */
 325         store = readl(main_buf);
 326         /* NANDFC buffer 1 is used for device status */
 327         writenfc(1, &host->regs->buf_addr);
 328 #endif
 329
 330         /* Read status into main buffer */
 331         tmp = readnfc(&host->regs->config1);
 332         tmp &= ~NFC_CONFIG1_SP_EN;
 333         writenfc(tmp, &host->regs->config1);
 334
 335         writenfc(NFC_STATUS, &host->regs->operation);
 336
 337         /* Wait for operation to complete */
 338         wait_op_done(host, TROP_US_DELAY, 0);
 339
 340 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 341         /*
 342          *  Status is placed in first word of main buffer
 343          * get status, then recovery area 1 data
 344          */
 345         ret = readw(main_buf);
 346         writel(store, main_buf);
 347 #elif defined(MXC_NFC_V3_2)
 348         ret = readnfc(&host->regs->config1) >> 16;
 349 #endif
 350
 351         return ret;
 352 }
 353
 354 /* This function is used by upper layer to checks if device is ready */
 355 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 356 {
 357         /*
 358          * NFC handles R/B internally. Therefore, this function
 359          * always returns status as ready.
 360          */
 361         return 1;
 362 }
 363
 364 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
 365 {
 366         struct nand_chip *nand_chip = mtd->priv;
 367         struct mxc_nand_host *host = nand_chip->priv;
 368 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 369         uint16_t tmp = readnfc(&host->regs->config1);
 370
 371         if (on)
 372                 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
 373         else
 374                 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
 375         writenfc(tmp, &host->regs->config1);
 376 #elif defined(MXC_NFC_V3_2)
 377         uint32_t tmp = readnfc(&host->ip_regs->config2);
 378
 379         if (on)
 380                 tmp |= NFC_V3_CONFIG2_ECC_EN;
 381         else
 382                 tmp &= ~NFC_V3_CONFIG2_ECC_EN;
 383         writenfc(tmp, &host->ip_regs->config2);
 384 #endif
 385 }
 386
 387 #ifdef CONFIG_MXC_NAND_HWECC
 388 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 389 {
 390         /*
 391          * If HW ECC is enabled, we turn it on during init. There is
 392          * no need to enable again here.
 393          */
 394 }
 395
 396 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
 397 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 398                                       struct nand_chip *chip,
 399                                       int page, int sndcmd)
 400 {
 401         struct mxc_nand_host *host = chip->priv;
 402         uint8_t *buf = chip->oob_poi;
 403         int length = mtd->oobsize;
 404         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 405         uint8_t *bufpoi = buf;
 406         int i, toread;
 407
 408         MTDDEBUG(MTD_DEBUG_LEVEL0,
 409                         "%s: Reading OOB area of page %u to oob %p\n",
 410                          __func__, page, buf);
 411
 412         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 413         for (i = 0; i < chip->ecc.steps; i++) {
 414                 toread = min_t(int, length, chip->ecc.prepad);
 415                 if (toread) {
 416                         chip->read_buf(mtd, bufpoi, toread);
 417                         bufpoi += toread;
 418                         length -= toread;
 419                 }
 420                 bufpoi += chip->ecc.bytes;
 421                 host->col_addr += chip->ecc.bytes;
 422                 length -= chip->ecc.bytes;
 423
 424                 toread = min_t(int, length, chip->ecc.postpad);
 425                 if (toread) {
 426                         chip->read_buf(mtd, bufpoi, toread);
 427                         bufpoi += toread;
 428                         length -= toread;
 429                 }
 430         }
 431         if (length > 0)
 432                 chip->read_buf(mtd, bufpoi, length);
 433
 434         _mxc_nand_enable_hwecc(mtd, 0);
 435         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 436                         mtd->writesize + chip->ecc.prepad, page);
 437         bufpoi = buf + chip->ecc.prepad;
 438         length = mtd->oobsize - chip->ecc.prepad;
 439         for (i = 0; i < chip->ecc.steps; i++) {
 440                 toread = min_t(int, length, chip->ecc.bytes);
 441                 chip->read_buf(mtd, bufpoi, toread);
 442                 bufpoi += eccpitch;
 443                 length -= eccpitch;
 444                 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
 445         }
 446         _mxc_nand_enable_hwecc(mtd, 1);
 447         return 1;
 448 }
 449
 450 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 451                                            struct nand_chip *chip,
 452                                            uint8_t *buf,
 453                                            int page)
 454 {
 455         struct mxc_nand_host *host = chip->priv;
 456         int eccsize = chip->ecc.size;
 457         int eccbytes = chip->ecc.bytes;
 458         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 459         uint8_t *oob = chip->oob_poi;
 460         int steps, size;
 461         int n;
 462
 463         _mxc_nand_enable_hwecc(mtd, 0);
 464         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 465
 466         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 467                 host->col_addr = n * eccsize;
 468                 chip->read_buf(mtd, buf, eccsize);
 469                 buf += eccsize;
 470
 471                 host->col_addr = mtd->writesize + n * eccpitch;
 472                 if (chip->ecc.prepad) {
 473                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 474                         oob += chip->ecc.prepad;
 475                 }
 476
 477                 chip->read_buf(mtd, oob, eccbytes);
 478                 oob += eccbytes;
 479
 480                 if (chip->ecc.postpad) {
 481                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 482                         oob += chip->ecc.postpad;
 483                 }
 484         }
 485
 486         size = mtd->oobsize - (oob - chip->oob_poi);
 487         if (size)
 488                 chip->read_buf(mtd, oob, size);
 489         _mxc_nand_enable_hwecc(mtd, 1);
 490
 491         return 0;
 492 }
 493
 494 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 495                                        struct nand_chip *chip,
 496                                        uint8_t *buf,
 497                                        int page)
 498 {
 499         struct mxc_nand_host *host = chip->priv;
 500         int n, eccsize = chip->ecc.size;
 501         int eccbytes = chip->ecc.bytes;
 502         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 503         int eccsteps = chip->ecc.steps;
 504         uint8_t *p = buf;
 505         uint8_t *oob = chip->oob_poi;
 506
 507         MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
 508               page, buf, oob);
 509
 510         /* first read the data area and the available portion of OOB */
 511         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 512                 int stat;
 513
 514                 host->col_addr = n * eccsize;
 515
 516                 chip->read_buf(mtd, p, eccsize);
 517
 518                 host->col_addr = mtd->writesize + n * eccpitch;
 519
 520                 if (chip->ecc.prepad) {
 521                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 522                         oob += chip->ecc.prepad;
 523                 }
 524
 525                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 526
 527                 if (stat < 0)
 528                         mtd->ecc_stats.failed++;
 529                 else
 530                         mtd->ecc_stats.corrected += stat;
 531                 oob += eccbytes;
 532
 533                 if (chip->ecc.postpad) {
 534                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 535                         oob += chip->ecc.postpad;
 536                 }
 537         }
 538
 539         /* Calculate remaining oob bytes */
 540         n = mtd->oobsize - (oob - chip->oob_poi);
 541         if (n)
 542                 chip->read_buf(mtd, oob, n);
 543
 544         /* Then switch ECC off and read the OOB area to get the ECC code */
 545         _mxc_nand_enable_hwecc(mtd, 0);
 546         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 547         eccsteps = chip->ecc.steps;
 548         oob = chip->oob_poi + chip->ecc.prepad;
 549         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 550                 host->col_addr = mtd->writesize +
 551                                  n * eccpitch +
 552                                  chip->ecc.prepad;
 553                 chip->read_buf(mtd, oob, eccbytes);
 554                 oob += eccbytes + chip->ecc.postpad;
 555         }
 556         _mxc_nand_enable_hwecc(mtd, 1);
 557         return 0;
 558 }
 559
 560 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 561                                        struct nand_chip *chip, int page)
 562 {
 563         struct mxc_nand_host *host = chip->priv;
 564         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 565         int length = mtd->oobsize;
 566         int i, len, status, steps = chip->ecc.steps;
 567         const uint8_t *bufpoi = chip->oob_poi;
 568
 569         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 570         for (i = 0; i < steps; i++) {
 571                 len = min_t(int, length, eccpitch);
 572
 573                 chip->write_buf(mtd, bufpoi, len);
 574                 bufpoi += len;
 575                 length -= len;
 576                 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
 577         }
 578         if (length > 0)
 579                 chip->write_buf(mtd, bufpoi, length);
 580
 581         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 582         status = chip->waitfunc(mtd, chip);
 583         return status & NAND_STATUS_FAIL ? -EIO : 0;
 584 }
 585
 586 static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 587                                              struct nand_chip *chip,
 588                                              const uint8_t *buf)
 589 {
 590         struct mxc_nand_host *host = chip->priv;
 591         int eccsize = chip->ecc.size;
 592         int eccbytes = chip->ecc.bytes;
 593         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 594         uint8_t *oob = chip->oob_poi;
 595         int steps, size;
 596         int n;
 597
 598         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 599                 host->col_addr = n * eccsize;
 600                 chip->write_buf(mtd, buf, eccsize);
 601                 buf += eccsize;
 602
 603                 host->col_addr = mtd->writesize + n * eccpitch;
 604
 605                 if (chip->ecc.prepad) {
 606                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 607                         oob += chip->ecc.prepad;
 608                 }
 609
 610                 host->col_addr += eccbytes;
 611                 oob += eccbytes;
 612
 613                 if (chip->ecc.postpad) {
 614                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 615                         oob += chip->ecc.postpad;
 616                 }
 617         }
 618
 619         size = mtd->oobsize - (oob - chip->oob_poi);
 620         if (size)
 621                 chip->write_buf(mtd, oob, size);
 622 }
 623
 624 static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 625                                          struct nand_chip *chip,
 626                                          const uint8_t *buf)
 627 {
 628         struct mxc_nand_host *host = chip->priv;
 629         int i, n, eccsize = chip->ecc.size;
 630         int eccbytes = chip->ecc.bytes;
 631         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 632         int eccsteps = chip->ecc.steps;
 633         const uint8_t *p = buf;
 634         uint8_t *oob = chip->oob_poi;
 635
 636         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
 637
 638         for (i = n = 0;
 639              eccsteps;
 640              n++, eccsteps--, i += eccbytes, p += eccsize) {
 641                 host->col_addr = n * eccsize;
 642
 643                 chip->write_buf(mtd, p, eccsize);
 644
 645                 host->col_addr = mtd->writesize + n * eccpitch;
 646
 647                 if (chip->ecc.prepad) {
 648                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 649                         oob += chip->ecc.prepad;
 650                 }
 651
 652                 chip->write_buf(mtd, oob, eccbytes);
 653                 oob += eccbytes;
 654
 655                 if (chip->ecc.postpad) {
 656                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 657                         oob += chip->ecc.postpad;
 658                 }
 659         }
 660
 661         /* Calculate remaining oob bytes */
 662         i = mtd->oobsize - (oob - chip->oob_poi);
 663         if (i)
 664                 chip->write_buf(mtd, oob, i);
 665 }
 666
 667 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 668                                  u_char *read_ecc, u_char *calc_ecc)
 669 {
 670         struct nand_chip *nand_chip = mtd->priv;
 671         struct mxc_nand_host *host = nand_chip->priv;
 672         uint32_t ecc_status = readl(&host->regs->ecc_status_result);
 673         int subpages = mtd->writesize / nand_chip->subpagesize;
 674         int pg2blk_shift = nand_chip->phys_erase_shift -
 675                            nand_chip->page_shift;
 676
 677         do {
 678                 if ((ecc_status & 0xf) > 4) {
 679                         static int last_bad = -1;
 680
 681                         if (last_bad != host->page_addr >> pg2blk_shift) {
 682                                 last_bad = host->page_addr >> pg2blk_shift;
 683                                 printk(KERN_DEBUG
 684                                        "MXC_NAND: HWECC uncorrectable ECC error"
 685                                        " in block %u page %u subpage %d\n",
 686                                        last_bad, host->page_addr,
 687                                        mtd->writesize / nand_chip->subpagesize
 688                                             - subpages);
 689                         }
 690                         return -1;
 691                 }
 692                 ecc_status >>= 4;
 693                 subpages--;
 694         } while (subpages > 0);
 695
 696         return 0;
 697 }
 698 #else
 699 #define mxc_nand_read_page_syndrome NULL
 700 #define mxc_nand_read_page_raw_syndrome NULL
 701 #define mxc_nand_read_oob_syndrome NULL
 702 #define mxc_nand_write_page_syndrome NULL
 703 #define mxc_nand_write_page_raw_syndrome NULL
 704 #define mxc_nand_write_oob_syndrome NULL
 705
 706 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 707                                  u_char *read_ecc, u_char *calc_ecc)
 708 {
 709         struct nand_chip *nand_chip = mtd->priv;
 710         struct mxc_nand_host *host = nand_chip->priv;
 711
 712         /*
 713          * 1-Bit errors are automatically corrected in HW.  No need for
 714          * additional correction.  2-Bit errors cannot be corrected by
 715          * HW ECC, so we need to return failure
 716          */
 717         uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
 718
 719         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 720                 MTDDEBUG(MTD_DEBUG_LEVEL0,
 721                       "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 722                 return -1;
 723         }
 724
 725         return 0;
 726 }
 727 #endif
 728
 729 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 730                                   u_char *ecc_code)
 731 {
 732         return 0;
 733 }
 734 #endif
 735
 736 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 737 {
 738         struct nand_chip *nand_chip = mtd->priv;
 739         struct mxc_nand_host *host = nand_chip->priv;
 740         uint8_t ret = 0;
 741         uint16_t col;
 742         uint16_t __iomem *main_buf =
 743                 (uint16_t __iomem *)host->regs->main_area[0];
 744         uint16_t __iomem *spare_buf =
 745                 (uint16_t __iomem *)host->regs->spare_area[0];
 746         union {
 747                 uint16_t word;
 748                 uint8_t bytes[2];
 749         } nfc_word;
 750
 751         /* Check for status request */
 752         if (host->status_request)
 753                 return get_dev_status(host) & 0xFF;
 754
 755         /* Get column for 16-bit access */
 756         col = host->col_addr >> 1;
 757
 758         /* If we are accessing the spare region */
 759         if (host->spare_only)
 760                 nfc_word.word = readw(&spare_buf[col]);
 761         else
 762                 nfc_word.word = readw(&main_buf[col]);
 763
 764         /* Pick upper/lower byte of word from RAM buffer */
 765         ret = nfc_word.bytes[host->col_addr & 0x1];
 766
 767         /* Update saved column address */
 768         if (nand_chip->options & NAND_BUSWIDTH_16)
 769                 host->col_addr += 2;
 770         else
 771                 host->col_addr++;
 772
 773         return ret;
 774 }
 775
 776 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 777 {
 778         struct nand_chip *nand_chip = mtd->priv;
 779         struct mxc_nand_host *host = nand_chip->priv;
 780         uint16_t col, ret;
 781         uint16_t __iomem *p;
 782
 783         MTDDEBUG(MTD_DEBUG_LEVEL3,
 784               "mxc_nand_read_word(col = %d)\n", host->col_addr);
 785
 786         col = host->col_addr;
 787         /* Adjust saved column address */
 788         if (col < mtd->writesize && host->spare_only)
 789                 col += mtd->writesize;
 790
 791         if (col < mtd->writesize) {
 792                 p = (uint16_t __iomem *)(host->regs->main_area[0] +
 793                                 (col >> 1));
 794         } else {
 795                 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
 796                                 ((col - mtd->writesize) >> 1));
 797         }
 798
 799         if (col & 1) {
 800                 union {
 801                         uint16_t word;
 802                         uint8_t bytes[2];
 803                 } nfc_word[3];
 804
 805                 nfc_word[0].word = readw(p);
 806                 nfc_word[1].word = readw(p + 1);
 807
 808                 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
 809                 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
 810
 811                 ret = nfc_word[2].word;
 812         } else {
 813                 ret = readw(p);
 814         }
 815
 816         /* Update saved column address */
 817         host->col_addr = col + 2;
 818
 819         return ret;
 820 }
 821
 822 /*
 823  * Write data of length len to buffer buf. The data to be
 824  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 825  * Operation by the NFC, the data is written to NAND Flash
 826  */
 827 static void mxc_nand_write_buf(struct mtd_info *mtd,
 828                                 const u_char *buf, int len)
 829 {
 830         struct nand_chip *nand_chip = mtd->priv;
 831         struct mxc_nand_host *host = nand_chip->priv;
 832         int n, col, i = 0;
 833
 834         MTDDEBUG(MTD_DEBUG_LEVEL3,
 835               "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 836               len);
 837
 838         col = host->col_addr;
 839
 840         /* Adjust saved column address */
 841         if (col < mtd->writesize && host->spare_only)
 842                 col += mtd->writesize;
 843
 844         n = mtd->writesize + mtd->oobsize - col;
 845         n = min(len, n);
 846
 847         MTDDEBUG(MTD_DEBUG_LEVEL3,
 848               "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 849
 850         while (n > 0) {
 851                 void __iomem *p;
 852
 853                 if (col < mtd->writesize) {
 854                         p = host->regs->main_area[0] + (col & ~3);
 855                 } else {
 856                         p = host->regs->spare_area[0] -
 857                                                 mtd->writesize + (col & ~3);
 858                 }
 859
 860                 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
 861                       __LINE__, p);
 862
 863                 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
 864                         union {
 865                                 uint32_t word;
 866                                 uint8_t bytes[4];
 867                         } nfc_word;
 868
 869                         nfc_word.word = readl(p);
 870                         nfc_word.bytes[col & 3] = buf[i++];
 871                         n--;
 872                         col++;
 873
 874                         writel(nfc_word.word, p);
 875                 } else {
 876                         int m = mtd->writesize - col;
 877
 878                         if (col >= mtd->writesize)
 879                                 m += mtd->oobsize;
 880
 881                         m = min(n, m) & ~3;
 882
 883                         MTDDEBUG(MTD_DEBUG_LEVEL3,
 884                               "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 885                               __func__,  __LINE__, n, m, i, col);
 886
 887                         mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
 888                         col += m;
 889                         i += m;
 890                         n -= m;
 891                 }
 892         }
 893         /* Update saved column address */
 894         host->col_addr = col;
 895 }
 896
 897 /*
 898  * Read the data buffer from the NAND Flash. To read the data from NAND
 899  * Flash first the data output cycle is initiated by the NFC, which copies
 900  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 901  */
 902 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 903 {
 904         struct nand_chip *nand_chip = mtd->priv;
 905         struct mxc_nand_host *host = nand_chip->priv;
 906         int n, col, i = 0;
 907
 908         MTDDEBUG(MTD_DEBUG_LEVEL3,
 909               "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
 910
 911         col = host->col_addr;
 912
 913         /* Adjust saved column address */
 914         if (col < mtd->writesize && host->spare_only)
 915                 col += mtd->writesize;
 916
 917         n = mtd->writesize + mtd->oobsize - col;
 918         n = min(len, n);
 919
 920         while (n > 0) {
 921                 void __iomem *p;
 922
 923                 if (col < mtd->writesize) {
 924                         p = host->regs->main_area[0] + (col & ~3);
 925                 } else {
 926                         p = host->regs->spare_area[0] -
 927                                         mtd->writesize + (col & ~3);
 928                 }
 929
 930                 if (((col | (int)&buf[i]) & 3) || n < 4) {
 931                         union {
 932                                 uint32_t word;
 933                                 uint8_t bytes[4];
 934                         } nfc_word;
 935
 936                         nfc_word.word = readl(p);
 937                         buf[i++] = nfc_word.bytes[col & 3];
 938                         n--;
 939                         col++;
 940                 } else {
 941                         int m = mtd->writesize - col;
 942
 943                         if (col >= mtd->writesize)
 944                                 m += mtd->oobsize;
 945
 946                         m = min(n, m) & ~3;
 947                         mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
 948
 949                         col += m;
 950                         i += m;
 951                         n -= m;
 952                 }
 953         }
 954         /* Update saved column address */
 955         host->col_addr = col;
 956 }
 957
 958 /*
 959  * Used by the upper layer to verify the data in NAND Flash
 960  * with the data in the buf.
 961  */
 962 static int mxc_nand_verify_buf(struct mtd_info *mtd,
 963                                 const u_char *buf, int len)
 964 {
 965         u_char tmp[256];
 966         uint bsize;
 967
 968         while (len) {
 969                 bsize = min(len, 256);
 970                 mxc_nand_read_buf(mtd, tmp, bsize);
 971
 972                 if (memcmp(buf, tmp, bsize))
 973                         return 1;
 974
 975                 buf += bsize;
 976                 len -= bsize;
 977         }
 978
 979         return 0;
 980 }
 981
 982 /*
 983  * This function is used by upper layer for select and
 984  * deselect of the NAND chip
 985  */
 986 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 987 {
 988         struct nand_chip *nand_chip = mtd->priv;
 989         struct mxc_nand_host *host = nand_chip->priv;
 990
 991         switch (chip) {
 992         case -1:
 993                 /* TODO: Disable the NFC clock */
 994                 if (host->clk_act)
 995                         host->clk_act = 0;
 996                 break;
 997         case 0:
 998                 /* TODO: Enable the NFC clock */
 999                 if (!host->clk_act)
1000                         host->clk_act = 1;
1001                 break;
1002
1003         default:
1004                 break;
1005         }
1006 }
1007
1008 /*
1009  * Used by the upper layer to write command to NAND Flash for
1010  * different operations to be carried out on NAND Flash
1011  */
1012 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1013                                 int column, int page_addr)
1014 {
1015         struct nand_chip *nand_chip = mtd->priv;
1016         struct mxc_nand_host *host = nand_chip->priv;
1017
1018         MTDDEBUG(MTD_DEBUG_LEVEL3,
1019               "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1020               command, column, page_addr);
1021
1022         /* Reset command state information */
1023         host->status_request = false;
1024
1025         /* Command pre-processing step */
1026         switch (command) {
1027
1028         case NAND_CMD_STATUS:
1029                 host->col_addr = 0;
1030                 host->status_request = true;
1031                 break;
1032
1033         case NAND_CMD_READ0:
1034                 host->page_addr = page_addr;
1035                 host->col_addr = column;
1036                 host->spare_only = false;
1037                 break;
1038
1039         case NAND_CMD_READOOB:
1040                 host->col_addr = column;
1041                 host->spare_only = true;
1042                 if (host->pagesize_2k)
1043                         command = NAND_CMD_READ0; /* only READ0 is valid */
1044                 break;
1045
1046         case NAND_CMD_SEQIN:
1047                 if (column >= mtd->writesize) {
1048                         /*
1049                          * before sending SEQIN command for partial write,
1050                          * we need read one page out. FSL NFC does not support
1051                          * partial write. It always sends out 512+ecc+512+ecc
1052                          * for large page nand flash. But for small page nand
1053                          * flash, it does support SPARE ONLY operation.
1054                          */
1055                         if (host->pagesize_2k) {
1056                                 /* call ourself to read a page */
1057                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1058                                                 page_addr);
1059                         }
1060
1061                         host->col_addr = column - mtd->writesize;
1062                         host->spare_only = true;
1063
1064                         /* Set program pointer to spare region */
1065                         if (!host->pagesize_2k)
1066                                 send_cmd(host, NAND_CMD_READOOB);
1067                 } else {
1068                         host->spare_only = false;
1069                         host->col_addr = column;
1070
1071                         /* Set program pointer to page start */
1072                         if (!host->pagesize_2k)
1073                                 send_cmd(host, NAND_CMD_READ0);
1074                 }
1075                 break;
1076
1077         case NAND_CMD_PAGEPROG:
1078                 send_prog_page(host, 0, host->spare_only);
1079
1080                 if (host->pagesize_2k && is_mxc_nfc_1()) {
1081                         /* data in 4 areas */
1082                         send_prog_page(host, 1, host->spare_only);
1083                         send_prog_page(host, 2, host->spare_only);
1084                         send_prog_page(host, 3, host->spare_only);
1085                 }
1086
1087                 break;
1088         }
1089
1090         /* Write out the command to the device. */
1091         send_cmd(host, command);
1092
1093         /* Write out column address, if necessary */
1094         if (column != -1) {
1095                 /*
1096                  * MXC NANDFC can only perform full page+spare or
1097                  * spare-only read/write. When the upper layers perform
1098                  * a read/write buffer operation, we will use the saved
1099                  * column address to index into the full page.
1100                  */
1101                 send_addr(host, 0);
1102                 if (host->pagesize_2k)
1103                         /* another col addr cycle for 2k page */
1104                         send_addr(host, 0);
1105         }
1106
1107         /* Write out page address, if necessary */
1108         if (page_addr != -1) {
1109                 u32 page_mask = nand_chip->pagemask;
1110                 do {
1111                         send_addr(host, page_addr & 0xFF);
1112                         page_addr >>= 8;
1113                         page_mask >>= 8;
1114                 } while (page_mask);
1115         }
1116
1117         /* Command post-processing step */
1118         switch (command) {
1119
1120         case NAND_CMD_RESET:
1121                 break;
1122
1123         case NAND_CMD_READOOB:
1124         case NAND_CMD_READ0:
1125                 if (host->pagesize_2k) {
1126                         /* send read confirm command */
1127                         send_cmd(host, NAND_CMD_READSTART);
1128                         /* read for each AREA */
1129                         send_read_page(host, 0, host->spare_only);
1130                         if (is_mxc_nfc_1()) {
1131                                 send_read_page(host, 1, host->spare_only);
1132                                 send_read_page(host, 2, host->spare_only);
1133                                 send_read_page(host, 3, host->spare_only);
1134                         }
1135                 } else {
1136                         send_read_page(host, 0, host->spare_only);
1137                 }
1138                 break;
1139
1140         case NAND_CMD_READID:
1141                 host->col_addr = 0;
1142                 send_read_id(host);
1143                 break;
1144
1145         case NAND_CMD_PAGEPROG:
1146                 break;
1147
1148         case NAND_CMD_STATUS:
1149                 break;
1150
1151         case NAND_CMD_ERASE2:
1152                 break;
1153         }
1154 }
1155
1156 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1157
1158 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1159 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1160
1161 static struct nand_bbt_descr bbt_main_descr = {
1162         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1163                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1164         .offs = 0,
1165         .len = 4,
1166         .veroffs = 4,
1167         .maxblocks = 4,
1168         .pattern = bbt_pattern,
1169 };
1170
1171 static struct nand_bbt_descr bbt_mirror_descr = {
1172         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1173                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1174         .offs = 0,
1175         .len = 4,
1176         .veroffs = 4,
1177         .maxblocks = 4,
1178         .pattern = mirror_pattern,
1179 };
1180
1181 #endif
1182
1183 int board_nand_init(struct nand_chip *this)
1184 {
1185         struct mtd_info *mtd;
1186 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1187         uint32_t tmp;
1188 #endif
1189
1190 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1191         this->options |= NAND_USE_FLASH_BBT;
1192         this->bbt_td = &bbt_main_descr;
1193         this->bbt_md = &bbt_mirror_descr;
1194 #endif
1195
1196         /* structures must be linked */
1197         mtd = &host->mtd;
1198         mtd->priv = this;
1199         host->nand = this;
1200
1201         /* 5 us command delay time */
1202         this->chip_delay = 5;
1203
1204         this->priv = host;
1205         this->dev_ready = mxc_nand_dev_ready;
1206         this->cmdfunc = mxc_nand_command;
1207         this->select_chip = mxc_nand_select_chip;
1208         this->read_byte = mxc_nand_read_byte;
1209         this->read_word = mxc_nand_read_word;
1210         this->write_buf = mxc_nand_write_buf;
1211         this->read_buf = mxc_nand_read_buf;
1212         this->verify_buf = mxc_nand_verify_buf;
1213
1214         host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1215 #ifdef MXC_NFC_V3_2
1216         host->ip_regs =
1217                 (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1218 #endif
1219         host->clk_act = 1;
1220
1221 #ifdef CONFIG_MXC_NAND_HWECC
1222         this->ecc.calculate = mxc_nand_calculate_ecc;
1223         this->ecc.hwctl = mxc_nand_enable_hwecc;
1224         this->ecc.correct = mxc_nand_correct_data;
1225         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
1226                 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1227                 this->ecc.read_page = mxc_nand_read_page_syndrome;
1228                 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1229                 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1230                 this->ecc.write_page = mxc_nand_write_page_syndrome;
1231                 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1232                 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1233                 this->ecc.bytes = 9;
1234                 this->ecc.prepad = 7;
1235         } else {
1236                 this->ecc.mode = NAND_ECC_HW;
1237         }
1238
1239         host->pagesize_2k = 0;
1240
1241         this->ecc.size = 512;
1242         _mxc_nand_enable_hwecc(mtd, 1);
1243 #else
1244         this->ecc.layout = &nand_soft_eccoob;
1245         this->ecc.mode = NAND_ECC_SOFT;
1246         _mxc_nand_enable_hwecc(mtd, 0);
1247 #endif
1248         /* Reset NAND */
1249         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1250
1251         /* NAND bus width determines access functions used by upper layer */
1252         if (is_16bit_nand())
1253                 this->options |= NAND_BUSWIDTH_16;
1254
1255 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1256         host->pagesize_2k = 1;
1257         this->ecc.layout = &nand_hw_eccoob2k;
1258 #else
1259         host->pagesize_2k = 0;
1260         this->ecc.layout = &nand_hw_eccoob;
1261 #endif
1262
1263 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
1264 #ifdef MXC_NFC_V2_1
1265         tmp = readnfc(&host->regs->config1);
1266         tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
1267         tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
1268         writenfc(tmp, &host->regs->config1);
1269         if (host->pagesize_2k)
1270                 writenfc(64/2, &host->regs->spare_area_size);
1271         else
1272                 writenfc(16/2, &host->regs->spare_area_size);
1273 #endif
1274
1275         /*
1276          * preset operation
1277          * Unlock the internal RAM Buffer
1278          */
1279         writenfc(0x2, &host->regs->config);
1280
1281         /* Blocks to be unlocked */
1282         writenfc(0x0, &host->regs->unlockstart_blkaddr);
1283         /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1284          * unlockend_blkaddr, but the magic 0x4000 does not always work
1285          * when writing more than some 32 megabytes (on 2k page nands)
1286          * However 0xFFFF doesn't seem to have this kind
1287          * of limitation (tried it back and forth several times).
1288          * The linux kernel driver sets this to 0xFFFF for the v2 controller
1289          * only, but probably this was not tested there for v1.
1290          * The very same limitation seems to apply to this kernel driver.
1291          * This might be NAND chip specific and the i.MX31 datasheet is
1292          * extremely vague about the semantics of this register.
1293          */
1294         writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
1295
1296         /* Unlock Block Command for given address range */
1297         writenfc(0x4, &host->regs->wrprot);
1298 #elif defined(MXC_NFC_V3_2)
1299         writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1300         writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1301
1302         /* Unlock the internal RAM Buffer */
1303         writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1304                         &host->ip_regs->wrprot);
1305
1306         /* Blocks to be unlocked */
1307         for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
1308                 writenfc(0x0 | 0xFFFF << 16,
1309                                 &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1310
1311         writenfc(0, &host->ip_regs->ipc);
1312
1313         tmp = readnfc(&host->ip_regs->config2);
1314         tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
1315                         NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
1316         tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
1317
1318         if (host->pagesize_2k) {
1319                 tmp |= NFC_V3_CONFIG2_SPAS(64/2);
1320                 tmp |= NFC_V3_CONFIG2_PS_2048;
1321         } else {
1322                 tmp |= NFC_V3_CONFIG2_SPAS(16/2);
1323                 tmp |= NFC_V3_CONFIG2_PS_512;
1324         }
1325
1326         writenfc(tmp, &host->ip_regs->config2);
1327
1328         tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1329                         NFC_V3_CONFIG3_NO_SDMA |
1330                         NFC_V3_CONFIG3_RBB_MODE |
1331                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1332                         NFC_V3_CONFIG3_ADD_OP(0);
1333
1334         if (!(this->options & NAND_BUSWIDTH_16))
1335                 tmp |= NFC_V3_CONFIG3_FW8;
1336
1337         writenfc(tmp, &host->ip_regs->config3);
1338
1339         writenfc(0, &host->ip_regs->delay_line);
1340 #endif
1341
1342         return 0;
1343 }