git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  18  * MA 02110-1301, USA.
  19  */
  20
  21 #include <common.h>
  22 #include <nand.h>
  23 #include <linux/err.h>
  24 #include <asm/io.h>
  25 #ifdef CONFIG_MX27
  26 #include <asm/arch/imx-regs.h>
  27 #endif
  28
  29 #define DRIVER_NAME "mxc_nand"
  30
  31 struct nfc_regs {
  32 /* NFC RAM BUFFER Main area 0 */
  33         uint8_t main_area0[0x200];
  34         uint8_t main_area1[0x200];
  35         uint8_t main_area2[0x200];
  36         uint8_t main_area3[0x200];
  37 /* SPARE BUFFER Spare area 0 */
  38         uint8_t spare_area0[0x10];
  39         uint8_t spare_area1[0x10];
  40         uint8_t spare_area2[0x10];
  41         uint8_t spare_area3[0x10];
  42         uint8_t pad[0x5c0];
  43 /* NFC registers */
  44         uint16_t nfc_buf_size;
  45         uint16_t reserved;
  46         uint16_t nfc_buf_addr;
  47         uint16_t nfc_flash_addr;
  48         uint16_t nfc_flash_cmd;
  49         uint16_t nfc_config;
  50         uint16_t nfc_ecc_status_result;
  51         uint16_t nfc_rsltmain_area;
  52         uint16_t nfc_rsltspare_area;
  53         uint16_t nfc_wrprot;
  54         uint16_t nfc_unlockstart_blkaddr;
  55         uint16_t nfc_unlockend_blkaddr;
  56         uint16_t nfc_nf_wrprst;
  57         uint16_t nfc_config1;
  58         uint16_t nfc_config2;
  59 };
  60
  61 /*
  62  * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
  63  * for Command operation
  64  */
  65 #define NFC_CMD            0x1
  66
  67 /*
  68  * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
  69  * for Address operation
  70  */
  71 #define NFC_ADDR           0x2
  72
  73 /*
  74  * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
  75  * for Input operation
  76  */
  77 #define NFC_INPUT          0x4
  78
  79 /*
  80  * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
  81  * for Data Output operation
  82  */
  83 #define NFC_OUTPUT         0x8
  84
  85 /*
  86  * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
  87  * for Read ID operation
  88  */
  89 #define NFC_ID             0x10
  90
  91 /*
  92  * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
  93  * for Read Status operation
  94  */
  95 #define NFC_STATUS         0x20
  96
  97 /*
  98  * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
  99  * Status operation
 100  */
 101 #define NFC_INT            0x8000
 102
 103 #define NFC_SP_EN           (1 << 2)
 104 #define NFC_ECC_EN          (1 << 3)
 105 #define NFC_BIG             (1 << 5)
 106 #define NFC_RST             (1 << 6)
 107 #define NFC_CE              (1 << 7)
 108 #define NFC_ONE_CYCLE       (1 << 8)
 109
 110 typedef enum {false, true} bool;
 111
 112 struct mxc_nand_host {
 113         struct mtd_info         mtd;
 114         struct nand_chip        *nand;
 115
 116         struct nfc_regs __iomem *regs;
 117         int                     spare_only;
 118         int                     status_request;
 119         int                     pagesize_2k;
 120         int                     clk_act;
 121         uint16_t                col_addr;
 122 };
 123
 124 static struct mxc_nand_host mxc_host;
 125 static struct mxc_nand_host *host = &mxc_host;
 126
 127 /* Define delays in microsec for NAND device operations */
 128 #define TROP_US_DELAY   2000
 129 /* Macros to get byte and bit positions of ECC */
 130 #define COLPOS(x)  ((x) >> 3)
 131 #define BITPOS(x) ((x) & 0xf)
 132
 133 /* Define single bit Error positions in Main & Spare area */
 134 #define MAIN_SINGLEBIT_ERROR 0x4
 135 #define SPARE_SINGLEBIT_ERROR 0x1
 136
 137 /* OOB placement block for use with hardware ecc generation */
 138 #ifdef CONFIG_MXC_NAND_HWECC
 139 static struct nand_ecclayout nand_hw_eccoob = {
 140         .eccbytes = 5,
 141         .eccpos = {6, 7, 8, 9, 10},
 142         .oobfree = {{0, 5}, {11, 5}, }
 143 };
 144 #else
 145 static struct nand_ecclayout nand_soft_eccoob = {
 146         .eccbytes = 6,
 147         .eccpos = {6, 7, 8, 9, 10, 11},
 148         .oobfree = {{0, 5}, {12, 4}, }
 149 };
 150 #endif
 151
 152 #ifdef CONFIG_MX27
 153 static int is_16bit_nand(void)
 154 {
 155         struct system_control_regs *sc_regs =
 156                 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
 157
 158         if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
 159                 return 1;
 160         else
 161                 return 0;
 162 }
 163 #elif defined(CONFIG_MX31)
 164 static int is_16bit_nand(void)
 165 {
 166         struct clock_control_regs *sc_regs =
 167                 (struct clock_control_regs *)CCM_BASE;
 168
 169         if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
 170                 return 1;
 171         else
 172                 return 0;
 173 }
 174 #else
 175 #warning "8/16 bit NAND autodetection not supported"
 176 static int is_16bit_nand(void)
 177 {
 178         return 0;
 179 }
 180 #endif
 181
 182 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
 183 {
 184         uint32_t *d = dest;
 185
 186         size >>= 2;
 187         while (size--)
 188                 __raw_writel(__raw_readl(source++), d++);
 189         return dest;
 190 }
 191
 192 /*
 193  * This function polls the NANDFC to wait for the basic operation to
 194  * complete by checking the INT bit of config2 register.
 195  */
 196 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 197                                 uint16_t param)
 198 {
 199         uint32_t tmp;
 200
 201         while (max_retries-- > 0) {
 202                 if (readw(&host->regs->nfc_config2) & NFC_INT) {
 203                         tmp = readw(&host->regs->nfc_config2);
 204                         tmp  &= ~NFC_INT;
 205                         writew(tmp, &host->regs->nfc_config2);
 206                         break;
 207                 }
 208                 udelay(1);
 209         }
 210         if (max_retries < 0) {
 211                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
 212                                 __func__, param);
 213         }
 214 }
 215
 216 /*
 217  * This function issues the specified command to the NAND device and
 218  * waits for completion.
 219  */
 220 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
 221 {
 222         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
 223
 224         writew(cmd, &host->regs->nfc_flash_cmd);
 225         writew(NFC_CMD, &host->regs->nfc_config2);
 226
 227         /* Wait for operation to complete */
 228         wait_op_done(host, TROP_US_DELAY, cmd);
 229 }
 230
 231 /*
 232  * This function sends an address (or partial address) to the
 233  * NAND device. The address is used to select the source/destination for
 234  * a NAND command.
 235  */
 236 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
 237 {
 238         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
 239
 240         writew(addr, &host->regs->nfc_flash_addr);
 241         writew(NFC_ADDR, &host->regs->nfc_config2);
 242
 243         /* Wait for operation to complete */
 244         wait_op_done(host, TROP_US_DELAY, addr);
 245 }
 246
 247 /*
 248  * This function requests the NANDFC to initate the transfer
 249  * of data currently in the NANDFC RAM buffer to the NAND device.
 250  */
 251 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 252                         int spare_only)
 253 {
 254         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
 255
 256         writew(buf_id, &host->regs->nfc_buf_addr);
 257
 258         /* Configure spare or page+spare access */
 259         if (!host->pagesize_2k) {
 260                 uint16_t config1 = readw(&host->regs->nfc_config1);
 261                 if (spare_only)
 262                         config1 |= NFC_SP_EN;
 263                 else
 264                         config1 &= ~(NFC_SP_EN);
 265                 writew(config1, &host->regs->nfc_config1);
 266         }
 267
 268         writew(NFC_INPUT, &host->regs->nfc_config2);
 269
 270         /* Wait for operation to complete */
 271         wait_op_done(host, TROP_US_DELAY, spare_only);
 272 }
 273
 274 /*
 275  * Requests NANDFC to initated the transfer of data from the
 276  * NAND device into in the NANDFC ram buffer.
 277  */
 278 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 279                 int spare_only)
 280 {
 281         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
 282
 283         writew(buf_id, &host->regs->nfc_buf_addr);
 284
 285         /* Configure spare or page+spare access */
 286         if (!host->pagesize_2k) {
 287                 uint32_t config1 = readw(&host->regs->nfc_config1);
 288                 if (spare_only)
 289                         config1 |= NFC_SP_EN;
 290                 else
 291                         config1 &= ~NFC_SP_EN;
 292                 writew(config1, &host->regs->nfc_config1);
 293         }
 294
 295         writew(NFC_OUTPUT, &host->regs->nfc_config2);
 296
 297         /* Wait for operation to complete */
 298         wait_op_done(host, TROP_US_DELAY, spare_only);
 299 }
 300
 301 /* Request the NANDFC to perform a read of the NAND device ID. */
 302 static void send_read_id(struct mxc_nand_host *host)
 303 {
 304         uint16_t tmp;
 305
 306         /* NANDFC buffer 0 is used for device ID output */
 307         writew(0x0, &host->regs->nfc_buf_addr);
 308
 309         /* Read ID into main buffer */
 310         tmp = readw(&host->regs->nfc_config1);
 311         tmp &= ~NFC_SP_EN;
 312         writew(tmp, &host->regs->nfc_config1);
 313
 314         writew(NFC_ID, &host->regs->nfc_config2);
 315
 316         /* Wait for operation to complete */
 317         wait_op_done(host, TROP_US_DELAY, 0);
 318 }
 319
 320 /*
 321  * This function requests the NANDFC to perform a read of the
 322  * NAND device status and returns the current status.
 323  */
 324 static uint16_t get_dev_status(struct mxc_nand_host *host)
 325 {
 326         void __iomem *main_buf = host->regs->main_area1;
 327         uint32_t store;
 328         uint16_t ret, tmp;
 329         /* Issue status request to NAND device */
 330
 331         /* store the main area1 first word, later do recovery */
 332         store = readl(main_buf);
 333         /* NANDFC buffer 1 is used for device status */
 334         writew(1, &host->regs->nfc_buf_addr);
 335
 336         /* Read status into main buffer */
 337         tmp = readw(&host->regs->nfc_config1);
 338         tmp &= ~NFC_SP_EN;
 339         writew(tmp, &host->regs->nfc_config1);
 340
 341         writew(NFC_STATUS, &host->regs->nfc_config2);
 342
 343         /* Wait for operation to complete */
 344         wait_op_done(host, TROP_US_DELAY, 0);
 345
 346         /*
 347          *  Status is placed in first word of main buffer
 348          * get status, then recovery area 1 data
 349          */
 350         ret = readw(main_buf);
 351         writel(store, main_buf);
 352
 353         return ret;
 354 }
 355
 356 /* This function is used by upper layer to checks if device is ready */
 357 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 358 {
 359         /*
 360          * NFC handles R/B internally. Therefore, this function
 361          * always returns status as ready.
 362          */
 363         return 1;
 364 }
 365
 366 #ifdef CONFIG_MXC_NAND_HWECC
 367 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 368 {
 369         /*
 370          * If HW ECC is enabled, we turn it on during init. There is
 371          * no need to enable again here.
 372          */
 373 }
 374
 375 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 376                                  u_char *read_ecc, u_char *calc_ecc)
 377 {
 378         struct nand_chip *nand_chip = mtd->priv;
 379         struct mxc_nand_host *host = nand_chip->priv;
 380
 381         /*
 382          * 1-Bit errors are automatically corrected in HW.  No need for
 383          * additional correction.  2-Bit errors cannot be corrected by
 384          * HW ECC, so we need to return failure
 385          */
 386         uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
 387
 388         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 389                 MTDDEBUG(MTD_DEBUG_LEVEL0,
 390                       "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 391                 return -1;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 398                                   u_char *ecc_code)
 399 {
 400         return 0;
 401 }
 402 #endif
 403
 404 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 405 {
 406         struct nand_chip *nand_chip = mtd->priv;
 407         struct mxc_nand_host *host = nand_chip->priv;
 408         uint8_t ret = 0;
 409         uint16_t col;
 410         uint16_t __iomem *main_buf =
 411                 (uint16_t __iomem *)host->regs->main_area0;
 412         uint16_t __iomem *spare_buf =
 413                 (uint16_t __iomem *)host->regs->spare_area0;
 414         union {
 415                 uint16_t word;
 416                 uint8_t bytes[2];
 417         } nfc_word;
 418
 419         /* Check for status request */
 420         if (host->status_request)
 421                 return get_dev_status(host) & 0xFF;
 422
 423         /* Get column for 16-bit access */
 424         col = host->col_addr >> 1;
 425
 426         /* If we are accessing the spare region */
 427         if (host->spare_only)
 428                 nfc_word.word = readw(&spare_buf[col]);
 429         else
 430                 nfc_word.word = readw(&main_buf[col]);
 431
 432         /* Pick upper/lower byte of word from RAM buffer */
 433         ret = nfc_word.bytes[host->col_addr & 0x1];
 434
 435         /* Update saved column address */
 436         if (nand_chip->options & NAND_BUSWIDTH_16)
 437                 host->col_addr += 2;
 438         else
 439                 host->col_addr++;
 440
 441         return ret;
 442 }
 443
 444 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 445 {
 446         struct nand_chip *nand_chip = mtd->priv;
 447         struct mxc_nand_host *host = nand_chip->priv;
 448         uint16_t col, ret;
 449         uint16_t __iomem *p;
 450
 451         MTDDEBUG(MTD_DEBUG_LEVEL3,
 452               "mxc_nand_read_word(col = %d)\n", host->col_addr);
 453
 454         col = host->col_addr;
 455         /* Adjust saved column address */
 456         if (col < mtd->writesize && host->spare_only)
 457                 col += mtd->writesize;
 458
 459         if (col < mtd->writesize) {
 460                 p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
 461         } else {
 462                 p = (uint16_t __iomem *)(host->regs->spare_area0 +
 463                                 ((col - mtd->writesize) >> 1));
 464         }
 465
 466         if (col & 1) {
 467                 union {
 468                         uint16_t word;
 469                         uint8_t bytes[2];
 470                 } nfc_word[3];
 471
 472                 nfc_word[0].word = readw(p);
 473                 nfc_word[1].word = readw(p + 1);
 474
 475                 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
 476                 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
 477
 478                 ret = nfc_word[2].word;
 479         } else {
 480                 ret = readw(p);
 481         }
 482
 483         /* Update saved column address */
 484         host->col_addr = col + 2;
 485
 486         return ret;
 487 }
 488
 489 /*
 490  * Write data of length len to buffer buf. The data to be
 491  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 492  * Operation by the NFC, the data is written to NAND Flash
 493  */
 494 static void mxc_nand_write_buf(struct mtd_info *mtd,
 495                                 const u_char *buf, int len)
 496 {
 497         struct nand_chip *nand_chip = mtd->priv;
 498         struct mxc_nand_host *host = nand_chip->priv;
 499         int n, col, i = 0;
 500
 501         MTDDEBUG(MTD_DEBUG_LEVEL3,
 502               "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 503               len);
 504
 505         col = host->col_addr;
 506
 507         /* Adjust saved column address */
 508         if (col < mtd->writesize && host->spare_only)
 509                 col += mtd->writesize;
 510
 511         n = mtd->writesize + mtd->oobsize - col;
 512         n = min(len, n);
 513
 514         MTDDEBUG(MTD_DEBUG_LEVEL3,
 515               "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 516
 517         while (n > 0) {
 518                 void __iomem *p;
 519
 520                 if (col < mtd->writesize) {
 521                         p = host->regs->main_area0 + (col & ~3);
 522                 } else {
 523                         p = host->regs->spare_area0 -
 524                                                 mtd->writesize + (col & ~3);
 525                 }
 526
 527                 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
 528                       __LINE__, p);
 529
 530                 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
 531                         union {
 532                                 uint32_t word;
 533                                 uint8_t bytes[4];
 534                         } nfc_word;
 535
 536                         nfc_word.word = readl(p);
 537                         nfc_word.bytes[col & 3] = buf[i++];
 538                         n--;
 539                         col++;
 540
 541                         writel(nfc_word.word, p);
 542                 } else {
 543                         int m = mtd->writesize - col;
 544
 545                         if (col >= mtd->writesize)
 546                                 m += mtd->oobsize;
 547
 548                         m = min(n, m) & ~3;
 549
 550                         MTDDEBUG(MTD_DEBUG_LEVEL3,
 551                               "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 552                               __func__,  __LINE__, n, m, i, col);
 553
 554                         mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
 555                         col += m;
 556                         i += m;
 557                         n -= m;
 558                 }
 559         }
 560         /* Update saved column address */
 561         host->col_addr = col;
 562 }
 563
 564 /*
 565  * Read the data buffer from the NAND Flash. To read the data from NAND
 566  * Flash first the data output cycle is initiated by the NFC, which copies
 567  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 568  */
 569 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 570 {
 571         struct nand_chip *nand_chip = mtd->priv;
 572         struct mxc_nand_host *host = nand_chip->priv;
 573         int n, col, i = 0;
 574
 575         MTDDEBUG(MTD_DEBUG_LEVEL3,
 576               "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
 577
 578         col = host->col_addr;
 579
 580         /* Adjust saved column address */
 581         if (col < mtd->writesize && host->spare_only)
 582                 col += mtd->writesize;
 583
 584         n = mtd->writesize + mtd->oobsize - col;
 585         n = min(len, n);
 586
 587         while (n > 0) {
 588                 void __iomem *p;
 589
 590                 if (col < mtd->writesize) {
 591                         p = host->regs->main_area0 + (col & ~3);
 592                 } else {
 593                         p = host->regs->spare_area0 -
 594                                         mtd->writesize + (col & ~3);
 595                 }
 596
 597                 if (((col | (int)&buf[i]) & 3) || n < 4) {
 598                         union {
 599                                 uint32_t word;
 600                                 uint8_t bytes[4];
 601                         } nfc_word;
 602
 603                         nfc_word.word = readl(p);
 604                         buf[i++] = nfc_word.bytes[col & 3];
 605                         n--;
 606                         col++;
 607                 } else {
 608                         int m = mtd->writesize - col;
 609
 610                         if (col >= mtd->writesize)
 611                                 m += mtd->oobsize;
 612
 613                         m = min(n, m) & ~3;
 614                         mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
 615
 616                         col += m;
 617                         i += m;
 618                         n -= m;
 619                 }
 620         }
 621         /* Update saved column address */
 622         host->col_addr = col;
 623 }
 624
 625 /*
 626  * Used by the upper layer to verify the data in NAND Flash
 627  * with the data in the buf.
 628  */
 629 static int mxc_nand_verify_buf(struct mtd_info *mtd,
 630                                 const u_char *buf, int len)
 631 {
 632         u_char tmp[256];
 633         uint bsize;
 634
 635         while (len) {
 636                 bsize = min(len, 256);
 637                 mxc_nand_read_buf(mtd, tmp, bsize);
 638
 639                 if (memcmp(buf, tmp, bsize))
 640                         return 1;
 641
 642                 buf += bsize;
 643                 len -= bsize;
 644         }
 645
 646         return 0;
 647 }
 648
 649 /*
 650  * This function is used by upper layer for select and
 651  * deselect of the NAND chip
 652  */
 653 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 654 {
 655         struct nand_chip *nand_chip = mtd->priv;
 656         struct mxc_nand_host *host = nand_chip->priv;
 657
 658         switch (chip) {
 659         case -1:
 660                 /* TODO: Disable the NFC clock */
 661                 if (host->clk_act)
 662                         host->clk_act = 0;
 663                 break;
 664         case 0:
 665                 /* TODO: Enable the NFC clock */
 666                 if (!host->clk_act)
 667                         host->clk_act = 1;
 668                 break;
 669
 670         default:
 671                 break;
 672         }
 673 }
 674
 675 /*
 676  * Used by the upper layer to write command to NAND Flash for
 677  * different operations to be carried out on NAND Flash
 678  */
 679 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 680                                 int column, int page_addr)
 681 {
 682         struct nand_chip *nand_chip = mtd->priv;
 683         struct mxc_nand_host *host = nand_chip->priv;
 684
 685         MTDDEBUG(MTD_DEBUG_LEVEL3,
 686               "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 687               command, column, page_addr);
 688
 689         /* Reset command state information */
 690         host->status_request = false;
 691
 692         /* Command pre-processing step */
 693         switch (command) {
 694
 695         case NAND_CMD_STATUS:
 696                 host->col_addr = 0;
 697                 host->status_request = true;
 698                 break;
 699
 700         case NAND_CMD_READ0:
 701                 host->col_addr = column;
 702                 host->spare_only = false;
 703                 break;
 704
 705         case NAND_CMD_READOOB:
 706                 host->col_addr = column;
 707                 host->spare_only = true;
 708                 if (host->pagesize_2k)
 709                         command = NAND_CMD_READ0; /* only READ0 is valid */
 710                 break;
 711
 712         case NAND_CMD_SEQIN:
 713                 if (column >= mtd->writesize) {
 714                         /*
 715                          * before sending SEQIN command for partial write,
 716                          * we need read one page out. FSL NFC does not support
 717                          * partial write. It alway send out 512+ecc+512+ecc ...
 718                          * for large page nand flash. But for small page nand
 719                          * flash, it does support SPARE ONLY operation.
 720                          */
 721                         if (host->pagesize_2k) {
 722                                 /* call ourself to read a page */
 723                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
 724                                                 page_addr);
 725                         }
 726
 727                         host->col_addr = column - mtd->writesize;
 728                         host->spare_only = true;
 729
 730                         /* Set program pointer to spare region */
 731                         if (!host->pagesize_2k)
 732                                 send_cmd(host, NAND_CMD_READOOB);
 733                 } else {
 734                         host->spare_only = false;
 735                         host->col_addr = column;
 736
 737                         /* Set program pointer to page start */
 738                         if (!host->pagesize_2k)
 739                                 send_cmd(host, NAND_CMD_READ0);
 740                 }
 741                 break;
 742
 743         case NAND_CMD_PAGEPROG:
 744                 send_prog_page(host, 0, host->spare_only);
 745
 746                 if (host->pagesize_2k) {
 747                         /* data in 4 areas datas */
 748                         send_prog_page(host, 1, host->spare_only);
 749                         send_prog_page(host, 2, host->spare_only);
 750                         send_prog_page(host, 3, host->spare_only);
 751                 }
 752
 753                 break;
 754         }
 755
 756         /* Write out the command to the device. */
 757         send_cmd(host, command);
 758
 759         /* Write out column address, if necessary */
 760         if (column != -1) {
 761                 /*
 762                  * MXC NANDFC can only perform full page+spare or
 763                  * spare-only read/write.  When the upper layers
 764                  * layers perform a read/write buf operation,
 765                  * we will used the saved column adress to index into
 766                  * the full page.
 767                  */
 768                 send_addr(host, 0);
 769                 if (host->pagesize_2k)
 770                         /* another col addr cycle for 2k page */
 771                         send_addr(host, 0);
 772         }
 773
 774         /* Write out page address, if necessary */
 775         if (page_addr != -1) {
 776                 /* paddr_0 - p_addr_7 */
 777                 send_addr(host, (page_addr & 0xff));
 778
 779                 if (host->pagesize_2k) {
 780                         send_addr(host, (page_addr >> 8) & 0xFF);
 781                         if (mtd->size >= 0x10000000) {
 782                                 /* paddr_8 - paddr_15 */
 783                                 send_addr(host, (page_addr >> 8) & 0xff);
 784                                 send_addr(host, (page_addr >> 16) & 0xff);
 785                         } else {
 786                                 /* paddr_8 - paddr_15 */
 787                                 send_addr(host, (page_addr >> 8) & 0xff);
 788                         }
 789                 } else {
 790                         /* One more address cycle for higher density devices */
 791                         if (mtd->size >= 0x4000000) {
 792                                 /* paddr_8 - paddr_15 */
 793                                 send_addr(host, (page_addr >> 8) & 0xff);
 794                                 send_addr(host, (page_addr >> 16) & 0xff);
 795                         } else {
 796                                 /* paddr_8 - paddr_15 */
 797                                 send_addr(host, (page_addr >> 8) & 0xff);
 798                         }
 799                 }
 800         }
 801
 802         /* Command post-processing step */
 803         switch (command) {
 804
 805         case NAND_CMD_RESET:
 806                 break;
 807
 808         case NAND_CMD_READOOB:
 809         case NAND_CMD_READ0:
 810                 if (host->pagesize_2k) {
 811                         /* send read confirm command */
 812                         send_cmd(host, NAND_CMD_READSTART);
 813                         /* read for each AREA */
 814                         send_read_page(host, 0, host->spare_only);
 815                         send_read_page(host, 1, host->spare_only);
 816                         send_read_page(host, 2, host->spare_only);
 817                         send_read_page(host, 3, host->spare_only);
 818                 } else {
 819                         send_read_page(host, 0, host->spare_only);
 820                 }
 821                 break;
 822
 823         case NAND_CMD_READID:
 824                 host->col_addr = 0;
 825                 send_read_id(host);
 826                 break;
 827
 828         case NAND_CMD_PAGEPROG:
 829                 break;
 830
 831         case NAND_CMD_STATUS:
 832                 break;
 833
 834         case NAND_CMD_ERASE2:
 835                 break;
 836         }
 837 }
 838
 839 int board_nand_init(struct nand_chip *this)
 840 {
 841         struct mtd_info *mtd;
 842         uint16_t tmp;
 843         int err = 0;
 844
 845         /* structures must be linked */
 846         mtd = &host->mtd;
 847         mtd->priv = this;
 848         host->nand = this;
 849
 850         /* 5 us command delay time */
 851         this->chip_delay = 5;
 852
 853         this->priv = host;
 854         this->dev_ready = mxc_nand_dev_ready;
 855         this->cmdfunc = mxc_nand_command;
 856         this->select_chip = mxc_nand_select_chip;
 857         this->read_byte = mxc_nand_read_byte;
 858         this->read_word = mxc_nand_read_word;
 859         this->write_buf = mxc_nand_write_buf;
 860         this->read_buf = mxc_nand_read_buf;
 861         this->verify_buf = mxc_nand_verify_buf;
 862
 863         host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
 864         host->clk_act = 1;
 865
 866 #ifdef CONFIG_MXC_NAND_HWECC
 867         this->ecc.calculate = mxc_nand_calculate_ecc;
 868         this->ecc.hwctl = mxc_nand_enable_hwecc;
 869         this->ecc.correct = mxc_nand_correct_data;
 870         this->ecc.mode = NAND_ECC_HW;
 871         this->ecc.size = 512;
 872         this->ecc.bytes = 3;
 873         this->ecc.layout = &nand_hw_eccoob;
 874         tmp = readw(&host->regs->nfc_config1);
 875         tmp |= NFC_ECC_EN;
 876         writew(tmp, &host->regs->nfc_config1);
 877 #else
 878         this->ecc.layout = &nand_soft_eccoob;
 879         this->ecc.mode = NAND_ECC_SOFT;
 880         tmp = readw(&host->regs->nfc_config1);
 881         tmp &= ~NFC_ECC_EN;
 882         writew(tmp, &host->regs->nfc_config1);
 883 #endif
 884
 885         /* Reset NAND */
 886         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 887
 888         /*
 889          * preset operation
 890          * Unlock the internal RAM Buffer
 891          */
 892         writew(0x2, &host->regs->nfc_config);
 893
 894         /* Blocks to be unlocked */
 895         writew(0x0, &host->regs->nfc_unlockstart_blkaddr);
 896         writew(0x4000, &host->regs->nfc_unlockend_blkaddr);
 897
 898         /* Unlock Block Command for given address range */
 899         writew(0x4, &host->regs->nfc_wrprot);
 900
 901         /* NAND bus width determines access funtions used by upper layer */
 902         if (is_16bit_nand())
 903                 this->options |= NAND_BUSWIDTH_16;
 904
 905         host->pagesize_2k = 0;
 906
 907         return err;
 908 }