1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
10 * Register map and bit definitions for the Freescale NAND Flash Controller
11 * present in various i.MX devices.
13 * MX31 and MX27 have version 1, which has:
14 * 4 512-byte main buffers and
15 * 4 16-byte spare buffers
16 * to support up to 2K byte pagesize nand.
17 * Reading or writing a 2K page requires 4 FDI/FDO cycles.
19 * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which
21 * 8 512-byte main buffers and
22 * 8 64-byte spare buffers
23 * to support up to 4K byte pagesize nand.
24 * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
25 * Also some of registers are moved and/or changed meaning as seen below.
27 #if defined(CONFIG_MX27) || defined(CONFIG_MX31)
29 #define is_mxc_nfc_1() 1
30 #define is_mxc_nfc_21() 0
31 #define is_mxc_nfc_32() 0
32 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
34 #define is_mxc_nfc_1() 0
35 #define is_mxc_nfc_21() 1
36 #define is_mxc_nfc_32() 0
37 #elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
40 #define is_mxc_nfc_1() 0
41 #define is_mxc_nfc_21() 0
42 #define is_mxc_nfc_32() 1
44 #error "MXC NFC implementation not supported"
46 #define is_mxc_nfc_3() is_mxc_nfc_32()
48 #if defined(MXC_NFC_V1)
49 #define NAND_MXC_NR_BUFS 4
50 #define NAND_MXC_SPARE_BUF_SIZE 16
51 #define NAND_MXC_REG_OFFSET 0xe00
52 #define NAND_MXC_2K_MULTI_CYCLE
53 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
54 #define NAND_MXC_NR_BUFS 8
55 #define NAND_MXC_SPARE_BUF_SIZE 64
56 #define NAND_MXC_REG_OFFSET 0x1e00
59 struct mxc_nand_regs {
60 u8 main_area[NAND_MXC_NR_BUFS][0x200];
61 u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
63 * reserved size is offset of nfc registers
64 * minus total main and spare sizes
66 u8 reserved1[NAND_MXC_REG_OFFSET
67 - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
68 #if defined(MXC_NFC_V1)
75 u16 ecc_status_result;
79 u16 unlockstart_blkaddr;
80 u16 unlockend_blkaddr;
84 #elif defined(MXC_NFC_V2_1)
90 u32 ecc_status_result;
98 u16 unlockstart_blkaddr;
99 u16 unlockend_blkaddr;
100 u16 unlockstart_blkaddr1;
101 u16 unlockend_blkaddr1;
102 u16 unlockstart_blkaddr2;
103 u16 unlockend_blkaddr2;
104 u16 unlockstart_blkaddr3;
105 u16 unlockend_blkaddr3;
106 #elif defined(MXC_NFC_V3_2)
110 u32 ecc_status_result;
117 struct mxc_nand_ip_regs {
119 u32 wrprot_unlock_blkaddr[8];
128 /* Set FCMD to 1, rest to 0 for Command operation */
131 /* Set FADD to 1, rest to 0 for Address operation */
134 /* Set FDI to 1, rest to 0 for Input operation */
135 #define NFC_INPUT 0x4
137 /* Set FDO to 001, rest to 0 for Data Output operation */
138 #define NFC_OUTPUT 0x8
140 /* Set FDO to 010, rest to 0 for Read ID operation */
143 /* Set FDO to 100, rest to 0 for Read Status operation */
144 #define NFC_STATUS 0x20
146 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
147 #define NFC_CONFIG1_SP_EN (1 << 2)
148 #define NFC_CONFIG1_RST (1 << 6)
149 #define NFC_CONFIG1_CE (1 << 7)
150 #elif defined(MXC_NFC_V3_2)
151 #define NFC_CONFIG1_SP_EN (1 << 0)
152 #define NFC_CONFIG1_CE (1 << 1)
153 #define NFC_CONFIG1_RST (1 << 2)
155 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
156 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
157 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
158 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
159 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
160 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
161 #define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4)
162 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4)
164 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
165 #define NFC_V3_CONFIG2_PS_MASK (0x3 << 0)
166 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
167 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
168 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
169 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
170 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
171 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
172 #define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5)
173 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
174 #define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7)
175 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
176 #define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9)
177 #define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9)
178 #define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12)
179 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
180 #define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16)
181 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
182 #define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24)
183 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
185 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
186 #define NFC_V3_CONFIG3_FW8 (1 << 3)
187 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
188 #define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12)
189 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
190 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
192 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
193 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
195 #define NFC_V3_IPC_CREQ (1 << 0)
196 #define NFC_V3_IPC_INT (1 << 31)
198 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
199 #define operation config2
200 #define readnfc readw
201 #define writenfc writew
202 #elif defined(MXC_NFC_V3_2)
203 #define operation launch
204 #define readnfc readl
205 #define writenfc writel
208 #endif /* __MXC_NAND_H */