2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/types.h>
21 #include <asm/errno.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/imx-regs.h>
25 #include <asm/imx-common/regs-bch.h>
26 #include <asm/imx-common/regs-gpmi.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/imx-common/dma.h>
30 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
32 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
33 #if defined(CONFIG_MX6)
34 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
36 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
38 #define MXS_NAND_METADATA_SIZE 10
39 #define MXS_NAND_BITS_PER_ECC_LEVEL 13
40 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
42 #define MXS_NAND_BCH_TIMEOUT 10000
44 struct mxs_nand_info {
47 uint32_t cmd_queue_len;
48 uint32_t data_buf_size;
54 uint8_t marking_block_bad;
57 /* Functions with altered behaviour */
58 int (*hooked_read_oob)(struct mtd_info *mtd,
59 loff_t from, struct mtd_oob_ops *ops);
60 int (*hooked_write_oob)(struct mtd_info *mtd,
61 loff_t to, struct mtd_oob_ops *ops);
62 int (*hooked_block_markbad)(struct mtd_info *mtd,
66 struct mxs_dma_desc **desc;
70 struct nand_ecclayout fake_ecc_layout;
71 static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
72 static int galois_field = 13;
75 * Cache management functions
77 #ifndef CONFIG_SYS_DCACHE_OFF
78 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
80 uint32_t addr = (uint32_t)info->data_buf;
82 flush_dcache_range(addr, addr + info->data_buf_size);
85 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
87 uint32_t addr = (uint32_t)info->data_buf;
89 invalidate_dcache_range(addr, addr + info->data_buf_size);
92 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
94 uint32_t addr = (uint32_t)info->cmd_buf;
96 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
99 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
100 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
101 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
104 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
106 struct mxs_dma_desc *desc;
108 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
109 printf("MXS NAND: Too many DMA descriptors requested\n");
113 desc = info->desc[info->desc_index];
119 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
122 struct mxs_dma_desc *desc;
124 for (i = 0; i < info->desc_index; i++) {
125 desc = info->desc[i];
126 memset(desc, 0, sizeof(struct mxs_dma_desc));
127 desc->address = (dma_addr_t)desc;
130 info->desc_index = 0;
133 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
135 return page_data_size / chunk_data_size;
138 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
140 return ecc_strength * galois_field;
143 static uint32_t mxs_nand_aux_status_offset(void)
145 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
148 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
149 uint32_t page_oob_size)
154 * Determine the ECC layout with the formula:
155 * ECC bits per chunk = (total page spare data bits) /
156 * (bits per ECC level) / (chunks per page)
158 * total page spare data bits =
159 * (page oob size - meta data size) * (bits per byte)
161 ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
163 mxs_nand_ecc_chunk_cnt(page_data_size));
165 return round_down(ecc_strength, 2);
168 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
169 uint32_t ecc_strength)
171 uint32_t chunk_data_size_in_bits;
172 uint32_t chunk_ecc_size_in_bits;
173 uint32_t chunk_total_size_in_bits;
174 uint32_t block_mark_chunk_number;
175 uint32_t block_mark_chunk_bit_offset;
176 uint32_t block_mark_bit_offset;
178 chunk_data_size_in_bits = chunk_data_size * 8;
179 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
181 chunk_total_size_in_bits =
182 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
184 /* Compute the bit offset of the block mark within the physical page. */
185 block_mark_bit_offset = page_data_size * 8;
187 /* Subtract the metadata bits. */
188 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
191 * Compute the chunk number (starting at zero) in which the block mark
194 block_mark_chunk_number =
195 block_mark_bit_offset / chunk_total_size_in_bits;
198 * Compute the bit offset of the block mark within its chunk, and
201 block_mark_chunk_bit_offset = block_mark_bit_offset -
202 (block_mark_chunk_number * chunk_total_size_in_bits);
204 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
208 * Now that we know the chunk number in which the block mark appears,
209 * we can subtract all the ECC bits that appear before it.
211 block_mark_bit_offset -=
212 block_mark_chunk_number * chunk_ecc_size_in_bits;
214 return block_mark_bit_offset;
217 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
219 uint32_t ecc_strength;
220 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
221 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
224 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
226 uint32_t ecc_strength;
227 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
228 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
232 * Wait for BCH complete IRQ and clear the IRQ
234 static int mxs_nand_wait_for_bch_complete(void)
236 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
237 int timeout = MXS_NAND_BCH_TIMEOUT;
240 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
241 BCH_CTRL_COMPLETE_IRQ, timeout);
243 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
249 * This is the function that we install in the cmd_ctrl function pointer of the
250 * owning struct nand_chip. The only functions in the reference implementation
251 * that use these functions pointers are cmdfunc and select_chip.
253 * In this driver, we implement our own select_chip, so this function will only
254 * be called by the reference implementation's cmdfunc. For this reason, we can
255 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
258 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
260 struct nand_chip *nand = mtd->priv;
261 struct mxs_nand_info *nand_info = nand->priv;
262 struct mxs_dma_desc *d;
263 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
267 * If this condition is true, something is _VERY_ wrong in MTD
270 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
271 printf("MXS NAND: Command queue too long\n");
276 * Every operation begins with a command byte and a series of zero or
277 * more address bytes. These are distinguished by either the Address
278 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
279 * asserted. When MTD is ready to execute the command, it will
280 * deasert both latch enables.
282 * Rather than run a separate DMA operation for every single byte, we
283 * queue them up and run a single DMA operation for the entire series
284 * of command and data bytes.
286 if (ctrl & (NAND_ALE | NAND_CLE)) {
287 if (data != NAND_CMD_NONE)
288 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
293 * If control arrives here, MTD has deasserted both the ALE and CLE,
294 * which means it's ready to run an operation. Check if we have any
297 if (nand_info->cmd_queue_len == 0)
300 /* Compile the DMA descriptor -- a descriptor that sends command. */
301 d = mxs_nand_get_dma_desc(nand_info);
303 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
304 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
305 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
306 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
308 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
310 d->cmd.pio_words[0] =
311 GPMI_CTRL0_COMMAND_MODE_WRITE |
312 GPMI_CTRL0_WORD_LENGTH |
313 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
314 GPMI_CTRL0_ADDRESS_NAND_CLE |
315 GPMI_CTRL0_ADDRESS_INCREMENT |
316 nand_info->cmd_queue_len;
318 mxs_dma_desc_append(channel, d);
321 mxs_nand_flush_cmd_buf(nand_info);
323 /* Execute the DMA chain. */
324 ret = mxs_dma_go(channel);
326 printf("MXS NAND: Error sending command\n");
328 mxs_nand_return_dma_descs(nand_info);
330 /* Reset the command queue. */
331 nand_info->cmd_queue_len = 0;
335 * Test if the NAND flash is ready.
337 static int mxs_nand_device_ready(struct mtd_info *mtd)
339 struct nand_chip *chip = mtd->priv;
340 struct mxs_nand_info *nand_info = chip->priv;
341 struct mxs_gpmi_regs *gpmi_regs =
342 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
345 tmp = readl(&gpmi_regs->hw_gpmi_stat);
346 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
352 * Select the NAND chip.
354 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
356 struct nand_chip *nand = mtd->priv;
357 struct mxs_nand_info *nand_info = nand->priv;
359 nand_info->cur_chip = chip;
363 * Handle block mark swapping.
365 * Note that, when this function is called, it doesn't know whether it's
366 * swapping the block mark, or swapping it *back* -- but it doesn't matter
367 * because the the operation is the same.
369 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
370 uint8_t *data_buf, uint8_t *oob_buf)
378 bit_offset = mxs_nand_mark_bit_offset(mtd);
379 buf_offset = mxs_nand_mark_byte_offset(mtd);
382 * Get the byte from the data area that overlays the block mark. Since
383 * the ECC engine applies its own view to the bits in the page, the
384 * physical block mark won't (in general) appear on a byte boundary in
387 src = data_buf[buf_offset] >> bit_offset;
388 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
394 data_buf[buf_offset] &= ~(0xff << bit_offset);
395 data_buf[buf_offset + 1] &= 0xff << bit_offset;
397 data_buf[buf_offset] |= dst << bit_offset;
398 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
402 * Read data from NAND.
404 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
406 struct nand_chip *nand = mtd->priv;
407 struct mxs_nand_info *nand_info = nand->priv;
408 struct mxs_dma_desc *d;
409 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
412 if (length > NAND_MAX_PAGESIZE) {
413 printf("MXS NAND: DMA buffer too big\n");
418 printf("MXS NAND: DMA buffer is NULL\n");
422 /* Compile the DMA descriptor - a descriptor that reads data. */
423 d = mxs_nand_get_dma_desc(nand_info);
425 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
426 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
427 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
428 (length << MXS_DMA_DESC_BYTES_OFFSET);
430 d->cmd.address = (dma_addr_t)nand_info->data_buf;
432 d->cmd.pio_words[0] =
433 GPMI_CTRL0_COMMAND_MODE_READ |
434 GPMI_CTRL0_WORD_LENGTH |
435 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
436 GPMI_CTRL0_ADDRESS_NAND_DATA |
439 mxs_dma_desc_append(channel, d);
442 * A DMA descriptor that waits for the command to end and the chip to
445 * I think we actually should *not* be waiting for the chip to become
446 * ready because, after all, we don't care. I think the original code
447 * did that and no one has re-thought it yet.
449 d = mxs_nand_get_dma_desc(nand_info);
451 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
452 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
453 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
457 d->cmd.pio_words[0] =
458 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
459 GPMI_CTRL0_WORD_LENGTH |
460 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
461 GPMI_CTRL0_ADDRESS_NAND_DATA;
463 mxs_dma_desc_append(channel, d);
465 /* Invalidate caches */
466 mxs_nand_inval_data_buf(nand_info);
468 /* Execute the DMA chain. */
469 ret = mxs_dma_go(channel);
471 printf("MXS NAND: DMA read error\n");
475 /* Invalidate caches */
476 mxs_nand_inval_data_buf(nand_info);
478 memcpy(buf, nand_info->data_buf, length);
481 mxs_nand_return_dma_descs(nand_info);
485 * Write data to NAND.
487 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
490 struct nand_chip *nand = mtd->priv;
491 struct mxs_nand_info *nand_info = nand->priv;
492 struct mxs_dma_desc *d;
493 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
496 if (length > NAND_MAX_PAGESIZE) {
497 printf("MXS NAND: DMA buffer too big\n");
502 printf("MXS NAND: DMA buffer is NULL\n");
506 memcpy(nand_info->data_buf, buf, length);
508 /* Compile the DMA descriptor - a descriptor that writes data. */
509 d = mxs_nand_get_dma_desc(nand_info);
511 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
512 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
513 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
514 (length << MXS_DMA_DESC_BYTES_OFFSET);
516 d->cmd.address = (dma_addr_t)nand_info->data_buf;
518 d->cmd.pio_words[0] =
519 GPMI_CTRL0_COMMAND_MODE_WRITE |
520 GPMI_CTRL0_WORD_LENGTH |
521 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
522 GPMI_CTRL0_ADDRESS_NAND_DATA |
525 mxs_dma_desc_append(channel, d);
528 mxs_nand_flush_data_buf(nand_info);
530 /* Execute the DMA chain. */
531 ret = mxs_dma_go(channel);
533 printf("MXS NAND: DMA write error\n");
535 mxs_nand_return_dma_descs(nand_info);
539 * Read a single byte from NAND.
541 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
544 mxs_nand_read_buf(mtd, &buf, 1);
549 * Read a page from NAND.
551 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
552 uint8_t *buf, int oob_required,
555 struct mxs_nand_info *nand_info = nand->priv;
556 struct mxs_dma_desc *d;
557 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
558 uint32_t corrected = 0, failed = 0;
562 /* Compile the DMA descriptor - wait for ready. */
563 d = mxs_nand_get_dma_desc(nand_info);
565 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
566 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
567 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
571 d->cmd.pio_words[0] =
572 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
573 GPMI_CTRL0_WORD_LENGTH |
574 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
575 GPMI_CTRL0_ADDRESS_NAND_DATA;
577 mxs_dma_desc_append(channel, d);
579 /* Compile the DMA descriptor - enable the BCH block and read. */
580 d = mxs_nand_get_dma_desc(nand_info);
582 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
583 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
587 d->cmd.pio_words[0] =
588 GPMI_CTRL0_COMMAND_MODE_READ |
589 GPMI_CTRL0_WORD_LENGTH |
590 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
591 GPMI_CTRL0_ADDRESS_NAND_DATA |
592 (mtd->writesize + mtd->oobsize);
593 d->cmd.pio_words[1] = 0;
594 d->cmd.pio_words[2] =
595 GPMI_ECCCTRL_ENABLE_ECC |
596 GPMI_ECCCTRL_ECC_CMD_DECODE |
597 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
598 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
599 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
600 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
602 mxs_dma_desc_append(channel, d);
604 /* Compile the DMA descriptor - disable the BCH block. */
605 d = mxs_nand_get_dma_desc(nand_info);
607 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
608 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
609 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
613 d->cmd.pio_words[0] =
614 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
615 GPMI_CTRL0_WORD_LENGTH |
616 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
617 GPMI_CTRL0_ADDRESS_NAND_DATA |
618 (mtd->writesize + mtd->oobsize);
619 d->cmd.pio_words[1] = 0;
620 d->cmd.pio_words[2] = 0;
622 mxs_dma_desc_append(channel, d);
624 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
625 d = mxs_nand_get_dma_desc(nand_info);
627 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
628 MXS_DMA_DESC_DEC_SEM;
632 mxs_dma_desc_append(channel, d);
634 /* Invalidate caches */
635 mxs_nand_inval_data_buf(nand_info);
637 /* Execute the DMA chain. */
638 ret = mxs_dma_go(channel);
640 printf("MXS NAND: DMA read error\n");
644 ret = mxs_nand_wait_for_bch_complete();
646 printf("MXS NAND: BCH read timeout\n");
650 /* Invalidate caches */
651 mxs_nand_inval_data_buf(nand_info);
653 /* Read DMA completed, now do the mark swapping. */
654 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
656 /* Loop over status bytes, accumulating ECC status. */
657 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
658 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
659 if (status[i] == 0x00)
662 if (status[i] == 0xff)
665 if (status[i] == 0xfe) {
670 corrected += status[i];
673 /* Propagate ECC status to the owning MTD. */
674 mtd->ecc_stats.failed += failed;
675 mtd->ecc_stats.corrected += corrected;
678 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
679 * details about our policy for delivering the OOB.
681 * We fill the caller's buffer with set bits, and then copy the block
682 * mark to the caller's buffer. Note that, if block mark swapping was
683 * necessary, it has already been done, so we can rely on the first
684 * byte of the auxiliary buffer to contain the block mark.
686 memset(nand->oob_poi, 0xff, mtd->oobsize);
688 nand->oob_poi[0] = nand_info->oob_buf[0];
690 memcpy(buf, nand_info->data_buf, mtd->writesize);
693 mxs_nand_return_dma_descs(nand_info);
699 * Write a page to NAND.
701 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
702 struct nand_chip *nand, const uint8_t *buf,
705 struct mxs_nand_info *nand_info = nand->priv;
706 struct mxs_dma_desc *d;
707 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
710 memcpy(nand_info->data_buf, buf, mtd->writesize);
711 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
713 /* Handle block mark swapping. */
714 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
716 /* Compile the DMA descriptor - write data. */
717 d = mxs_nand_get_dma_desc(nand_info);
719 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
720 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
721 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
725 d->cmd.pio_words[0] =
726 GPMI_CTRL0_COMMAND_MODE_WRITE |
727 GPMI_CTRL0_WORD_LENGTH |
728 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
729 GPMI_CTRL0_ADDRESS_NAND_DATA;
730 d->cmd.pio_words[1] = 0;
731 d->cmd.pio_words[2] =
732 GPMI_ECCCTRL_ENABLE_ECC |
733 GPMI_ECCCTRL_ECC_CMD_ENCODE |
734 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
735 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
736 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
737 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
739 mxs_dma_desc_append(channel, d);
742 mxs_nand_flush_data_buf(nand_info);
744 /* Execute the DMA chain. */
745 ret = mxs_dma_go(channel);
747 printf("MXS NAND: DMA write error\n");
751 ret = mxs_nand_wait_for_bch_complete();
753 printf("MXS NAND: BCH write timeout\n");
758 mxs_nand_return_dma_descs(nand_info);
763 * Read OOB from NAND.
765 * This function is a veneer that replaces the function originally installed by
766 * the NAND Flash MTD code.
768 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
769 struct mtd_oob_ops *ops)
771 struct nand_chip *chip = mtd->priv;
772 struct mxs_nand_info *nand_info = chip->priv;
775 if (ops->mode == MTD_OPS_RAW)
776 nand_info->raw_oob_mode = 1;
778 nand_info->raw_oob_mode = 0;
780 ret = nand_info->hooked_read_oob(mtd, from, ops);
782 nand_info->raw_oob_mode = 0;
790 * This function is a veneer that replaces the function originally installed by
791 * the NAND Flash MTD code.
793 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
794 struct mtd_oob_ops *ops)
796 struct nand_chip *chip = mtd->priv;
797 struct mxs_nand_info *nand_info = chip->priv;
800 if (ops->mode == MTD_OPS_RAW)
801 nand_info->raw_oob_mode = 1;
803 nand_info->raw_oob_mode = 0;
805 ret = nand_info->hooked_write_oob(mtd, to, ops);
807 nand_info->raw_oob_mode = 0;
813 * Mark a block bad in NAND.
815 * This function is a veneer that replaces the function originally installed by
816 * the NAND Flash MTD code.
818 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
820 struct nand_chip *chip = mtd->priv;
821 struct mxs_nand_info *nand_info = chip->priv;
824 nand_info->marking_block_bad = 1;
826 ret = nand_info->hooked_block_markbad(mtd, ofs);
828 nand_info->marking_block_bad = 0;
834 * There are several places in this driver where we have to handle the OOB and
835 * block marks. This is the function where things are the most complicated, so
836 * this is where we try to explain it all. All the other places refer back to
839 * These are the rules, in order of decreasing importance:
841 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
842 * write operations take measures to protect it.
844 * 2) In read operations, the first byte of the OOB we return must reflect the
845 * true state of the block mark, no matter where that block mark appears in
848 * 3) ECC-based read operations return an OOB full of set bits (since we never
849 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
852 * 4) "Raw" read operations return a direct view of the physical bytes in the
853 * page, using the conventional definition of which bytes are data and which
854 * are OOB. This gives the caller a way to see the actual, physical bytes
855 * in the page, without the distortions applied by our ECC engine.
857 * What we do for this specific read operation depends on whether we're doing
858 * "raw" read, or an ECC-based read.
860 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
861 * easy. When reading a page, for example, the NAND Flash MTD code calls our
862 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
863 * ECC-based or raw view of the page is implicit in which function it calls
864 * (there is a similar pair of ECC-based/raw functions for writing).
866 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
867 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
868 * caller wants an ECC-based or raw view of the page is not propagated down to
871 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
872 * ecc.read_oob and ecc.write_oob function pointers in the owning
873 * struct mtd_info with our own functions. These hook functions set the
874 * raw_oob_mode field so that, when control finally arrives here, we'll know
877 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
880 struct mxs_nand_info *nand_info = nand->priv;
883 * First, fill in the OOB buffer. If we're doing a raw read, we need to
884 * get the bytes from the physical page. If we're not doing a raw read,
885 * we need to fill the buffer with set bits.
887 if (nand_info->raw_oob_mode) {
889 * If control arrives here, we're doing a "raw" read. Send the
890 * command to read the conventional OOB and read it.
892 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
893 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
896 * If control arrives here, we're not doing a "raw" read. Fill
897 * the OOB buffer with set bits and correct the block mark.
899 memset(nand->oob_poi, 0xff, mtd->oobsize);
901 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
902 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
910 * Write OOB data to NAND.
912 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
915 struct mxs_nand_info *nand_info = nand->priv;
916 uint8_t block_mark = 0;
919 * There are fundamental incompatibilities between the i.MX GPMI NFC and
920 * the NAND Flash MTD model that make it essentially impossible to write
921 * the out-of-band bytes.
923 * We permit *ONE* exception. If the *intent* of writing the OOB is to
924 * mark a block bad, we can do that.
927 if (!nand_info->marking_block_bad) {
928 printf("NXS NAND: Writing OOB isn't supported\n");
932 /* Write the block mark. */
933 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
934 nand->write_buf(mtd, &block_mark, 1);
935 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
937 /* Check if it worked. */
938 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
945 * Claims all blocks are good.
947 * In principle, this function is *only* called when the NAND Flash MTD system
948 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
949 * the driver for bad block information.
951 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
952 * this function is *only* called when we take it away.
954 * Thus, this function is only called when we want *all* blocks to look good,
955 * so it *always* return success.
957 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
963 * Nominally, the purpose of this function is to look for or create the bad
964 * block table. In fact, since the we call this function at the very end of
965 * the initialization process started by nand_scan(), and we doesn't have a
966 * more formal mechanism, we "hook" this function to continue init process.
968 * At this point, the physical NAND Flash chips have been identified and
969 * counted, so we know the physical geometry. This enables us to make some
970 * important configuration decisions.
972 * The return value of this function propogates directly back to this driver's
973 * call to nand_scan(). Anything other than zero will cause this driver to
974 * tear everything down and declare failure.
976 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
978 struct nand_chip *nand = mtd->priv;
979 struct mxs_nand_info *nand_info = nand->priv;
980 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
983 if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) {
985 chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2;
988 if (mtd->oobsize > chunk_data_size) {
989 printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size);
993 /* Configure BCH and set NFC geometry */
994 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
996 /* Configure layout 0 */
997 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
998 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
999 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1000 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1001 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1002 tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1003 tmp |= (14 == galois_field ? 1 : 0) <<
1004 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
1005 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1007 tmp = (mtd->writesize + mtd->oobsize)
1008 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1009 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1010 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1011 tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1012 tmp |= (14 == galois_field ? 1 : 0) <<
1013 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1014 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1016 /* Set *all* chip selects to use layout 0 */
1017 writel(0, &bch_regs->hw_bch_layoutselect);
1019 /* Enable BCH complete interrupt */
1020 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1022 /* Hook some operations at the MTD level. */
1023 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1024 nand_info->hooked_read_oob = mtd->_read_oob;
1025 mtd->_read_oob = mxs_nand_hook_read_oob;
1028 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1029 nand_info->hooked_write_oob = mtd->_write_oob;
1030 mtd->_write_oob = mxs_nand_hook_write_oob;
1033 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1034 nand_info->hooked_block_markbad = mtd->_block_markbad;
1035 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1038 /* We use the reference implementation for bad block management. */
1039 return nand_default_bbt(mtd);
1043 * Allocate DMA buffers
1045 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1048 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1050 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1053 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1055 printf("MXS NAND: Error allocating DMA buffers\n");
1059 memset(buf, 0, nand_info->data_buf_size);
1061 nand_info->data_buf = buf;
1062 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1063 /* Command buffers */
1064 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1065 MXS_NAND_COMMAND_BUFFER_SIZE);
1066 if (!nand_info->cmd_buf) {
1068 printf("MXS NAND: Error allocating command buffers\n");
1071 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1072 nand_info->cmd_queue_len = 0;
1078 * Initializes the NFC hardware.
1080 int mxs_nand_init(struct mxs_nand_info *info)
1082 struct mxs_gpmi_regs *gpmi_regs =
1083 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1084 struct mxs_bch_regs *bch_regs =
1085 (struct mxs_bch_regs *)MXS_BCH_BASE;
1088 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1089 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1093 /* Allocate the DMA descriptors. */
1094 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1095 info->desc[i] = mxs_dma_desc_alloc();
1100 /* Init the DMA controller. */
1101 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1102 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1103 if (mxs_dma_init_channel(j))
1107 /* Reset the GPMI block. */
1108 mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
1109 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1112 * Choose NAND mode, set IRQ polarity, disable write protection and
1115 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
1116 GPMI_CTRL1_GPMI_MODE,
1117 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1118 GPMI_CTRL1_BCH_MODE);
1123 for (--j; j >= 0; j--)
1128 for (--i; i >= 0; i--)
1129 mxs_dma_desc_free(info->desc[i]);
1130 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1135 * This function is called during the driver binding process.
1137 * @param pdev the device structure used to store device specific
1138 * information that is used by the suspend, resume and
1141 * @return The function always returns 0.
1143 int board_nand_init(struct nand_chip *nand)
1145 struct mxs_nand_info *nand_info;
1148 nand_info = malloc(sizeof(struct mxs_nand_info));
1150 printf("MXS NAND: Failed to allocate private data\n");
1153 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1155 err = mxs_nand_alloc_buffers(nand_info);
1159 err = mxs_nand_init(nand_info);
1163 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1165 nand->priv = nand_info;
1166 nand->options |= NAND_NO_SUBPAGE_WRITE;
1168 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1170 nand->dev_ready = mxs_nand_device_ready;
1171 nand->select_chip = mxs_nand_select_chip;
1172 nand->block_bad = mxs_nand_block_bad;
1173 nand->scan_bbt = mxs_nand_scan_bbt;
1175 nand->read_byte = mxs_nand_read_byte;
1177 nand->read_buf = mxs_nand_read_buf;
1178 nand->write_buf = mxs_nand_write_buf;
1180 nand->ecc.read_page = mxs_nand_ecc_read_page;
1181 nand->ecc.write_page = mxs_nand_ecc_write_page;
1182 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1183 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1185 nand->ecc.layout = &fake_ecc_layout;
1186 nand->ecc.mode = NAND_ECC_HW;
1187 nand->ecc.bytes = 9;
1188 nand->ecc.size = 512;
1189 nand->ecc.strength = 8;
1194 free(nand_info->data_buf);
1195 free(nand_info->cmd_buf);