2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/types.h>
21 #include <linux/errno.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/imx-regs.h>
25 #include <asm/imx-common/regs-bch.h>
26 #include <asm/imx-common/regs-gpmi.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/imx-common/dma.h>
30 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
32 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
33 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
34 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
36 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
38 #define MXS_NAND_METADATA_SIZE 10
39 #define MXS_NAND_BITS_PER_ECC_LEVEL 13
41 #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
42 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
44 #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
47 #define MXS_NAND_BCH_TIMEOUT 10000
49 struct mxs_nand_info {
52 uint32_t cmd_queue_len;
53 uint32_t data_buf_size;
59 uint8_t marking_block_bad;
62 /* Functions with altered behaviour */
63 int (*hooked_read_oob)(struct mtd_info *mtd,
64 loff_t from, struct mtd_oob_ops *ops);
65 int (*hooked_write_oob)(struct mtd_info *mtd,
66 loff_t to, struct mtd_oob_ops *ops);
67 int (*hooked_block_markbad)(struct mtd_info *mtd,
71 struct mxs_dma_desc **desc;
75 struct nand_ecclayout fake_ecc_layout;
76 static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
77 static int galois_field = 13;
80 * Cache management functions
82 #ifndef CONFIG_SYS_DCACHE_OFF
83 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
85 uint32_t addr = (uint32_t)info->data_buf;
87 flush_dcache_range(addr, addr + info->data_buf_size);
90 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
92 uint32_t addr = (uint32_t)info->data_buf;
94 invalidate_dcache_range(addr, addr + info->data_buf_size);
97 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
99 uint32_t addr = (uint32_t)info->cmd_buf;
101 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
104 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
105 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
106 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
109 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
111 struct mxs_dma_desc *desc;
113 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
114 printf("MXS NAND: Too many DMA descriptors requested\n");
118 desc = info->desc[info->desc_index];
124 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
127 struct mxs_dma_desc *desc;
129 for (i = 0; i < info->desc_index; i++) {
130 desc = info->desc[i];
131 memset(desc, 0, sizeof(struct mxs_dma_desc));
132 desc->address = (dma_addr_t)desc;
135 info->desc_index = 0;
138 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
140 return page_data_size / chunk_data_size;
143 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
145 return ecc_strength * galois_field;
148 static uint32_t mxs_nand_aux_status_offset(void)
150 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
153 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
154 uint32_t page_oob_size)
157 int max_ecc_strength_supported;
159 /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
160 if (is_mx6sx() || is_mx7())
161 max_ecc_strength_supported = 62;
163 max_ecc_strength_supported = 40;
166 * Determine the ECC layout with the formula:
167 * ECC bits per chunk = (total page spare data bits) /
168 * (bits per ECC level) / (chunks per page)
170 * total page spare data bits =
171 * (page oob size - meta data size) * (bits per byte)
173 ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
175 mxs_nand_ecc_chunk_cnt(page_data_size));
177 return min(round_down(ecc_strength, 2), max_ecc_strength_supported);
180 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
181 uint32_t ecc_strength)
183 uint32_t chunk_data_size_in_bits;
184 uint32_t chunk_ecc_size_in_bits;
185 uint32_t chunk_total_size_in_bits;
186 uint32_t block_mark_chunk_number;
187 uint32_t block_mark_chunk_bit_offset;
188 uint32_t block_mark_bit_offset;
190 chunk_data_size_in_bits = chunk_data_size * 8;
191 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
193 chunk_total_size_in_bits =
194 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
196 /* Compute the bit offset of the block mark within the physical page. */
197 block_mark_bit_offset = page_data_size * 8;
199 /* Subtract the metadata bits. */
200 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
203 * Compute the chunk number (starting at zero) in which the block mark
206 block_mark_chunk_number =
207 block_mark_bit_offset / chunk_total_size_in_bits;
210 * Compute the bit offset of the block mark within its chunk, and
213 block_mark_chunk_bit_offset = block_mark_bit_offset -
214 (block_mark_chunk_number * chunk_total_size_in_bits);
216 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
220 * Now that we know the chunk number in which the block mark appears,
221 * we can subtract all the ECC bits that appear before it.
223 block_mark_bit_offset -=
224 block_mark_chunk_number * chunk_ecc_size_in_bits;
226 return block_mark_bit_offset;
229 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
231 uint32_t ecc_strength;
232 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
233 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
236 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
238 uint32_t ecc_strength;
239 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
240 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
244 * Wait for BCH complete IRQ and clear the IRQ
246 static int mxs_nand_wait_for_bch_complete(void)
248 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
249 int timeout = MXS_NAND_BCH_TIMEOUT;
252 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
253 BCH_CTRL_COMPLETE_IRQ, timeout);
255 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
261 * This is the function that we install in the cmd_ctrl function pointer of the
262 * owning struct nand_chip. The only functions in the reference implementation
263 * that use these functions pointers are cmdfunc and select_chip.
265 * In this driver, we implement our own select_chip, so this function will only
266 * be called by the reference implementation's cmdfunc. For this reason, we can
267 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
270 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
272 struct nand_chip *nand = mtd_to_nand(mtd);
273 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
274 struct mxs_dma_desc *d;
275 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
279 * If this condition is true, something is _VERY_ wrong in MTD
282 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
283 printf("MXS NAND: Command queue too long\n");
288 * Every operation begins with a command byte and a series of zero or
289 * more address bytes. These are distinguished by either the Address
290 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
291 * asserted. When MTD is ready to execute the command, it will
292 * deasert both latch enables.
294 * Rather than run a separate DMA operation for every single byte, we
295 * queue them up and run a single DMA operation for the entire series
296 * of command and data bytes.
298 if (ctrl & (NAND_ALE | NAND_CLE)) {
299 if (data != NAND_CMD_NONE)
300 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
305 * If control arrives here, MTD has deasserted both the ALE and CLE,
306 * which means it's ready to run an operation. Check if we have any
309 if (nand_info->cmd_queue_len == 0)
312 /* Compile the DMA descriptor -- a descriptor that sends command. */
313 d = mxs_nand_get_dma_desc(nand_info);
315 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
316 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
317 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
318 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
320 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
322 d->cmd.pio_words[0] =
323 GPMI_CTRL0_COMMAND_MODE_WRITE |
324 GPMI_CTRL0_WORD_LENGTH |
325 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
326 GPMI_CTRL0_ADDRESS_NAND_CLE |
327 GPMI_CTRL0_ADDRESS_INCREMENT |
328 nand_info->cmd_queue_len;
330 mxs_dma_desc_append(channel, d);
333 mxs_nand_flush_cmd_buf(nand_info);
335 /* Execute the DMA chain. */
336 ret = mxs_dma_go(channel);
338 printf("MXS NAND: Error sending command\n");
340 mxs_nand_return_dma_descs(nand_info);
342 /* Reset the command queue. */
343 nand_info->cmd_queue_len = 0;
347 * Test if the NAND flash is ready.
349 static int mxs_nand_device_ready(struct mtd_info *mtd)
351 struct nand_chip *chip = mtd_to_nand(mtd);
352 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
353 struct mxs_gpmi_regs *gpmi_regs =
354 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
357 tmp = readl(&gpmi_regs->hw_gpmi_stat);
358 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
364 * Select the NAND chip.
366 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
368 struct nand_chip *nand = mtd_to_nand(mtd);
369 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
371 nand_info->cur_chip = chip;
375 * Handle block mark swapping.
377 * Note that, when this function is called, it doesn't know whether it's
378 * swapping the block mark, or swapping it *back* -- but it doesn't matter
379 * because the the operation is the same.
381 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
382 uint8_t *data_buf, uint8_t *oob_buf)
390 bit_offset = mxs_nand_mark_bit_offset(mtd);
391 buf_offset = mxs_nand_mark_byte_offset(mtd);
394 * Get the byte from the data area that overlays the block mark. Since
395 * the ECC engine applies its own view to the bits in the page, the
396 * physical block mark won't (in general) appear on a byte boundary in
399 src = data_buf[buf_offset] >> bit_offset;
400 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
406 data_buf[buf_offset] &= ~(0xff << bit_offset);
407 data_buf[buf_offset + 1] &= 0xff << bit_offset;
409 data_buf[buf_offset] |= dst << bit_offset;
410 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
414 * Read data from NAND.
416 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
418 struct nand_chip *nand = mtd_to_nand(mtd);
419 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
420 struct mxs_dma_desc *d;
421 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
424 if (length > NAND_MAX_PAGESIZE) {
425 printf("MXS NAND: DMA buffer too big\n");
430 printf("MXS NAND: DMA buffer is NULL\n");
434 /* Compile the DMA descriptor - a descriptor that reads data. */
435 d = mxs_nand_get_dma_desc(nand_info);
437 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
438 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
439 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
440 (length << MXS_DMA_DESC_BYTES_OFFSET);
442 d->cmd.address = (dma_addr_t)nand_info->data_buf;
444 d->cmd.pio_words[0] =
445 GPMI_CTRL0_COMMAND_MODE_READ |
446 GPMI_CTRL0_WORD_LENGTH |
447 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
448 GPMI_CTRL0_ADDRESS_NAND_DATA |
451 mxs_dma_desc_append(channel, d);
454 * A DMA descriptor that waits for the command to end and the chip to
457 * I think we actually should *not* be waiting for the chip to become
458 * ready because, after all, we don't care. I think the original code
459 * did that and no one has re-thought it yet.
461 d = mxs_nand_get_dma_desc(nand_info);
463 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
464 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
465 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
469 d->cmd.pio_words[0] =
470 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
471 GPMI_CTRL0_WORD_LENGTH |
472 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
473 GPMI_CTRL0_ADDRESS_NAND_DATA;
475 mxs_dma_desc_append(channel, d);
477 /* Invalidate caches */
478 mxs_nand_inval_data_buf(nand_info);
480 /* Execute the DMA chain. */
481 ret = mxs_dma_go(channel);
483 printf("MXS NAND: DMA read error\n");
487 /* Invalidate caches */
488 mxs_nand_inval_data_buf(nand_info);
490 memcpy(buf, nand_info->data_buf, length);
493 mxs_nand_return_dma_descs(nand_info);
497 * Write data to NAND.
499 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
502 struct nand_chip *nand = mtd_to_nand(mtd);
503 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
504 struct mxs_dma_desc *d;
505 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
508 if (length > NAND_MAX_PAGESIZE) {
509 printf("MXS NAND: DMA buffer too big\n");
514 printf("MXS NAND: DMA buffer is NULL\n");
518 memcpy(nand_info->data_buf, buf, length);
520 /* Compile the DMA descriptor - a descriptor that writes data. */
521 d = mxs_nand_get_dma_desc(nand_info);
523 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
524 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
525 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
526 (length << MXS_DMA_DESC_BYTES_OFFSET);
528 d->cmd.address = (dma_addr_t)nand_info->data_buf;
530 d->cmd.pio_words[0] =
531 GPMI_CTRL0_COMMAND_MODE_WRITE |
532 GPMI_CTRL0_WORD_LENGTH |
533 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
534 GPMI_CTRL0_ADDRESS_NAND_DATA |
537 mxs_dma_desc_append(channel, d);
540 mxs_nand_flush_data_buf(nand_info);
542 /* Execute the DMA chain. */
543 ret = mxs_dma_go(channel);
545 printf("MXS NAND: DMA write error\n");
547 mxs_nand_return_dma_descs(nand_info);
551 * Read a single byte from NAND.
553 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
556 mxs_nand_read_buf(mtd, &buf, 1);
561 * Read a page from NAND.
563 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
564 uint8_t *buf, int oob_required,
567 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
568 struct mxs_dma_desc *d;
569 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
570 uint32_t corrected = 0, failed = 0;
574 /* Compile the DMA descriptor - wait for ready. */
575 d = mxs_nand_get_dma_desc(nand_info);
577 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
578 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
579 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
583 d->cmd.pio_words[0] =
584 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
585 GPMI_CTRL0_WORD_LENGTH |
586 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
587 GPMI_CTRL0_ADDRESS_NAND_DATA;
589 mxs_dma_desc_append(channel, d);
591 /* Compile the DMA descriptor - enable the BCH block and read. */
592 d = mxs_nand_get_dma_desc(nand_info);
594 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
595 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
599 d->cmd.pio_words[0] =
600 GPMI_CTRL0_COMMAND_MODE_READ |
601 GPMI_CTRL0_WORD_LENGTH |
602 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
603 GPMI_CTRL0_ADDRESS_NAND_DATA |
604 (mtd->writesize + mtd->oobsize);
605 d->cmd.pio_words[1] = 0;
606 d->cmd.pio_words[2] =
607 GPMI_ECCCTRL_ENABLE_ECC |
608 GPMI_ECCCTRL_ECC_CMD_DECODE |
609 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
610 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
611 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
612 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
614 mxs_dma_desc_append(channel, d);
616 /* Compile the DMA descriptor - disable the BCH block. */
617 d = mxs_nand_get_dma_desc(nand_info);
619 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
620 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
621 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
625 d->cmd.pio_words[0] =
626 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
627 GPMI_CTRL0_WORD_LENGTH |
628 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
629 GPMI_CTRL0_ADDRESS_NAND_DATA |
630 (mtd->writesize + mtd->oobsize);
631 d->cmd.pio_words[1] = 0;
632 d->cmd.pio_words[2] = 0;
634 mxs_dma_desc_append(channel, d);
636 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
637 d = mxs_nand_get_dma_desc(nand_info);
639 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
640 MXS_DMA_DESC_DEC_SEM;
644 mxs_dma_desc_append(channel, d);
646 /* Invalidate caches */
647 mxs_nand_inval_data_buf(nand_info);
649 /* Execute the DMA chain. */
650 ret = mxs_dma_go(channel);
652 printf("MXS NAND: DMA read error\n");
656 ret = mxs_nand_wait_for_bch_complete();
658 printf("MXS NAND: BCH read timeout\n");
662 /* Invalidate caches */
663 mxs_nand_inval_data_buf(nand_info);
665 /* Read DMA completed, now do the mark swapping. */
666 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
668 /* Loop over status bytes, accumulating ECC status. */
669 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
670 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
671 if (status[i] == 0x00)
674 if (status[i] == 0xff)
677 if (status[i] == 0xfe) {
682 corrected += status[i];
685 /* Propagate ECC status to the owning MTD. */
686 mtd->ecc_stats.failed += failed;
687 mtd->ecc_stats.corrected += corrected;
690 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
691 * details about our policy for delivering the OOB.
693 * We fill the caller's buffer with set bits, and then copy the block
694 * mark to the caller's buffer. Note that, if block mark swapping was
695 * necessary, it has already been done, so we can rely on the first
696 * byte of the auxiliary buffer to contain the block mark.
698 memset(nand->oob_poi, 0xff, mtd->oobsize);
700 nand->oob_poi[0] = nand_info->oob_buf[0];
702 memcpy(buf, nand_info->data_buf, mtd->writesize);
705 mxs_nand_return_dma_descs(nand_info);
711 * Write a page to NAND.
713 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
714 struct nand_chip *nand, const uint8_t *buf,
715 int oob_required, int page)
717 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
718 struct mxs_dma_desc *d;
719 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
722 memcpy(nand_info->data_buf, buf, mtd->writesize);
723 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
725 /* Handle block mark swapping. */
726 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
728 /* Compile the DMA descriptor - write data. */
729 d = mxs_nand_get_dma_desc(nand_info);
731 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
732 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
733 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
737 d->cmd.pio_words[0] =
738 GPMI_CTRL0_COMMAND_MODE_WRITE |
739 GPMI_CTRL0_WORD_LENGTH |
740 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
741 GPMI_CTRL0_ADDRESS_NAND_DATA;
742 d->cmd.pio_words[1] = 0;
743 d->cmd.pio_words[2] =
744 GPMI_ECCCTRL_ENABLE_ECC |
745 GPMI_ECCCTRL_ECC_CMD_ENCODE |
746 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
747 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
748 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
749 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
751 mxs_dma_desc_append(channel, d);
754 mxs_nand_flush_data_buf(nand_info);
756 /* Execute the DMA chain. */
757 ret = mxs_dma_go(channel);
759 printf("MXS NAND: DMA write error\n");
763 ret = mxs_nand_wait_for_bch_complete();
765 printf("MXS NAND: BCH write timeout\n");
770 mxs_nand_return_dma_descs(nand_info);
775 * Read OOB from NAND.
777 * This function is a veneer that replaces the function originally installed by
778 * the NAND Flash MTD code.
780 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
781 struct mtd_oob_ops *ops)
783 struct nand_chip *chip = mtd_to_nand(mtd);
784 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
787 if (ops->mode == MTD_OPS_RAW)
788 nand_info->raw_oob_mode = 1;
790 nand_info->raw_oob_mode = 0;
792 ret = nand_info->hooked_read_oob(mtd, from, ops);
794 nand_info->raw_oob_mode = 0;
802 * This function is a veneer that replaces the function originally installed by
803 * the NAND Flash MTD code.
805 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
806 struct mtd_oob_ops *ops)
808 struct nand_chip *chip = mtd_to_nand(mtd);
809 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
812 if (ops->mode == MTD_OPS_RAW)
813 nand_info->raw_oob_mode = 1;
815 nand_info->raw_oob_mode = 0;
817 ret = nand_info->hooked_write_oob(mtd, to, ops);
819 nand_info->raw_oob_mode = 0;
825 * Mark a block bad in NAND.
827 * This function is a veneer that replaces the function originally installed by
828 * the NAND Flash MTD code.
830 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
832 struct nand_chip *chip = mtd_to_nand(mtd);
833 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
836 nand_info->marking_block_bad = 1;
838 ret = nand_info->hooked_block_markbad(mtd, ofs);
840 nand_info->marking_block_bad = 0;
846 * There are several places in this driver where we have to handle the OOB and
847 * block marks. This is the function where things are the most complicated, so
848 * this is where we try to explain it all. All the other places refer back to
851 * These are the rules, in order of decreasing importance:
853 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
854 * write operations take measures to protect it.
856 * 2) In read operations, the first byte of the OOB we return must reflect the
857 * true state of the block mark, no matter where that block mark appears in
860 * 3) ECC-based read operations return an OOB full of set bits (since we never
861 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
864 * 4) "Raw" read operations return a direct view of the physical bytes in the
865 * page, using the conventional definition of which bytes are data and which
866 * are OOB. This gives the caller a way to see the actual, physical bytes
867 * in the page, without the distortions applied by our ECC engine.
869 * What we do for this specific read operation depends on whether we're doing
870 * "raw" read, or an ECC-based read.
872 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
873 * easy. When reading a page, for example, the NAND Flash MTD code calls our
874 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
875 * ECC-based or raw view of the page is implicit in which function it calls
876 * (there is a similar pair of ECC-based/raw functions for writing).
878 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
879 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
880 * caller wants an ECC-based or raw view of the page is not propagated down to
883 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
884 * ecc.read_oob and ecc.write_oob function pointers in the owning
885 * struct mtd_info with our own functions. These hook functions set the
886 * raw_oob_mode field so that, when control finally arrives here, we'll know
889 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
892 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
895 * First, fill in the OOB buffer. If we're doing a raw read, we need to
896 * get the bytes from the physical page. If we're not doing a raw read,
897 * we need to fill the buffer with set bits.
899 if (nand_info->raw_oob_mode) {
901 * If control arrives here, we're doing a "raw" read. Send the
902 * command to read the conventional OOB and read it.
904 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
905 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
908 * If control arrives here, we're not doing a "raw" read. Fill
909 * the OOB buffer with set bits and correct the block mark.
911 memset(nand->oob_poi, 0xff, mtd->oobsize);
913 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
914 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
922 * Write OOB data to NAND.
924 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
927 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
928 uint8_t block_mark = 0;
931 * There are fundamental incompatibilities between the i.MX GPMI NFC and
932 * the NAND Flash MTD model that make it essentially impossible to write
933 * the out-of-band bytes.
935 * We permit *ONE* exception. If the *intent* of writing the OOB is to
936 * mark a block bad, we can do that.
939 if (!nand_info->marking_block_bad) {
940 printf("NXS NAND: Writing OOB isn't supported\n");
944 /* Write the block mark. */
945 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
946 nand->write_buf(mtd, &block_mark, 1);
947 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
949 /* Check if it worked. */
950 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
957 * Claims all blocks are good.
959 * In principle, this function is *only* called when the NAND Flash MTD system
960 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
961 * the driver for bad block information.
963 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
964 * this function is *only* called when we take it away.
966 * Thus, this function is only called when we want *all* blocks to look good,
967 * so it *always* return success.
969 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
975 * Nominally, the purpose of this function is to look for or create the bad
976 * block table. In fact, since the we call this function at the very end of
977 * the initialization process started by nand_scan(), and we doesn't have a
978 * more formal mechanism, we "hook" this function to continue init process.
980 * At this point, the physical NAND Flash chips have been identified and
981 * counted, so we know the physical geometry. This enables us to make some
982 * important configuration decisions.
984 * The return value of this function propagates directly back to this driver's
985 * call to nand_scan(). Anything other than zero will cause this driver to
986 * tear everything down and declare failure.
988 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
990 struct nand_chip *nand = mtd_to_nand(mtd);
991 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
992 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
995 if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) {
997 chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2;
1000 if (mtd->oobsize > chunk_data_size) {
1001 printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size);
1005 /* Configure BCH and set NFC geometry */
1006 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1008 /* Configure layout 0 */
1009 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
1010 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1011 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1012 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1013 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1014 tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1015 tmp |= (14 == galois_field ? 1 : 0) <<
1016 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
1017 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1019 tmp = (mtd->writesize + mtd->oobsize)
1020 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1021 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1022 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1023 tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1024 tmp |= (14 == galois_field ? 1 : 0) <<
1025 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1026 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1028 /* Set *all* chip selects to use layout 0 */
1029 writel(0, &bch_regs->hw_bch_layoutselect);
1031 /* Enable BCH complete interrupt */
1032 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1034 /* Hook some operations at the MTD level. */
1035 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1036 nand_info->hooked_read_oob = mtd->_read_oob;
1037 mtd->_read_oob = mxs_nand_hook_read_oob;
1040 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1041 nand_info->hooked_write_oob = mtd->_write_oob;
1042 mtd->_write_oob = mxs_nand_hook_write_oob;
1045 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1046 nand_info->hooked_block_markbad = mtd->_block_markbad;
1047 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1050 /* We use the reference implementation for bad block management. */
1051 return nand_default_bbt(mtd);
1055 * Allocate DMA buffers
1057 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1060 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1062 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1065 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1067 printf("MXS NAND: Error allocating DMA buffers\n");
1071 memset(buf, 0, nand_info->data_buf_size);
1073 nand_info->data_buf = buf;
1074 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1075 /* Command buffers */
1076 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1077 MXS_NAND_COMMAND_BUFFER_SIZE);
1078 if (!nand_info->cmd_buf) {
1080 printf("MXS NAND: Error allocating command buffers\n");
1083 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1084 nand_info->cmd_queue_len = 0;
1090 * Initializes the NFC hardware.
1092 int mxs_nand_init(struct mxs_nand_info *info)
1094 struct mxs_gpmi_regs *gpmi_regs =
1095 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1096 struct mxs_bch_regs *bch_regs =
1097 (struct mxs_bch_regs *)MXS_BCH_BASE;
1098 int i = 0, j, ret = 0;
1100 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1101 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1107 /* Allocate the DMA descriptors. */
1108 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1109 info->desc[i] = mxs_dma_desc_alloc();
1110 if (!info->desc[i]) {
1116 /* Init the DMA controller. */
1117 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1118 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1119 ret = mxs_dma_init_channel(j);
1124 /* Reset the GPMI block. */
1125 mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
1126 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1129 * Choose NAND mode, set IRQ polarity, disable write protection and
1132 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
1133 GPMI_CTRL1_GPMI_MODE,
1134 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1135 GPMI_CTRL1_BCH_MODE);
1140 for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
1143 for (--i; i >= 0; i--)
1144 mxs_dma_desc_free(info->desc[i]);
1148 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1153 * This function is called during the driver binding process.
1155 * @param pdev the device structure used to store device specific
1156 * information that is used by the suspend, resume and
1159 * @return The function always returns 0.
1161 int board_nand_init(struct nand_chip *nand)
1163 struct mxs_nand_info *nand_info;
1166 nand_info = malloc(sizeof(struct mxs_nand_info));
1168 printf("MXS NAND: Failed to allocate private data\n");
1171 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1173 err = mxs_nand_alloc_buffers(nand_info);
1177 err = mxs_nand_init(nand_info);
1181 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1183 nand_set_controller_data(nand, nand_info);
1184 nand->options |= NAND_NO_SUBPAGE_WRITE;
1186 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1188 nand->dev_ready = mxs_nand_device_ready;
1189 nand->select_chip = mxs_nand_select_chip;
1190 nand->block_bad = mxs_nand_block_bad;
1191 nand->scan_bbt = mxs_nand_scan_bbt;
1193 nand->read_byte = mxs_nand_read_byte;
1195 nand->read_buf = mxs_nand_read_buf;
1196 nand->write_buf = mxs_nand_write_buf;
1198 nand->ecc.read_page = mxs_nand_ecc_read_page;
1199 nand->ecc.write_page = mxs_nand_ecc_write_page;
1200 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1201 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1203 nand->ecc.layout = &fake_ecc_layout;
1204 nand->ecc.mode = NAND_ECC_HW;
1205 nand->ecc.bytes = 9;
1206 nand->ecc.size = 512;
1207 nand->ecc.strength = 8;
1212 free(nand_info->data_buf);
1213 free(nand_info->cmd_buf);