5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
37 #define ENOTSUPP 524 /* Operation is not supported */
41 #include <linux/err.h>
42 #include <linux/mtd/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
47 #ifdef CONFIG_MTD_PARTITIONS
48 #include <linux/mtd/partitions.h>
52 #include <asm/errno.h>
55 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
56 * a flash. NAND flash is initialized prior to interrupts so standard timers
57 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
58 * which is greater than (max NAND reset time / NAND status read time).
59 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
61 #ifndef CONFIG_SYS_NAND_RESET_CNT
62 #define CONFIG_SYS_NAND_RESET_CNT 200000
65 /* Define default oob placement schemes for large and small page devices */
66 static struct nand_ecclayout nand_oob_8 = {
76 static struct nand_ecclayout nand_oob_16 = {
78 .eccpos = {0, 1, 2, 3, 6, 7},
84 static struct nand_ecclayout nand_oob_64 = {
87 40, 41, 42, 43, 44, 45, 46, 47,
88 48, 49, 50, 51, 52, 53, 54, 55,
89 56, 57, 58, 59, 60, 61, 62, 63},
95 static struct nand_ecclayout nand_oob_128 = {
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100, 101, 102, 103,
101 104, 105, 106, 107, 108, 109, 110, 111,
102 112, 113, 114, 115, 116, 117, 118, 119,
103 120, 121, 122, 123, 124, 125, 126, 127},
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
119 * nand_release_device - [GENERIC] release chip
120 * @mtd: MTD device structure
122 * Deselect, release chip lock and wake up anyone waiting on the device
124 static void nand_release_device (struct mtd_info *mtd)
126 struct nand_chip *this = mtd->priv;
127 this->select_chip(mtd, -1); /* De-select the NAND device */
131 * nand_read_byte - [DEFAULT] read one byte from the chip
132 * @mtd: MTD device structure
134 * Default read function for 8bit buswith
136 static uint8_t nand_read_byte(struct mtd_info *mtd)
138 struct nand_chip *chip = mtd->priv;
139 return readb(chip->IO_ADDR_R);
143 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
144 * @mtd: MTD device structure
146 * Default read function for 16bit buswith with
147 * endianess conversion
149 static uint8_t nand_read_byte16(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
152 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
156 * nand_read_word - [DEFAULT] read one word from the chip
157 * @mtd: MTD device structure
159 * Default read function for 16bit buswith without
160 * endianess conversion
162 static u16 nand_read_word(struct mtd_info *mtd)
164 struct nand_chip *chip = mtd->priv;
165 return readw(chip->IO_ADDR_R);
169 * nand_select_chip - [DEFAULT] control CE line
170 * @mtd: MTD device structure
171 * @chipnr: chipnumber to select, -1 for deselect
173 * Default select function for 1 chip devices.
175 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
177 struct nand_chip *chip = mtd->priv;
181 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
192 * nand_write_buf - [DEFAULT] write buffer to chip
193 * @mtd: MTD device structure
195 * @len: number of bytes to write
197 * Default write function for 8bit buswith
199 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
202 struct nand_chip *chip = mtd->priv;
204 for (i = 0; i < len; i++)
205 writeb(buf[i], chip->IO_ADDR_W);
209 * nand_read_buf - [DEFAULT] read chip data into buffer
210 * @mtd: MTD device structure
211 * @buf: buffer to store date
212 * @len: number of bytes to read
214 * Default read function for 8bit buswith
216 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
219 struct nand_chip *chip = mtd->priv;
221 for (i = 0; i < len; i++)
222 buf[i] = readb(chip->IO_ADDR_R);
226 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
227 * @mtd: MTD device structure
228 * @buf: buffer containing the data to compare
229 * @len: number of bytes to compare
231 * Default verify function for 8bit buswith
233 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
236 struct nand_chip *chip = mtd->priv;
238 for (i = 0; i < len; i++)
239 if (buf[i] != readb(chip->IO_ADDR_R))
245 * nand_write_buf16 - [DEFAULT] write buffer to chip
246 * @mtd: MTD device structure
248 * @len: number of bytes to write
250 * Default write function for 16bit buswith
252 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
255 struct nand_chip *chip = mtd->priv;
256 u16 *p = (u16 *) buf;
259 for (i = 0; i < len; i++)
260 writew(p[i], chip->IO_ADDR_W);
265 * nand_read_buf16 - [DEFAULT] read chip data into buffer
266 * @mtd: MTD device structure
267 * @buf: buffer to store date
268 * @len: number of bytes to read
270 * Default read function for 16bit buswith
272 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
275 struct nand_chip *chip = mtd->priv;
276 u16 *p = (u16 *) buf;
279 for (i = 0; i < len; i++)
280 p[i] = readw(chip->IO_ADDR_R);
284 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
285 * @mtd: MTD device structure
286 * @buf: buffer containing the data to compare
287 * @len: number of bytes to compare
289 * Default verify function for 16bit buswith
291 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
294 struct nand_chip *chip = mtd->priv;
295 u16 *p = (u16 *) buf;
298 for (i = 0; i < len; i++)
299 if (p[i] != readw(chip->IO_ADDR_R))
306 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
307 * @mtd: MTD device structure
308 * @ofs: offset from device start
309 * @getchip: 0, if the chip is already selected
311 * Check, if the block is bad.
313 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
315 int page, chipnr, res = 0;
316 struct nand_chip *chip = mtd->priv;
319 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
322 chipnr = (int)(ofs >> chip->chip_shift);
324 nand_get_device(chip, mtd, FL_READING);
326 /* Select the NAND device */
327 chip->select_chip(mtd, chipnr);
330 if (chip->options & NAND_BUSWIDTH_16) {
331 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
333 bad = cpu_to_le16(chip->read_word(mtd));
334 if (chip->badblockpos & 0x1)
336 if ((bad & 0xFF) != 0xff)
339 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
340 if (chip->read_byte(mtd) != 0xff)
345 nand_release_device(mtd);
351 * nand_default_block_markbad - [DEFAULT] mark a block bad
352 * @mtd: MTD device structure
353 * @ofs: offset from device start
355 * This is the default implementation, which can be overridden by
356 * a hardware specific driver.
358 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
360 struct nand_chip *chip = mtd->priv;
361 uint8_t buf[2] = { 0, 0 };
364 /* Get block number */
365 block = (int)(ofs >> chip->bbt_erase_shift);
367 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
369 /* Do we have a flash based bad block table ? */
370 if (chip->options & NAND_USE_FLASH_BBT)
371 ret = nand_update_bbt(mtd, ofs);
373 /* We write two bytes, so we dont have to mess with 16 bit
376 nand_get_device(chip, mtd, FL_WRITING);
378 chip->ops.len = chip->ops.ooblen = 2;
379 chip->ops.datbuf = NULL;
380 chip->ops.oobbuf = buf;
381 chip->ops.ooboffs = chip->badblockpos & ~0x01;
383 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
384 nand_release_device(mtd);
387 mtd->ecc_stats.badblocks++;
393 * nand_check_wp - [GENERIC] check if the chip is write protected
394 * @mtd: MTD device structure
395 * Check, if the device is write protected
397 * The function expects, that the device is already selected
399 static int nand_check_wp(struct mtd_info *mtd)
401 struct nand_chip *chip = mtd->priv;
402 /* Check the WP bit */
403 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
404 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
408 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
409 * @mtd: MTD device structure
410 * @ofs: offset from device start
411 * @getchip: 0, if the chip is already selected
412 * @allowbbt: 1, if its allowed to access the bbt area
414 * Check, if the block is bad. Either by reading the bad block table or
415 * calling of the scan function.
417 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
420 struct nand_chip *chip = mtd->priv;
422 if (!(chip->options & NAND_BBT_SCANNED)) {
423 chip->options |= NAND_BBT_SCANNED;
428 return chip->block_bad(mtd, ofs, getchip);
430 /* Return info from the table */
431 return nand_isbad_bbt(mtd, ofs, allowbbt);
435 * Wait for the ready pin, after a command
436 * The timeout is catched later.
438 void nand_wait_ready(struct mtd_info *mtd)
440 struct nand_chip *chip = mtd->priv;
441 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
445 /* wait until command is processed or timeout occures */
446 while (get_timer(0) < timeo) {
448 if (chip->dev_ready(mtd))
454 * nand_command - [DEFAULT] Send command to NAND device
455 * @mtd: MTD device structure
456 * @command: the command to be sent
457 * @column: the column address for this command, -1 if none
458 * @page_addr: the page address for this command, -1 if none
460 * Send command to NAND device. This function is used for small page
461 * devices (256/512 Bytes per page)
463 static void nand_command(struct mtd_info *mtd, unsigned int command,
464 int column, int page_addr)
466 register struct nand_chip *chip = mtd->priv;
467 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
468 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
471 * Write out the command to the device.
473 if (command == NAND_CMD_SEQIN) {
476 if (column >= mtd->writesize) {
478 column -= mtd->writesize;
479 readcmd = NAND_CMD_READOOB;
480 } else if (column < 256) {
481 /* First 256 bytes --> READ0 */
482 readcmd = NAND_CMD_READ0;
485 readcmd = NAND_CMD_READ1;
487 chip->cmd_ctrl(mtd, readcmd, ctrl);
488 ctrl &= ~NAND_CTRL_CHANGE;
490 chip->cmd_ctrl(mtd, command, ctrl);
493 * Address cycle, when necessary
495 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
496 /* Serially input address */
498 /* Adjust columns for 16 bit buswidth */
499 if (chip->options & NAND_BUSWIDTH_16)
501 chip->cmd_ctrl(mtd, column, ctrl);
502 ctrl &= ~NAND_CTRL_CHANGE;
504 if (page_addr != -1) {
505 chip->cmd_ctrl(mtd, page_addr, ctrl);
506 ctrl &= ~NAND_CTRL_CHANGE;
507 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
508 /* One more address cycle for devices > 32MiB */
509 if (chip->chipsize > (32 << 20))
510 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
512 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
515 * program and erase have their own busy handlers
516 * status and sequential in needs no delay
520 case NAND_CMD_PAGEPROG:
521 case NAND_CMD_ERASE1:
522 case NAND_CMD_ERASE2:
524 case NAND_CMD_STATUS:
530 udelay(chip->chip_delay);
531 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
532 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
534 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
535 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
539 /* This applies to read commands */
542 * If we don't have access to the busy pin, we apply the given
545 if (!chip->dev_ready) {
546 udelay(chip->chip_delay);
550 /* Apply this short delay always to ensure that we do wait tWB in
551 * any case on any machine. */
554 nand_wait_ready(mtd);
558 * nand_command_lp - [DEFAULT] Send command to NAND large page device
559 * @mtd: MTD device structure
560 * @command: the command to be sent
561 * @column: the column address for this command, -1 if none
562 * @page_addr: the page address for this command, -1 if none
564 * Send command to NAND device. This is the version for the new large page
565 * devices We dont have the separate regions as we have in the small page
566 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
568 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
569 int column, int page_addr)
571 register struct nand_chip *chip = mtd->priv;
572 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
574 /* Emulate NAND_CMD_READOOB */
575 if (command == NAND_CMD_READOOB) {
576 column += mtd->writesize;
577 command = NAND_CMD_READ0;
580 /* Command latch cycle */
581 chip->cmd_ctrl(mtd, command & 0xff,
582 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
584 if (column != -1 || page_addr != -1) {
585 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
587 /* Serially input address */
589 /* Adjust columns for 16 bit buswidth */
590 if (chip->options & NAND_BUSWIDTH_16)
592 chip->cmd_ctrl(mtd, column, ctrl);
593 ctrl &= ~NAND_CTRL_CHANGE;
594 chip->cmd_ctrl(mtd, column >> 8, ctrl);
596 if (page_addr != -1) {
597 chip->cmd_ctrl(mtd, page_addr, ctrl);
598 chip->cmd_ctrl(mtd, page_addr >> 8,
599 NAND_NCE | NAND_ALE);
600 /* One more address cycle for devices > 128MiB */
601 if (chip->chipsize > (128 << 20))
602 chip->cmd_ctrl(mtd, page_addr >> 16,
603 NAND_NCE | NAND_ALE);
606 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
609 * program and erase have their own busy handlers
610 * status, sequential in, and deplete1 need no delay
614 case NAND_CMD_CACHEDPROG:
615 case NAND_CMD_PAGEPROG:
616 case NAND_CMD_ERASE1:
617 case NAND_CMD_ERASE2:
620 case NAND_CMD_STATUS:
621 case NAND_CMD_DEPLETE1:
625 * read error status commands require only a short delay
627 case NAND_CMD_STATUS_ERROR:
628 case NAND_CMD_STATUS_ERROR0:
629 case NAND_CMD_STATUS_ERROR1:
630 case NAND_CMD_STATUS_ERROR2:
631 case NAND_CMD_STATUS_ERROR3:
632 udelay(chip->chip_delay);
638 udelay(chip->chip_delay);
639 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
640 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
641 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
642 NAND_NCE | NAND_CTRL_CHANGE);
643 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
647 case NAND_CMD_RNDOUT:
648 /* No ready / busy check necessary */
649 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
650 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
651 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
652 NAND_NCE | NAND_CTRL_CHANGE);
656 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
657 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
658 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
659 NAND_NCE | NAND_CTRL_CHANGE);
661 /* This applies to read commands */
664 * If we don't have access to the busy pin, we apply the given
667 if (!chip->dev_ready) {
668 udelay(chip->chip_delay);
673 /* Apply this short delay always to ensure that we do wait tWB in
674 * any case on any machine. */
677 nand_wait_ready(mtd);
681 * nand_get_device - [GENERIC] Get chip for selected access
682 * @chip: the nand chip descriptor
683 * @mtd: MTD device structure
684 * @new_state: the state which is requested
686 * Get the device and lock it for exclusive access
688 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
690 this->state = new_state;
695 * nand_wait - [DEFAULT] wait until the command is done
696 * @mtd: MTD device structure
697 * @chip: NAND chip structure
699 * Wait for command done. This applies to erase and program only
700 * Erase can take up to 400ms and program up to 20ms according to
701 * general NAND and SmartMedia specs
703 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
706 int state = this->state;
708 if (state == FL_ERASING)
709 timeo = (CONFIG_SYS_HZ * 400) / 1000;
711 timeo = (CONFIG_SYS_HZ * 20) / 1000;
713 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
714 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
716 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
721 if (get_timer(0) > timeo) {
726 if (this->dev_ready) {
727 if (this->dev_ready(mtd))
730 if (this->read_byte(mtd) & NAND_STATUS_READY)
734 #ifdef PPCHAMELON_NAND_TIMER_HACK
736 while (get_timer(0) < 10);
737 #endif /* PPCHAMELON_NAND_TIMER_HACK */
739 return this->read_byte(mtd);
743 * nand_read_page_raw - [Intern] read raw page data without ecc
744 * @mtd: mtd info structure
745 * @chip: nand chip info structure
746 * @buf: buffer to store read data
747 * @page: page number to read
749 * Not for syndrome calculating ecc controllers, which use a special oob layout
751 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
752 uint8_t *buf, int page)
754 chip->read_buf(mtd, buf, mtd->writesize);
755 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
760 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
761 * @mtd: mtd info structure
762 * @chip: nand chip info structure
763 * @buf: buffer to store read data
764 * @page: page number to read
766 * We need a special oob layout and handling even when OOB isn't used.
768 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
769 uint8_t *buf, int page)
771 int eccsize = chip->ecc.size;
772 int eccbytes = chip->ecc.bytes;
773 uint8_t *oob = chip->oob_poi;
776 for (steps = chip->ecc.steps; steps > 0; steps--) {
777 chip->read_buf(mtd, buf, eccsize);
780 if (chip->ecc.prepad) {
781 chip->read_buf(mtd, oob, chip->ecc.prepad);
782 oob += chip->ecc.prepad;
785 chip->read_buf(mtd, oob, eccbytes);
788 if (chip->ecc.postpad) {
789 chip->read_buf(mtd, oob, chip->ecc.postpad);
790 oob += chip->ecc.postpad;
794 size = mtd->oobsize - (oob - chip->oob_poi);
796 chip->read_buf(mtd, oob, size);
802 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
803 * @mtd: mtd info structure
804 * @chip: nand chip info structure
805 * @buf: buffer to store read data
806 * @page: page number to read
808 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
809 uint8_t *buf, int page)
811 int i, eccsize = chip->ecc.size;
812 int eccbytes = chip->ecc.bytes;
813 int eccsteps = chip->ecc.steps;
815 uint8_t *ecc_calc = chip->buffers->ecccalc;
816 uint8_t *ecc_code = chip->buffers->ecccode;
817 uint32_t *eccpos = chip->ecc.layout->eccpos;
819 chip->ecc.read_page_raw(mtd, chip, buf, page);
821 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
822 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
824 for (i = 0; i < chip->ecc.total; i++)
825 ecc_code[i] = chip->oob_poi[eccpos[i]];
827 eccsteps = chip->ecc.steps;
830 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
833 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
835 mtd->ecc_stats.failed++;
837 mtd->ecc_stats.corrected += stat;
843 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
844 * @mtd: mtd info structure
845 * @chip: nand chip info structure
846 * @data_offs: offset of requested data within the page
847 * @readlen: data length
848 * @bufpoi: buffer to store read data
850 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
852 int start_step, end_step, num_steps;
853 uint32_t *eccpos = chip->ecc.layout->eccpos;
855 int data_col_addr, i, gaps = 0;
856 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
857 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
859 /* Column address wihin the page aligned to ECC size (256bytes). */
860 start_step = data_offs / chip->ecc.size;
861 end_step = (data_offs + readlen - 1) / chip->ecc.size;
862 num_steps = end_step - start_step + 1;
864 /* Data size aligned to ECC ecc.size*/
865 datafrag_len = num_steps * chip->ecc.size;
866 eccfrag_len = num_steps * chip->ecc.bytes;
868 data_col_addr = start_step * chip->ecc.size;
869 /* If we read not a page aligned data */
870 if (data_col_addr != 0)
871 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
873 p = bufpoi + data_col_addr;
874 chip->read_buf(mtd, p, datafrag_len);
877 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
878 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
880 /* The performance is faster if to position offsets
881 according to ecc.pos. Let make sure here that
882 there are no gaps in ecc positions */
883 for (i = 0; i < eccfrag_len - 1; i++) {
884 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
885 eccpos[i + start_step * chip->ecc.bytes + 1]) {
891 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
892 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
894 /* send the command to read the particular ecc bytes */
895 /* take care about buswidth alignment in read_buf */
896 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
897 aligned_len = eccfrag_len;
898 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
900 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
903 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
904 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
907 for (i = 0; i < eccfrag_len; i++)
908 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
910 p = bufpoi + data_col_addr;
911 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
914 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
916 mtd->ecc_stats.failed++;
918 mtd->ecc_stats.corrected += stat;
924 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
925 * @mtd: mtd info structure
926 * @chip: nand chip info structure
927 * @buf: buffer to store read data
928 * @page: page number to read
930 * Not for syndrome calculating ecc controllers which need a special oob layout
932 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
933 uint8_t *buf, int page)
935 int i, eccsize = chip->ecc.size;
936 int eccbytes = chip->ecc.bytes;
937 int eccsteps = chip->ecc.steps;
939 uint8_t *ecc_calc = chip->buffers->ecccalc;
940 uint8_t *ecc_code = chip->buffers->ecccode;
941 uint32_t *eccpos = chip->ecc.layout->eccpos;
943 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
944 chip->ecc.hwctl(mtd, NAND_ECC_READ);
945 chip->read_buf(mtd, p, eccsize);
946 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
948 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
950 for (i = 0; i < chip->ecc.total; i++)
951 ecc_code[i] = chip->oob_poi[eccpos[i]];
953 eccsteps = chip->ecc.steps;
956 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
959 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
961 mtd->ecc_stats.failed++;
963 mtd->ecc_stats.corrected += stat;
969 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
970 * @mtd: mtd info structure
971 * @chip: nand chip info structure
972 * @buf: buffer to store read data
973 * @page: page number to read
975 * Hardware ECC for large page chips, require OOB to be read first.
976 * For this ECC mode, the write_page method is re-used from ECC_HW.
977 * These methods read/write ECC from the OOB area, unlike the
978 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
979 * "infix ECC" scheme and reads/writes ECC from the data area, by
980 * overwriting the NAND manufacturer bad block markings.
982 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
983 struct nand_chip *chip, uint8_t *buf, int page)
985 int i, eccsize = chip->ecc.size;
986 int eccbytes = chip->ecc.bytes;
987 int eccsteps = chip->ecc.steps;
989 uint8_t *ecc_code = chip->buffers->ecccode;
990 uint32_t *eccpos = chip->ecc.layout->eccpos;
991 uint8_t *ecc_calc = chip->buffers->ecccalc;
993 /* Read the OOB area first */
994 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
995 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
996 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
998 for (i = 0; i < chip->ecc.total; i++)
999 ecc_code[i] = chip->oob_poi[eccpos[i]];
1001 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1004 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1005 chip->read_buf(mtd, p, eccsize);
1006 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1008 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1010 mtd->ecc_stats.failed++;
1012 mtd->ecc_stats.corrected += stat;
1018 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1019 * @mtd: mtd info structure
1020 * @chip: nand chip info structure
1021 * @buf: buffer to store read data
1022 * @page: page number to read
1024 * The hw generator calculates the error syndrome automatically. Therefor
1025 * we need a special oob layout and handling.
1027 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1028 uint8_t *buf, int page)
1030 int i, eccsize = chip->ecc.size;
1031 int eccbytes = chip->ecc.bytes;
1032 int eccsteps = chip->ecc.steps;
1034 uint8_t *oob = chip->oob_poi;
1036 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1039 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1040 chip->read_buf(mtd, p, eccsize);
1042 if (chip->ecc.prepad) {
1043 chip->read_buf(mtd, oob, chip->ecc.prepad);
1044 oob += chip->ecc.prepad;
1047 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1048 chip->read_buf(mtd, oob, eccbytes);
1049 stat = chip->ecc.correct(mtd, p, oob, NULL);
1052 mtd->ecc_stats.failed++;
1054 mtd->ecc_stats.corrected += stat;
1058 if (chip->ecc.postpad) {
1059 chip->read_buf(mtd, oob, chip->ecc.postpad);
1060 oob += chip->ecc.postpad;
1064 /* Calculate remaining oob bytes */
1065 i = mtd->oobsize - (oob - chip->oob_poi);
1067 chip->read_buf(mtd, oob, i);
1073 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1074 * @chip: nand chip structure
1075 * @oob: oob destination address
1076 * @ops: oob ops structure
1077 * @len: size of oob to transfer
1079 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1080 struct mtd_oob_ops *ops, size_t len)
1086 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1089 case MTD_OOB_AUTO: {
1090 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1091 uint32_t boffs = 0, roffs = ops->ooboffs;
1094 for(; free->length && len; free++, len -= bytes) {
1095 /* Read request not from offset 0 ? */
1096 if (unlikely(roffs)) {
1097 if (roffs >= free->length) {
1098 roffs -= free->length;
1101 boffs = free->offset + roffs;
1102 bytes = min_t(size_t, len,
1103 (free->length - roffs));
1106 bytes = min_t(size_t, len, free->length);
1107 boffs = free->offset;
1109 memcpy(oob, chip->oob_poi + boffs, bytes);
1121 * nand_do_read_ops - [Internal] Read data with ECC
1123 * @mtd: MTD device structure
1124 * @from: offset to read from
1125 * @ops: oob ops structure
1127 * Internal function. Called with chip held.
1129 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1130 struct mtd_oob_ops *ops)
1132 int chipnr, page, realpage, col, bytes, aligned;
1133 struct nand_chip *chip = mtd->priv;
1134 struct mtd_ecc_stats stats;
1135 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1138 uint32_t readlen = ops->len;
1139 uint32_t oobreadlen = ops->ooblen;
1140 uint8_t *bufpoi, *oob, *buf;
1142 stats = mtd->ecc_stats;
1144 chipnr = (int)(from >> chip->chip_shift);
1145 chip->select_chip(mtd, chipnr);
1147 realpage = (int)(from >> chip->page_shift);
1148 page = realpage & chip->pagemask;
1150 col = (int)(from & (mtd->writesize - 1));
1156 bytes = min(mtd->writesize - col, readlen);
1157 aligned = (bytes == mtd->writesize);
1159 /* Is the current page in the buffer ? */
1160 if (realpage != chip->pagebuf || oob) {
1161 bufpoi = aligned ? buf : chip->buffers->databuf;
1163 if (likely(sndcmd)) {
1164 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1168 /* Now read the page into the buffer */
1169 if (unlikely(ops->mode == MTD_OOB_RAW))
1170 ret = chip->ecc.read_page_raw(mtd, chip,
1172 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1173 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1175 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1180 /* Transfer not aligned data */
1182 if (!NAND_SUBPAGE_READ(chip) && !oob)
1183 chip->pagebuf = realpage;
1184 memcpy(buf, chip->buffers->databuf + col, bytes);
1189 if (unlikely(oob)) {
1190 /* Raw mode does data:oob:data:oob */
1191 if (ops->mode != MTD_OOB_RAW) {
1192 int toread = min(oobreadlen,
1193 chip->ecc.layout->oobavail);
1195 oob = nand_transfer_oob(chip,
1197 oobreadlen -= toread;
1200 buf = nand_transfer_oob(chip,
1201 buf, ops, mtd->oobsize);
1204 if (!(chip->options & NAND_NO_READRDY)) {
1206 * Apply delay or wait for ready/busy pin. Do
1207 * this before the AUTOINCR check, so no
1208 * problems arise if a chip which does auto
1209 * increment is marked as NOAUTOINCR by the
1212 if (!chip->dev_ready)
1213 udelay(chip->chip_delay);
1215 nand_wait_ready(mtd);
1218 memcpy(buf, chip->buffers->databuf + col, bytes);
1227 /* For subsequent reads align to page boundary. */
1229 /* Increment page address */
1232 page = realpage & chip->pagemask;
1233 /* Check, if we cross a chip boundary */
1236 chip->select_chip(mtd, -1);
1237 chip->select_chip(mtd, chipnr);
1240 /* Check, if the chip supports auto page increment
1241 * or if we have hit a block boundary.
1243 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1247 ops->retlen = ops->len - (size_t) readlen;
1249 ops->oobretlen = ops->ooblen - oobreadlen;
1254 if (mtd->ecc_stats.failed - stats.failed)
1257 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1261 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1262 * @mtd: MTD device structure
1263 * @from: offset to read from
1264 * @len: number of bytes to read
1265 * @retlen: pointer to variable to store the number of read bytes
1266 * @buf: the databuffer to put data
1268 * Get hold of the chip and call nand_do_read
1270 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1271 size_t *retlen, uint8_t *buf)
1273 struct nand_chip *chip = mtd->priv;
1276 /* Do not allow reads past end of device */
1277 if ((from + len) > mtd->size)
1282 nand_get_device(chip, mtd, FL_READING);
1284 chip->ops.len = len;
1285 chip->ops.datbuf = buf;
1286 chip->ops.oobbuf = NULL;
1288 ret = nand_do_read_ops(mtd, from, &chip->ops);
1290 *retlen = chip->ops.retlen;
1292 nand_release_device(mtd);
1298 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1299 * @mtd: mtd info structure
1300 * @chip: nand chip info structure
1301 * @page: page number to read
1302 * @sndcmd: flag whether to issue read command or not
1304 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1305 int page, int sndcmd)
1308 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1311 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1316 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1318 * @mtd: mtd info structure
1319 * @chip: nand chip info structure
1320 * @page: page number to read
1321 * @sndcmd: flag whether to issue read command or not
1323 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1324 int page, int sndcmd)
1326 uint8_t *buf = chip->oob_poi;
1327 int length = mtd->oobsize;
1328 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1329 int eccsize = chip->ecc.size;
1330 uint8_t *bufpoi = buf;
1331 int i, toread, sndrnd = 0, pos;
1333 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1334 for (i = 0; i < chip->ecc.steps; i++) {
1336 pos = eccsize + i * (eccsize + chunk);
1337 if (mtd->writesize > 512)
1338 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1340 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1343 toread = min_t(int, length, chunk);
1344 chip->read_buf(mtd, bufpoi, toread);
1349 chip->read_buf(mtd, bufpoi, length);
1355 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1356 * @mtd: mtd info structure
1357 * @chip: nand chip info structure
1358 * @page: page number to write
1360 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1364 const uint8_t *buf = chip->oob_poi;
1365 int length = mtd->oobsize;
1367 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1368 chip->write_buf(mtd, buf, length);
1369 /* Send command to program the OOB data */
1370 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1372 status = chip->waitfunc(mtd, chip);
1374 return status & NAND_STATUS_FAIL ? -EIO : 0;
1378 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1379 * with syndrome - only for large page flash !
1380 * @mtd: mtd info structure
1381 * @chip: nand chip info structure
1382 * @page: page number to write
1384 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1385 struct nand_chip *chip, int page)
1387 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1388 int eccsize = chip->ecc.size, length = mtd->oobsize;
1389 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1390 const uint8_t *bufpoi = chip->oob_poi;
1393 * data-ecc-data-ecc ... ecc-oob
1395 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1397 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1398 pos = steps * (eccsize + chunk);
1403 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1404 for (i = 0; i < steps; i++) {
1406 if (mtd->writesize <= 512) {
1407 uint32_t fill = 0xFFFFFFFF;
1411 int num = min_t(int, len, 4);
1412 chip->write_buf(mtd, (uint8_t *)&fill,
1417 pos = eccsize + i * (eccsize + chunk);
1418 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1422 len = min_t(int, length, chunk);
1423 chip->write_buf(mtd, bufpoi, len);
1428 chip->write_buf(mtd, bufpoi, length);
1430 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1431 status = chip->waitfunc(mtd, chip);
1433 return status & NAND_STATUS_FAIL ? -EIO : 0;
1437 * nand_do_read_oob - [Intern] NAND read out-of-band
1438 * @mtd: MTD device structure
1439 * @from: offset to read from
1440 * @ops: oob operations description structure
1442 * NAND read out-of-band data from the spare area
1444 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1445 struct mtd_oob_ops *ops)
1447 int page, realpage, chipnr, sndcmd = 1;
1448 struct nand_chip *chip = mtd->priv;
1449 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1450 int readlen = ops->ooblen;
1452 uint8_t *buf = ops->oobbuf;
1454 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1455 (unsigned long long)from, readlen);
1457 if (ops->mode == MTD_OOB_AUTO)
1458 len = chip->ecc.layout->oobavail;
1462 if (unlikely(ops->ooboffs >= len)) {
1463 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1464 "Attempt to start read outside oob\n");
1468 /* Do not allow reads past end of device */
1469 if (unlikely(from >= mtd->size ||
1470 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1471 (from >> chip->page_shift)) * len)) {
1472 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1473 "Attempt read beyond end of device\n");
1477 chipnr = (int)(from >> chip->chip_shift);
1478 chip->select_chip(mtd, chipnr);
1480 /* Shift to get page */
1481 realpage = (int)(from >> chip->page_shift);
1482 page = realpage & chip->pagemask;
1485 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1487 len = min(len, readlen);
1488 buf = nand_transfer_oob(chip, buf, ops, len);
1490 if (!(chip->options & NAND_NO_READRDY)) {
1492 * Apply delay or wait for ready/busy pin. Do this
1493 * before the AUTOINCR check, so no problems arise if a
1494 * chip which does auto increment is marked as
1495 * NOAUTOINCR by the board driver.
1497 if (!chip->dev_ready)
1498 udelay(chip->chip_delay);
1500 nand_wait_ready(mtd);
1507 /* Increment page address */
1510 page = realpage & chip->pagemask;
1511 /* Check, if we cross a chip boundary */
1514 chip->select_chip(mtd, -1);
1515 chip->select_chip(mtd, chipnr);
1518 /* Check, if the chip supports auto page increment
1519 * or if we have hit a block boundary.
1521 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1525 ops->oobretlen = ops->ooblen;
1530 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1531 * @mtd: MTD device structure
1532 * @from: offset to read from
1533 * @ops: oob operation description structure
1535 * NAND read data and/or out-of-band data
1537 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1538 struct mtd_oob_ops *ops)
1540 struct nand_chip *chip = mtd->priv;
1541 int ret = -ENOTSUPP;
1545 /* Do not allow reads past end of device */
1546 if (ops->datbuf && (from + ops->len) > mtd->size) {
1547 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1548 "Attempt read beyond end of device\n");
1552 nand_get_device(chip, mtd, FL_READING);
1565 ret = nand_do_read_oob(mtd, from, ops);
1567 ret = nand_do_read_ops(mtd, from, ops);
1570 nand_release_device(mtd);
1576 * nand_write_page_raw - [Intern] raw page write function
1577 * @mtd: mtd info structure
1578 * @chip: nand chip info structure
1581 * Not for syndrome calculating ecc controllers, which use a special oob layout
1583 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1586 chip->write_buf(mtd, buf, mtd->writesize);
1587 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1591 * nand_write_page_raw_syndrome - [Intern] raw page write function
1592 * @mtd: mtd info structure
1593 * @chip: nand chip info structure
1596 * We need a special oob layout and handling even when ECC isn't checked.
1598 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1601 int eccsize = chip->ecc.size;
1602 int eccbytes = chip->ecc.bytes;
1603 uint8_t *oob = chip->oob_poi;
1606 for (steps = chip->ecc.steps; steps > 0; steps--) {
1607 chip->write_buf(mtd, buf, eccsize);
1610 if (chip->ecc.prepad) {
1611 chip->write_buf(mtd, oob, chip->ecc.prepad);
1612 oob += chip->ecc.prepad;
1615 chip->read_buf(mtd, oob, eccbytes);
1618 if (chip->ecc.postpad) {
1619 chip->write_buf(mtd, oob, chip->ecc.postpad);
1620 oob += chip->ecc.postpad;
1624 size = mtd->oobsize - (oob - chip->oob_poi);
1626 chip->write_buf(mtd, oob, size);
1629 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1630 * @mtd: mtd info structure
1631 * @chip: nand chip info structure
1634 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1637 int i, eccsize = chip->ecc.size;
1638 int eccbytes = chip->ecc.bytes;
1639 int eccsteps = chip->ecc.steps;
1640 uint8_t *ecc_calc = chip->buffers->ecccalc;
1641 const uint8_t *p = buf;
1642 uint32_t *eccpos = chip->ecc.layout->eccpos;
1644 /* Software ecc calculation */
1645 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1646 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1648 for (i = 0; i < chip->ecc.total; i++)
1649 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1651 chip->ecc.write_page_raw(mtd, chip, buf);
1655 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1656 * @mtd: mtd info structure
1657 * @chip: nand chip info structure
1660 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1663 int i, eccsize = chip->ecc.size;
1664 int eccbytes = chip->ecc.bytes;
1665 int eccsteps = chip->ecc.steps;
1666 uint8_t *ecc_calc = chip->buffers->ecccalc;
1667 const uint8_t *p = buf;
1668 uint32_t *eccpos = chip->ecc.layout->eccpos;
1670 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1671 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1672 chip->write_buf(mtd, p, eccsize);
1673 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1676 for (i = 0; i < chip->ecc.total; i++)
1677 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1679 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1683 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1684 * @mtd: mtd info structure
1685 * @chip: nand chip info structure
1688 * The hw generator calculates the error syndrome automatically. Therefor
1689 * we need a special oob layout and handling.
1691 static void nand_write_page_syndrome(struct mtd_info *mtd,
1692 struct nand_chip *chip, const uint8_t *buf)
1694 int i, eccsize = chip->ecc.size;
1695 int eccbytes = chip->ecc.bytes;
1696 int eccsteps = chip->ecc.steps;
1697 const uint8_t *p = buf;
1698 uint8_t *oob = chip->oob_poi;
1700 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1702 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1703 chip->write_buf(mtd, p, eccsize);
1705 if (chip->ecc.prepad) {
1706 chip->write_buf(mtd, oob, chip->ecc.prepad);
1707 oob += chip->ecc.prepad;
1710 chip->ecc.calculate(mtd, p, oob);
1711 chip->write_buf(mtd, oob, eccbytes);
1714 if (chip->ecc.postpad) {
1715 chip->write_buf(mtd, oob, chip->ecc.postpad);
1716 oob += chip->ecc.postpad;
1720 /* Calculate remaining oob bytes */
1721 i = mtd->oobsize - (oob - chip->oob_poi);
1723 chip->write_buf(mtd, oob, i);
1727 * nand_write_page - [REPLACEABLE] write one page
1728 * @mtd: MTD device structure
1729 * @chip: NAND chip descriptor
1730 * @buf: the data to write
1731 * @page: page number to write
1732 * @cached: cached programming
1733 * @raw: use _raw version of write_page
1735 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1736 const uint8_t *buf, int page, int cached, int raw)
1740 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1743 chip->ecc.write_page_raw(mtd, chip, buf);
1745 chip->ecc.write_page(mtd, chip, buf);
1748 * Cached progamming disabled for now, Not sure if its worth the
1749 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1753 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1755 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1756 status = chip->waitfunc(mtd, chip);
1758 * See if operation failed and additional status checks are
1761 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1762 status = chip->errstat(mtd, chip, FL_WRITING, status,
1765 if (status & NAND_STATUS_FAIL)
1768 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1769 status = chip->waitfunc(mtd, chip);
1772 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1773 /* Send command to read back the data */
1774 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1776 if (chip->verify_buf(mtd, buf, mtd->writesize))
1783 * nand_fill_oob - [Internal] Transfer client buffer to oob
1784 * @chip: nand chip structure
1785 * @oob: oob data buffer
1786 * @ops: oob ops structure
1788 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1789 struct mtd_oob_ops *ops)
1791 size_t len = ops->ooblen;
1797 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1800 case MTD_OOB_AUTO: {
1801 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1802 uint32_t boffs = 0, woffs = ops->ooboffs;
1805 for(; free->length && len; free++, len -= bytes) {
1806 /* Write request not from offset 0 ? */
1807 if (unlikely(woffs)) {
1808 if (woffs >= free->length) {
1809 woffs -= free->length;
1812 boffs = free->offset + woffs;
1813 bytes = min_t(size_t, len,
1814 (free->length - woffs));
1817 bytes = min_t(size_t, len, free->length);
1818 boffs = free->offset;
1820 memcpy(chip->oob_poi + boffs, oob, bytes);
1831 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1834 * nand_do_write_ops - [Internal] NAND write with ECC
1835 * @mtd: MTD device structure
1836 * @to: offset to write to
1837 * @ops: oob operations description structure
1839 * NAND write with ECC
1841 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1842 struct mtd_oob_ops *ops)
1844 int chipnr, realpage, page, blockmask, column;
1845 struct nand_chip *chip = mtd->priv;
1846 uint32_t writelen = ops->len;
1847 uint8_t *oob = ops->oobbuf;
1848 uint8_t *buf = ops->datbuf;
1855 column = to & (mtd->writesize - 1);
1856 subpage = column || (writelen & (mtd->writesize - 1));
1861 chipnr = (int)(to >> chip->chip_shift);
1862 chip->select_chip(mtd, chipnr);
1864 /* Check, if it is write protected */
1865 if (nand_check_wp(mtd)) {
1866 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1870 realpage = (int)(to >> chip->page_shift);
1871 page = realpage & chip->pagemask;
1872 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1874 /* Invalidate the page cache, when we write to the cached page */
1875 if (to <= (chip->pagebuf << chip->page_shift) &&
1876 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1879 /* If we're not given explicit OOB data, let it be 0xFF */
1881 memset(chip->oob_poi, 0xff, mtd->oobsize);
1884 int bytes = mtd->writesize;
1885 int cached = writelen > bytes && page != blockmask;
1886 uint8_t *wbuf = buf;
1888 /* Partial page write ? */
1889 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1891 bytes = min_t(int, bytes - column, (int) writelen);
1893 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1894 memcpy(&chip->buffers->databuf[column], buf, bytes);
1895 wbuf = chip->buffers->databuf;
1899 oob = nand_fill_oob(chip, oob, ops);
1901 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1902 (ops->mode == MTD_OOB_RAW));
1914 page = realpage & chip->pagemask;
1915 /* Check, if we cross a chip boundary */
1918 chip->select_chip(mtd, -1);
1919 chip->select_chip(mtd, chipnr);
1923 ops->retlen = ops->len - writelen;
1925 ops->oobretlen = ops->ooblen;
1930 * nand_write - [MTD Interface] NAND write with ECC
1931 * @mtd: MTD device structure
1932 * @to: offset to write to
1933 * @len: number of bytes to write
1934 * @retlen: pointer to variable to store the number of written bytes
1935 * @buf: the data to write
1937 * NAND write with ECC
1939 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1940 size_t *retlen, const uint8_t *buf)
1942 struct nand_chip *chip = mtd->priv;
1945 /* Do not allow reads past end of device */
1946 if ((to + len) > mtd->size)
1951 nand_get_device(chip, mtd, FL_WRITING);
1953 chip->ops.len = len;
1954 chip->ops.datbuf = (uint8_t *)buf;
1955 chip->ops.oobbuf = NULL;
1957 ret = nand_do_write_ops(mtd, to, &chip->ops);
1959 *retlen = chip->ops.retlen;
1961 nand_release_device(mtd);
1967 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1968 * @mtd: MTD device structure
1969 * @to: offset to write to
1970 * @ops: oob operation description structure
1972 * NAND write out-of-band
1974 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1975 struct mtd_oob_ops *ops)
1977 int chipnr, page, status, len;
1978 struct nand_chip *chip = mtd->priv;
1980 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1981 (unsigned int)to, (int)ops->ooblen);
1983 if (ops->mode == MTD_OOB_AUTO)
1984 len = chip->ecc.layout->oobavail;
1988 /* Do not allow write past end of page */
1989 if ((ops->ooboffs + ops->ooblen) > len) {
1990 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1991 "Attempt to write past end of page\n");
1995 if (unlikely(ops->ooboffs >= len)) {
1996 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1997 "Attempt to start write outside oob\n");
2001 /* Do not allow reads past end of device */
2002 if (unlikely(to >= mtd->size ||
2003 ops->ooboffs + ops->ooblen >
2004 ((mtd->size >> chip->page_shift) -
2005 (to >> chip->page_shift)) * len)) {
2006 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2007 "Attempt write beyond end of device\n");
2011 chipnr = (int)(to >> chip->chip_shift);
2012 chip->select_chip(mtd, chipnr);
2014 /* Shift to get page */
2015 page = (int)(to >> chip->page_shift);
2018 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2019 * of my DiskOnChip 2000 test units) will clear the whole data page too
2020 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2021 * it in the doc2000 driver in August 1999. dwmw2.
2023 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2025 /* Check, if it is write protected */
2026 if (nand_check_wp(mtd))
2029 /* Invalidate the page cache, if we write to the cached page */
2030 if (page == chip->pagebuf)
2033 memset(chip->oob_poi, 0xff, mtd->oobsize);
2034 nand_fill_oob(chip, ops->oobbuf, ops);
2035 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2036 memset(chip->oob_poi, 0xff, mtd->oobsize);
2041 ops->oobretlen = ops->ooblen;
2047 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2048 * @mtd: MTD device structure
2049 * @to: offset to write to
2050 * @ops: oob operation description structure
2052 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2053 struct mtd_oob_ops *ops)
2055 struct nand_chip *chip = mtd->priv;
2056 int ret = -ENOTSUPP;
2060 /* Do not allow writes past end of device */
2061 if (ops->datbuf && (to + ops->len) > mtd->size) {
2062 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2063 "Attempt read beyond end of device\n");
2067 nand_get_device(chip, mtd, FL_WRITING);
2080 ret = nand_do_write_oob(mtd, to, ops);
2082 ret = nand_do_write_ops(mtd, to, ops);
2085 nand_release_device(mtd);
2090 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2091 * @mtd: MTD device structure
2092 * @page: the page address of the block which will be erased
2094 * Standard erase command for NAND chips
2096 static void single_erase_cmd(struct mtd_info *mtd, int page)
2098 struct nand_chip *chip = mtd->priv;
2099 /* Send commands to erase a block */
2100 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2101 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2105 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2106 * @mtd: MTD device structure
2107 * @page: the page address of the block which will be erased
2109 * AND multi block erase command function
2110 * Erase 4 consecutive blocks
2112 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2114 struct nand_chip *chip = mtd->priv;
2115 /* Send commands to erase a block */
2116 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2117 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2118 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2119 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2120 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2124 * nand_erase - [MTD Interface] erase block(s)
2125 * @mtd: MTD device structure
2126 * @instr: erase instruction
2128 * Erase one ore more blocks
2130 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2132 return nand_erase_nand(mtd, instr, 0);
2135 #define BBT_PAGE_MASK 0xffffff3f
2137 * nand_erase_nand - [Internal] erase block(s)
2138 * @mtd: MTD device structure
2139 * @instr: erase instruction
2140 * @allowbbt: allow erasing the bbt area
2142 * Erase one ore more blocks
2144 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2147 int page, status, pages_per_block, ret, chipnr;
2148 struct nand_chip *chip = mtd->priv;
2149 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2150 unsigned int bbt_masked_page = 0xffffffff;
2153 MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2154 "len = %llu\n", (unsigned long long) instr->addr,
2155 (unsigned long long) instr->len);
2157 /* Start address must align on block boundary */
2158 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2159 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2163 /* Length must align on block boundary */
2164 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2165 MTDDEBUG (MTD_DEBUG_LEVEL0,
2166 "nand_erase: Length not block aligned\n");
2170 /* Do not allow erase past end of device */
2171 if ((instr->len + instr->addr) > mtd->size) {
2172 MTDDEBUG (MTD_DEBUG_LEVEL0,
2173 "nand_erase: Erase past end of device\n");
2177 instr->fail_addr = 0xffffffff;
2179 /* Grab the lock and see if the device is available */
2180 nand_get_device(chip, mtd, FL_ERASING);
2182 /* Shift to get first page */
2183 page = (int)(instr->addr >> chip->page_shift);
2184 chipnr = (int)(instr->addr >> chip->chip_shift);
2186 /* Calculate pages in each block */
2187 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2189 /* Select the NAND device */
2190 chip->select_chip(mtd, chipnr);
2192 /* Check, if it is write protected */
2193 if (nand_check_wp(mtd)) {
2194 MTDDEBUG (MTD_DEBUG_LEVEL0,
2195 "nand_erase: Device is write protected!!!\n");
2196 instr->state = MTD_ERASE_FAILED;
2201 * If BBT requires refresh, set the BBT page mask to see if the BBT
2202 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2203 * can not be matched. This is also done when the bbt is actually
2204 * erased to avoid recusrsive updates
2206 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2207 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2209 /* Loop through the pages */
2212 instr->state = MTD_ERASING;
2216 * heck if we have a bad block, we do not erase bad blocks !
2218 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2219 chip->page_shift, 0, allowbbt)) {
2220 printk(KERN_WARNING "nand_erase: attempt to erase a "
2221 "bad block at page 0x%08x\n", page);
2222 instr->state = MTD_ERASE_FAILED;
2227 * Invalidate the page cache, if we erase the block which
2228 * contains the current cached page
2230 if (page <= chip->pagebuf && chip->pagebuf <
2231 (page + pages_per_block))
2234 chip->erase_cmd(mtd, page & chip->pagemask);
2236 status = chip->waitfunc(mtd, chip);
2239 * See if operation failed and additional status checks are
2242 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2243 status = chip->errstat(mtd, chip, FL_ERASING,
2246 /* See if block erase succeeded */
2247 if (status & NAND_STATUS_FAIL) {
2248 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2249 "Failed erase, page 0x%08x\n", page);
2250 instr->state = MTD_ERASE_FAILED;
2251 instr->fail_addr = ((loff_t)page << chip->page_shift);
2256 * If BBT requires refresh, set the BBT rewrite flag to the
2259 if (bbt_masked_page != 0xffffffff &&
2260 (page & BBT_PAGE_MASK) == bbt_masked_page)
2261 rewrite_bbt[chipnr] =
2262 ((loff_t)page << chip->page_shift);
2264 /* Increment page address and decrement length */
2265 len -= (1 << chip->phys_erase_shift);
2266 page += pages_per_block;
2268 /* Check, if we cross a chip boundary */
2269 if (len && !(page & chip->pagemask)) {
2271 chip->select_chip(mtd, -1);
2272 chip->select_chip(mtd, chipnr);
2275 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2276 * page mask to see if this BBT should be rewritten
2278 if (bbt_masked_page != 0xffffffff &&
2279 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2280 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2284 instr->state = MTD_ERASE_DONE;
2288 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2290 /* Deselect and wake up anyone waiting on the device */
2291 nand_release_device(mtd);
2293 /* Do call back function */
2295 mtd_erase_callback(instr);
2298 * If BBT requires refresh and erase was successful, rewrite any
2299 * selected bad block tables
2301 if (bbt_masked_page == 0xffffffff || ret)
2304 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2305 if (!rewrite_bbt[chipnr])
2307 /* update the BBT for chip */
2308 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2309 "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2310 chip->bbt_td->pages[chipnr]);
2311 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2314 /* Return more or less happy */
2319 * nand_sync - [MTD Interface] sync
2320 * @mtd: MTD device structure
2322 * Sync is actually a wait for chip ready function
2324 static void nand_sync(struct mtd_info *mtd)
2326 struct nand_chip *chip = mtd->priv;
2328 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2330 /* Grab the lock and see if the device is available */
2331 nand_get_device(chip, mtd, FL_SYNCING);
2332 /* Release it and go back */
2333 nand_release_device(mtd);
2337 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2338 * @mtd: MTD device structure
2339 * @offs: offset relative to mtd start
2341 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2343 /* Check for invalid offset */
2344 if (offs > mtd->size)
2347 return nand_block_checkbad(mtd, offs, 1, 0);
2351 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2352 * @mtd: MTD device structure
2353 * @ofs: offset relative to mtd start
2355 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2357 struct nand_chip *chip = mtd->priv;
2360 if ((ret = nand_block_isbad(mtd, ofs))) {
2361 /* If it was bad already, return success and do nothing. */
2367 return chip->block_markbad(mtd, ofs);
2371 * Set default functions
2373 static void nand_set_defaults(struct nand_chip *chip, int busw)
2375 /* check for proper chip_delay setup, set 20us if not */
2376 if (!chip->chip_delay)
2377 chip->chip_delay = 20;
2379 /* check, if a user supplied command function given */
2380 if (chip->cmdfunc == NULL)
2381 chip->cmdfunc = nand_command;
2383 /* check, if a user supplied wait function given */
2384 if (chip->waitfunc == NULL)
2385 chip->waitfunc = nand_wait;
2387 if (!chip->select_chip)
2388 chip->select_chip = nand_select_chip;
2389 if (!chip->read_byte)
2390 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2391 if (!chip->read_word)
2392 chip->read_word = nand_read_word;
2393 if (!chip->block_bad)
2394 chip->block_bad = nand_block_bad;
2395 if (!chip->block_markbad)
2396 chip->block_markbad = nand_default_block_markbad;
2397 if (!chip->write_buf)
2398 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2399 if (!chip->read_buf)
2400 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2401 if (!chip->verify_buf)
2402 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2403 if (!chip->scan_bbt)
2404 chip->scan_bbt = nand_default_bbt;
2405 if (!chip->controller)
2406 chip->controller = &chip->hwcontrol;
2410 * Get the flash and manufacturer id and lookup if the type is supported
2412 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2413 struct nand_chip *chip,
2414 int busw, int *maf_id)
2416 struct nand_flash_dev *type = NULL;
2417 int i, dev_id, maf_idx;
2418 int tmp_id, tmp_manf;
2420 /* Select the device */
2421 chip->select_chip(mtd, 0);
2424 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2427 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2429 /* Send the command for reading device ID */
2430 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2432 /* Read manufacturer and device IDs */
2433 *maf_id = chip->read_byte(mtd);
2434 dev_id = chip->read_byte(mtd);
2436 /* Try again to make sure, as some systems the bus-hold or other
2437 * interface concerns can cause random data which looks like a
2438 * possibly credible NAND flash to appear. If the two results do
2439 * not match, ignore the device completely.
2442 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2444 /* Read manufacturer and device IDs */
2446 tmp_manf = chip->read_byte(mtd);
2447 tmp_id = chip->read_byte(mtd);
2449 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2450 printk(KERN_INFO "%s: second ID read did not match "
2451 "%02x,%02x against %02x,%02x\n", __func__,
2452 *maf_id, dev_id, tmp_manf, tmp_id);
2453 return ERR_PTR(-ENODEV);
2456 /* Lookup the flash id */
2457 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2458 if (dev_id == nand_flash_ids[i].id) {
2459 type = &nand_flash_ids[i];
2465 /* supress warning if there is no nand */
2466 if (*maf_id != 0x00 && *maf_id != 0xff &&
2467 dev_id != 0x00 && dev_id != 0xff)
2468 printk(KERN_INFO "%s: unknown NAND device: "
2469 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2470 __func__, *maf_id, dev_id);
2471 return ERR_PTR(-ENODEV);
2475 mtd->name = type->name;
2477 chip->chipsize = (uint64_t)type->chipsize << 20;
2479 /* Newer devices have all the information in additional id bytes */
2480 if (!type->pagesize) {
2482 /* The 3rd id byte holds MLC / multichip data */
2483 chip->cellinfo = chip->read_byte(mtd);
2484 /* The 4th id byte is the important one */
2485 extid = chip->read_byte(mtd);
2487 mtd->writesize = 1024 << (extid & 0x3);
2490 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2492 /* Calc blocksize. Blocksize is multiples of 64KiB */
2493 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2495 /* Get buswidth information */
2496 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2500 * Old devices have chip data hardcoded in the device id table
2502 mtd->erasesize = type->erasesize;
2503 mtd->writesize = type->pagesize;
2504 mtd->oobsize = mtd->writesize / 32;
2505 busw = type->options & NAND_BUSWIDTH_16;
2508 /* Try to identify manufacturer */
2509 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2510 if (nand_manuf_ids[maf_idx].id == *maf_id)
2515 * Check, if buswidth is correct. Hardware drivers should set
2518 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2519 printk(KERN_INFO "NAND device: Manufacturer ID:"
2520 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2521 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2522 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2523 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2525 return ERR_PTR(-EINVAL);
2528 /* Calculate the address shift from the page size */
2529 chip->page_shift = ffs(mtd->writesize) - 1;
2530 /* Convert chipsize to number of pages per chip -1. */
2531 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2533 chip->bbt_erase_shift = chip->phys_erase_shift =
2534 ffs(mtd->erasesize) - 1;
2535 if (chip->chipsize & 0xffffffff)
2536 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2538 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2540 /* Set the bad block position */
2541 chip->badblockpos = mtd->writesize > 512 ?
2542 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2544 /* Get chip options, preserve non chip based options */
2545 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2546 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2549 * Set chip as a default. Board drivers can override it, if necessary
2551 chip->options |= NAND_NO_AUTOINCR;
2553 /* Check if chip is a not a samsung device. Do not clear the
2554 * options for chips which are not having an extended id.
2556 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2557 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2559 /* Check for AND chips with 4 page planes */
2560 if (chip->options & NAND_4PAGE_ARRAY)
2561 chip->erase_cmd = multi_erase_cmd;
2563 chip->erase_cmd = single_erase_cmd;
2565 /* Do not replace user supplied command function ! */
2566 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2567 chip->cmdfunc = nand_command_lp;
2569 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2570 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2571 nand_manuf_ids[maf_idx].name, type->name);
2577 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2578 * @mtd: MTD device structure
2579 * @maxchips: Number of chips to scan for
2581 * This is the first phase of the normal nand_scan() function. It
2582 * reads the flash ID and sets up MTD fields accordingly.
2584 * The mtd->owner field must be set to the module of the caller.
2586 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2588 int i, busw, nand_maf_id;
2589 struct nand_chip *chip = mtd->priv;
2590 struct nand_flash_dev *type;
2592 /* Get buswidth to select the correct functions */
2593 busw = chip->options & NAND_BUSWIDTH_16;
2594 /* Set the default functions */
2595 nand_set_defaults(chip, busw);
2597 /* Read the flash type */
2598 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2601 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2602 printk(KERN_WARNING "No NAND device found!!!\n");
2604 chip->select_chip(mtd, -1);
2605 return PTR_ERR(type);
2608 /* Check for a chip array */
2609 for (i = 1; i < maxchips; i++) {
2610 chip->select_chip(mtd, i);
2611 /* See comment in nand_get_flash_type for reset */
2612 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2613 /* Send the command for reading device ID */
2614 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2615 /* Read manufacturer and device IDs */
2616 if (nand_maf_id != chip->read_byte(mtd) ||
2617 type->id != chip->read_byte(mtd))
2622 printk(KERN_INFO "%d NAND chips detected\n", i);
2625 /* Store the number of chips and calc total size for mtd */
2627 mtd->size = i * chip->chipsize;
2634 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2635 * @mtd: MTD device structure
2637 * This is the second phase of the normal nand_scan() function. It
2638 * fills out all the uninitialized function pointers with the defaults
2639 * and scans for a bad block table if appropriate.
2641 int nand_scan_tail(struct mtd_info *mtd)
2644 struct nand_chip *chip = mtd->priv;
2646 if (!(chip->options & NAND_OWN_BUFFERS))
2647 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2651 /* Set the internal oob buffer location, just after the page data */
2652 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2655 * If no default placement scheme is given, select an appropriate one
2657 if (!chip->ecc.layout) {
2658 switch (mtd->oobsize) {
2660 chip->ecc.layout = &nand_oob_8;
2663 chip->ecc.layout = &nand_oob_16;
2666 chip->ecc.layout = &nand_oob_64;
2669 chip->ecc.layout = &nand_oob_128;
2672 printk(KERN_WARNING "No oob scheme defined for "
2673 "oobsize %d\n", mtd->oobsize);
2677 if (!chip->write_page)
2678 chip->write_page = nand_write_page;
2681 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2682 * selected and we have 256 byte pagesize fallback to software ECC
2685 switch (chip->ecc.mode) {
2686 case NAND_ECC_HW_OOB_FIRST:
2687 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2688 if (!chip->ecc.calculate || !chip->ecc.correct ||
2690 printk(KERN_WARNING "No ECC functions supplied, "
2691 "Hardware ECC not possible\n");
2694 if (!chip->ecc.read_page)
2695 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2698 /* Use standard hwecc read page function ? */
2699 if (!chip->ecc.read_page)
2700 chip->ecc.read_page = nand_read_page_hwecc;
2701 if (!chip->ecc.write_page)
2702 chip->ecc.write_page = nand_write_page_hwecc;
2703 if (!chip->ecc.read_page_raw)
2704 chip->ecc.read_page_raw = nand_read_page_raw;
2705 if (!chip->ecc.write_page_raw)
2706 chip->ecc.write_page_raw = nand_write_page_raw;
2707 if (!chip->ecc.read_oob)
2708 chip->ecc.read_oob = nand_read_oob_std;
2709 if (!chip->ecc.write_oob)
2710 chip->ecc.write_oob = nand_write_oob_std;
2712 case NAND_ECC_HW_SYNDROME:
2713 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2714 !chip->ecc.hwctl) &&
2715 (!chip->ecc.read_page ||
2716 chip->ecc.read_page == nand_read_page_hwecc ||
2717 !chip->ecc.write_page ||
2718 chip->ecc.write_page == nand_write_page_hwecc)) {
2719 printk(KERN_WARNING "No ECC functions supplied, "
2720 "Hardware ECC not possible\n");
2723 /* Use standard syndrome read/write page function ? */
2724 if (!chip->ecc.read_page)
2725 chip->ecc.read_page = nand_read_page_syndrome;
2726 if (!chip->ecc.write_page)
2727 chip->ecc.write_page = nand_write_page_syndrome;
2728 if (!chip->ecc.read_page_raw)
2729 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2730 if (!chip->ecc.write_page_raw)
2731 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2732 if (!chip->ecc.read_oob)
2733 chip->ecc.read_oob = nand_read_oob_syndrome;
2734 if (!chip->ecc.write_oob)
2735 chip->ecc.write_oob = nand_write_oob_syndrome;
2737 if (mtd->writesize >= chip->ecc.size)
2739 printk(KERN_WARNING "%d byte HW ECC not possible on "
2740 "%d byte page size, fallback to SW ECC\n",
2741 chip->ecc.size, mtd->writesize);
2742 chip->ecc.mode = NAND_ECC_SOFT;
2745 chip->ecc.calculate = nand_calculate_ecc;
2746 chip->ecc.correct = nand_correct_data;
2747 chip->ecc.read_page = nand_read_page_swecc;
2748 chip->ecc.read_subpage = nand_read_subpage;
2749 chip->ecc.write_page = nand_write_page_swecc;
2750 chip->ecc.read_page_raw = nand_read_page_raw;
2751 chip->ecc.write_page_raw = nand_write_page_raw;
2752 chip->ecc.read_oob = nand_read_oob_std;
2753 chip->ecc.write_oob = nand_write_oob_std;
2754 chip->ecc.size = 256;
2755 chip->ecc.bytes = 3;
2759 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2760 "This is not recommended !!\n");
2761 chip->ecc.read_page = nand_read_page_raw;
2762 chip->ecc.write_page = nand_write_page_raw;
2763 chip->ecc.read_oob = nand_read_oob_std;
2764 chip->ecc.read_page_raw = nand_read_page_raw;
2765 chip->ecc.write_page_raw = nand_write_page_raw;
2766 chip->ecc.write_oob = nand_write_oob_std;
2767 chip->ecc.size = mtd->writesize;
2768 chip->ecc.bytes = 0;
2772 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2778 * The number of bytes available for a client to place data into
2779 * the out of band area
2781 chip->ecc.layout->oobavail = 0;
2782 for (i = 0; chip->ecc.layout->oobfree[i].length
2783 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2784 chip->ecc.layout->oobavail +=
2785 chip->ecc.layout->oobfree[i].length;
2786 mtd->oobavail = chip->ecc.layout->oobavail;
2789 * Set the number of read / write steps for one page depending on ECC
2792 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2793 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2794 printk(KERN_WARNING "Invalid ecc parameters\n");
2797 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2800 * Allow subpage writes up to ecc.steps. Not possible for MLC
2803 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2804 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2805 switch(chip->ecc.steps) {
2807 mtd->subpage_sft = 1;
2812 mtd->subpage_sft = 2;
2816 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2818 /* Initialize state */
2819 chip->state = FL_READY;
2821 /* De-select the device */
2822 chip->select_chip(mtd, -1);
2824 /* Invalidate the pagebuffer reference */
2827 /* Fill in remaining MTD driver data */
2828 mtd->type = MTD_NANDFLASH;
2829 mtd->flags = MTD_CAP_NANDFLASH;
2830 mtd->erase = nand_erase;
2832 mtd->unpoint = NULL;
2833 mtd->read = nand_read;
2834 mtd->write = nand_write;
2835 mtd->read_oob = nand_read_oob;
2836 mtd->write_oob = nand_write_oob;
2837 mtd->sync = nand_sync;
2840 mtd->block_isbad = nand_block_isbad;
2841 mtd->block_markbad = nand_block_markbad;
2843 /* propagate ecc.layout to mtd_info */
2844 mtd->ecclayout = chip->ecc.layout;
2846 /* Check, if we should skip the bad block table scan */
2847 if (chip->options & NAND_SKIP_BBTSCAN)
2848 chip->options |= NAND_BBT_SCANNED;
2854 * nand_scan - [NAND Interface] Scan for the NAND device
2855 * @mtd: MTD device structure
2856 * @maxchips: Number of chips to scan for
2858 * This fills out all the uninitialized function pointers
2859 * with the defaults.
2860 * The flash ID is read and the mtd/chip structures are
2861 * filled with the appropriate values.
2862 * The mtd->owner field must be set to the module of the caller
2865 int nand_scan(struct mtd_info *mtd, int maxchips)
2869 ret = nand_scan_ident(mtd, maxchips);
2871 ret = nand_scan_tail(mtd);
2876 * nand_release - [NAND Interface] Free resources held by the NAND device
2877 * @mtd: MTD device structure
2879 void nand_release(struct mtd_info *mtd)
2881 struct nand_chip *chip = mtd->priv;
2883 #ifdef CONFIG_MTD_PARTITIONS
2884 /* Deregister partitions */
2885 del_mtd_partitions(mtd);
2888 /* Free bad block table memory */
2890 if (!(chip->options & NAND_OWN_BUFFERS))
2891 kfree(chip->buffers);