5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
37 #include <linux/module.h>
38 #include <linux/delay.h>
39 #include <linux/errno.h>
40 #include <linux/err.h>
41 #include <linux/sched.h>
42 #include <linux/slab.h>
43 #include <linux/types.h>
44 #include <linux/mtd/mtd.h>
45 #include <linux/mtd/nand.h>
46 #include <linux/mtd/nand_ecc.h>
47 #include <linux/mtd/compatmac.h>
48 #include <linux/interrupt.h>
49 #include <linux/bitops.h>
50 #include <linux/leds.h>
53 #ifdef CONFIG_MTD_PARTITIONS
54 #include <linux/mtd/partitions.h>
61 #define ENOTSUPP 524 /* Operation is not supported */
65 #include <linux/err.h>
66 #include <linux/mtd/compat.h>
67 #include <linux/mtd/mtd.h>
68 #include <linux/mtd/nand.h>
69 #include <linux/mtd/nand_ecc.h>
71 #ifdef CONFIG_MTD_PARTITIONS
72 #include <linux/mtd/partitions.h>
76 #include <asm/errno.h>
78 #ifdef CONFIG_JFFS2_NAND
79 #include <jffs2/jffs2.h>
83 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
84 * a flash. NAND flash is initialized prior to interrupts so standard timers
85 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
86 * which is greater than (max NAND reset time / NAND status read time).
87 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
89 #ifndef CONFIG_SYS_NAND_RESET_CNT
90 #define CONFIG_SYS_NAND_RESET_CNT 200000
93 /* Define default oob placement schemes for large and small page devices */
94 static struct nand_ecclayout nand_oob_8 = {
104 static struct nand_ecclayout nand_oob_16 = {
106 .eccpos = {0, 1, 2, 3, 6, 7},
112 static struct nand_ecclayout nand_oob_64 = {
115 40, 41, 42, 43, 44, 45, 46, 47,
116 48, 49, 50, 51, 52, 53, 54, 55,
117 56, 57, 58, 59, 60, 61, 62, 63},
123 static struct nand_ecclayout nand_oob_128 = {
126 80, 81, 82, 83, 84, 85, 86, 87,
127 88, 89, 90, 91, 92, 93, 94, 95,
128 96, 97, 98, 99, 100, 101, 102, 103,
129 104, 105, 106, 107, 108, 109, 110, 111,
130 112, 113, 114, 115, 116, 117, 118, 119,
131 120, 121, 122, 123, 124, 125, 126, 127},
138 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
141 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
142 struct mtd_oob_ops *ops);
144 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
147 * For devices which display every fart in the system on a separate LED. Is
148 * compiled away when LED support is disabled.
152 DEFINE_LED_TRIGGER(nand_led_trigger);
156 * nand_release_device - [GENERIC] release chip
157 * @mtd: MTD device structure
159 * Deselect, release chip lock and wake up anyone waiting on the device
163 static void nand_release_device(struct mtd_info *mtd)
165 struct nand_chip *chip = mtd->priv;
167 /* De-select the NAND device */
168 chip->select_chip(mtd, -1);
170 /* Release the controller and the chip */
171 spin_lock(&chip->controller->lock);
172 chip->controller->active = NULL;
173 chip->state = FL_READY;
174 wake_up(&chip->controller->wq);
175 spin_unlock(&chip->controller->lock);
178 static void nand_release_device (struct mtd_info *mtd)
180 struct nand_chip *this = mtd->priv;
181 this->select_chip(mtd, -1); /* De-select the NAND device */
186 * nand_read_byte - [DEFAULT] read one byte from the chip
187 * @mtd: MTD device structure
189 * Default read function for 8bit buswith
191 static uint8_t nand_read_byte(struct mtd_info *mtd)
193 struct nand_chip *chip = mtd->priv;
194 return readb(chip->IO_ADDR_R);
198 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
199 * @mtd: MTD device structure
201 * Default read function for 16bit buswith with
202 * endianess conversion
204 static uint8_t nand_read_byte16(struct mtd_info *mtd)
206 struct nand_chip *chip = mtd->priv;
207 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
211 * nand_read_word - [DEFAULT] read one word from the chip
212 * @mtd: MTD device structure
214 * Default read function for 16bit buswith without
215 * endianess conversion
217 static u16 nand_read_word(struct mtd_info *mtd)
219 struct nand_chip *chip = mtd->priv;
220 return readw(chip->IO_ADDR_R);
224 * nand_select_chip - [DEFAULT] control CE line
225 * @mtd: MTD device structure
226 * @chipnr: chipnumber to select, -1 for deselect
228 * Default select function for 1 chip devices.
230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
232 struct nand_chip *chip = mtd->priv;
236 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
247 * nand_write_buf - [DEFAULT] write buffer to chip
248 * @mtd: MTD device structure
250 * @len: number of bytes to write
252 * Default write function for 8bit buswith
254 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
257 struct nand_chip *chip = mtd->priv;
259 for (i = 0; i < len; i++)
260 writeb(buf[i], chip->IO_ADDR_W);
264 * nand_read_buf - [DEFAULT] read chip data into buffer
265 * @mtd: MTD device structure
266 * @buf: buffer to store date
267 * @len: number of bytes to read
269 * Default read function for 8bit buswith
271 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
274 struct nand_chip *chip = mtd->priv;
276 for (i = 0; i < len; i++)
277 buf[i] = readb(chip->IO_ADDR_R);
281 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
282 * @mtd: MTD device structure
283 * @buf: buffer containing the data to compare
284 * @len: number of bytes to compare
286 * Default verify function for 8bit buswith
288 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
291 struct nand_chip *chip = mtd->priv;
293 for (i = 0; i < len; i++)
294 if (buf[i] != readb(chip->IO_ADDR_R))
300 * nand_write_buf16 - [DEFAULT] write buffer to chip
301 * @mtd: MTD device structure
303 * @len: number of bytes to write
305 * Default write function for 16bit buswith
307 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
310 struct nand_chip *chip = mtd->priv;
311 u16 *p = (u16 *) buf;
314 for (i = 0; i < len; i++)
315 writew(p[i], chip->IO_ADDR_W);
320 * nand_read_buf16 - [DEFAULT] read chip data into buffer
321 * @mtd: MTD device structure
322 * @buf: buffer to store date
323 * @len: number of bytes to read
325 * Default read function for 16bit buswith
327 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
330 struct nand_chip *chip = mtd->priv;
331 u16 *p = (u16 *) buf;
334 for (i = 0; i < len; i++)
335 p[i] = readw(chip->IO_ADDR_R);
339 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
340 * @mtd: MTD device structure
341 * @buf: buffer containing the data to compare
342 * @len: number of bytes to compare
344 * Default verify function for 16bit buswith
346 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
349 struct nand_chip *chip = mtd->priv;
350 u16 *p = (u16 *) buf;
353 for (i = 0; i < len; i++)
354 if (p[i] != readw(chip->IO_ADDR_R))
361 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
362 * @mtd: MTD device structure
363 * @ofs: offset from device start
364 * @getchip: 0, if the chip is already selected
366 * Check, if the block is bad.
368 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
370 int page, chipnr, res = 0;
371 struct nand_chip *chip = mtd->priv;
374 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
377 chipnr = (int)(ofs >> chip->chip_shift);
379 nand_get_device(chip, mtd, FL_READING);
381 /* Select the NAND device */
382 chip->select_chip(mtd, chipnr);
385 if (chip->options & NAND_BUSWIDTH_16) {
386 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
388 bad = cpu_to_le16(chip->read_word(mtd));
389 if (chip->badblockpos & 0x1)
391 if ((bad & 0xFF) != 0xff)
394 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
395 if (chip->read_byte(mtd) != 0xff)
400 nand_release_device(mtd);
406 * nand_default_block_markbad - [DEFAULT] mark a block bad
407 * @mtd: MTD device structure
408 * @ofs: offset from device start
410 * This is the default implementation, which can be overridden by
411 * a hardware specific driver.
413 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
415 struct nand_chip *chip = mtd->priv;
416 uint8_t buf[2] = { 0, 0 };
419 /* Get block number */
420 block = (int)(ofs >> chip->bbt_erase_shift);
422 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
424 /* Do we have a flash based bad block table ? */
425 if (chip->options & NAND_USE_FLASH_BBT)
426 ret = nand_update_bbt(mtd, ofs);
428 /* We write two bytes, so we dont have to mess with 16 bit
431 nand_get_device(chip, mtd, FL_WRITING);
433 chip->ops.len = chip->ops.ooblen = 2;
434 chip->ops.datbuf = NULL;
435 chip->ops.oobbuf = buf;
436 chip->ops.ooboffs = chip->badblockpos & ~0x01;
438 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
439 nand_release_device(mtd);
442 mtd->ecc_stats.badblocks++;
448 * nand_check_wp - [GENERIC] check if the chip is write protected
449 * @mtd: MTD device structure
450 * Check, if the device is write protected
452 * The function expects, that the device is already selected
454 static int nand_check_wp(struct mtd_info *mtd)
456 struct nand_chip *chip = mtd->priv;
457 /* Check the WP bit */
458 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
459 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
463 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
464 * @mtd: MTD device structure
465 * @ofs: offset from device start
466 * @getchip: 0, if the chip is already selected
467 * @allowbbt: 1, if its allowed to access the bbt area
469 * Check, if the block is bad. Either by reading the bad block table or
470 * calling of the scan function.
472 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
475 struct nand_chip *chip = mtd->priv;
477 if (!(chip->options & NAND_BBT_SCANNED)) {
478 chip->options |= NAND_BBT_SCANNED;
483 return chip->block_bad(mtd, ofs, getchip);
485 /* Return info from the table */
486 return nand_isbad_bbt(mtd, ofs, allowbbt);
490 * Wait for the ready pin, after a command
491 * The timeout is catched later.
495 void nand_wait_ready(struct mtd_info *mtd)
497 struct nand_chip *chip = mtd->priv;
498 unsigned long timeo = jiffies + 2;
500 led_trigger_event(nand_led_trigger, LED_FULL);
501 /* wait until command is processed or timeout occures */
503 if (chip->dev_ready(mtd))
505 touch_softlockup_watchdog();
506 } while (time_before(jiffies, timeo));
507 led_trigger_event(nand_led_trigger, LED_OFF);
509 EXPORT_SYMBOL_GPL(nand_wait_ready);
511 void nand_wait_ready(struct mtd_info *mtd)
513 struct nand_chip *chip = mtd->priv;
514 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
518 /* wait until command is processed or timeout occures */
519 while (get_timer(0) < timeo) {
521 if (chip->dev_ready(mtd))
528 * nand_command - [DEFAULT] Send command to NAND device
529 * @mtd: MTD device structure
530 * @command: the command to be sent
531 * @column: the column address for this command, -1 if none
532 * @page_addr: the page address for this command, -1 if none
534 * Send command to NAND device. This function is used for small page
535 * devices (256/512 Bytes per page)
537 static void nand_command(struct mtd_info *mtd, unsigned int command,
538 int column, int page_addr)
540 register struct nand_chip *chip = mtd->priv;
541 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
542 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
545 * Write out the command to the device.
547 if (command == NAND_CMD_SEQIN) {
550 if (column >= mtd->writesize) {
552 column -= mtd->writesize;
553 readcmd = NAND_CMD_READOOB;
554 } else if (column < 256) {
555 /* First 256 bytes --> READ0 */
556 readcmd = NAND_CMD_READ0;
559 readcmd = NAND_CMD_READ1;
561 chip->cmd_ctrl(mtd, readcmd, ctrl);
562 ctrl &= ~NAND_CTRL_CHANGE;
564 chip->cmd_ctrl(mtd, command, ctrl);
567 * Address cycle, when necessary
569 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
570 /* Serially input address */
572 /* Adjust columns for 16 bit buswidth */
573 if (chip->options & NAND_BUSWIDTH_16)
575 chip->cmd_ctrl(mtd, column, ctrl);
576 ctrl &= ~NAND_CTRL_CHANGE;
578 if (page_addr != -1) {
579 chip->cmd_ctrl(mtd, page_addr, ctrl);
580 ctrl &= ~NAND_CTRL_CHANGE;
581 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
582 /* One more address cycle for devices > 32MiB */
583 if (chip->chipsize > (32 << 20))
584 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
586 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
589 * program and erase have their own busy handlers
590 * status and sequential in needs no delay
594 case NAND_CMD_PAGEPROG:
595 case NAND_CMD_ERASE1:
596 case NAND_CMD_ERASE2:
598 case NAND_CMD_STATUS:
604 udelay(chip->chip_delay);
605 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
606 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
608 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
609 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
613 /* This applies to read commands */
616 * If we don't have access to the busy pin, we apply the given
619 if (!chip->dev_ready) {
620 udelay(chip->chip_delay);
624 /* Apply this short delay always to ensure that we do wait tWB in
625 * any case on any machine. */
628 nand_wait_ready(mtd);
632 * nand_command_lp - [DEFAULT] Send command to NAND large page device
633 * @mtd: MTD device structure
634 * @command: the command to be sent
635 * @column: the column address for this command, -1 if none
636 * @page_addr: the page address for this command, -1 if none
638 * Send command to NAND device. This is the version for the new large page
639 * devices We dont have the separate regions as we have in the small page
640 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
642 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
643 int column, int page_addr)
645 register struct nand_chip *chip = mtd->priv;
646 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
648 /* Emulate NAND_CMD_READOOB */
649 if (command == NAND_CMD_READOOB) {
650 column += mtd->writesize;
651 command = NAND_CMD_READ0;
654 /* Command latch cycle */
655 chip->cmd_ctrl(mtd, command & 0xff,
656 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
658 if (column != -1 || page_addr != -1) {
659 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
661 /* Serially input address */
663 /* Adjust columns for 16 bit buswidth */
664 if (chip->options & NAND_BUSWIDTH_16)
666 chip->cmd_ctrl(mtd, column, ctrl);
667 ctrl &= ~NAND_CTRL_CHANGE;
668 chip->cmd_ctrl(mtd, column >> 8, ctrl);
670 if (page_addr != -1) {
671 chip->cmd_ctrl(mtd, page_addr, ctrl);
672 chip->cmd_ctrl(mtd, page_addr >> 8,
673 NAND_NCE | NAND_ALE);
674 /* One more address cycle for devices > 128MiB */
675 if (chip->chipsize > (128 << 20))
676 chip->cmd_ctrl(mtd, page_addr >> 16,
677 NAND_NCE | NAND_ALE);
680 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
683 * program and erase have their own busy handlers
684 * status, sequential in, and deplete1 need no delay
688 case NAND_CMD_CACHEDPROG:
689 case NAND_CMD_PAGEPROG:
690 case NAND_CMD_ERASE1:
691 case NAND_CMD_ERASE2:
694 case NAND_CMD_STATUS:
695 case NAND_CMD_DEPLETE1:
699 * read error status commands require only a short delay
701 case NAND_CMD_STATUS_ERROR:
702 case NAND_CMD_STATUS_ERROR0:
703 case NAND_CMD_STATUS_ERROR1:
704 case NAND_CMD_STATUS_ERROR2:
705 case NAND_CMD_STATUS_ERROR3:
706 udelay(chip->chip_delay);
712 udelay(chip->chip_delay);
713 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
714 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
715 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
716 NAND_NCE | NAND_CTRL_CHANGE);
717 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
721 case NAND_CMD_RNDOUT:
722 /* No ready / busy check necessary */
723 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
724 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
725 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
726 NAND_NCE | NAND_CTRL_CHANGE);
730 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
731 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
732 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
733 NAND_NCE | NAND_CTRL_CHANGE);
735 /* This applies to read commands */
738 * If we don't have access to the busy pin, we apply the given
741 if (!chip->dev_ready) {
742 udelay(chip->chip_delay);
747 /* Apply this short delay always to ensure that we do wait tWB in
748 * any case on any machine. */
751 nand_wait_ready(mtd);
755 * nand_get_device - [GENERIC] Get chip for selected access
756 * @chip: the nand chip descriptor
757 * @mtd: MTD device structure
758 * @new_state: the state which is requested
760 * Get the device and lock it for exclusive access
765 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
767 spinlock_t *lock = &chip->controller->lock;
768 wait_queue_head_t *wq = &chip->controller->wq;
769 DECLARE_WAITQUEUE(wait, current);
773 /* Hardware controller shared among independend devices */
774 /* Hardware controller shared among independend devices */
775 if (!chip->controller->active)
776 chip->controller->active = chip;
778 if (chip->controller->active == chip && chip->state == FL_READY) {
779 chip->state = new_state;
783 if (new_state == FL_PM_SUSPENDED) {
785 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
787 set_current_state(TASK_UNINTERRUPTIBLE);
788 add_wait_queue(wq, &wait);
791 remove_wait_queue(wq, &wait);
795 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
797 this->state = new_state;
803 * nand_wait - [DEFAULT] wait until the command is done
804 * @mtd: MTD device structure
805 * @chip: NAND chip structure
807 * Wait for command done. This applies to erase and program only
808 * Erase can take up to 400ms and program up to 20ms according to
809 * general NAND and SmartMedia specs
813 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
816 unsigned long timeo = jiffies;
817 int status, state = chip->state;
819 if (state == FL_ERASING)
820 timeo += (HZ * 400) / 1000;
822 timeo += (HZ * 20) / 1000;
824 led_trigger_event(nand_led_trigger, LED_FULL);
826 /* Apply this short delay always to ensure that we do wait tWB in
827 * any case on any machine. */
830 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
831 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
833 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
835 while (time_before(jiffies, timeo)) {
836 if (chip->dev_ready) {
837 if (chip->dev_ready(mtd))
840 if (chip->read_byte(mtd) & NAND_STATUS_READY)
845 led_trigger_event(nand_led_trigger, LED_OFF);
847 status = (int)chip->read_byte(mtd);
851 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
854 int state = this->state;
856 if (state == FL_ERASING)
857 timeo = (CONFIG_SYS_HZ * 400) / 1000;
859 timeo = (CONFIG_SYS_HZ * 20) / 1000;
861 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
862 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
864 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
869 if (get_timer(0) > timeo) {
874 if (this->dev_ready) {
875 if (this->dev_ready(mtd))
878 if (this->read_byte(mtd) & NAND_STATUS_READY)
882 #ifdef PPCHAMELON_NAND_TIMER_HACK
884 while (get_timer(0) < 10);
885 #endif /* PPCHAMELON_NAND_TIMER_HACK */
887 return this->read_byte(mtd);
892 * nand_read_page_raw - [Intern] read raw page data without ecc
893 * @mtd: mtd info structure
894 * @chip: nand chip info structure
895 * @buf: buffer to store read data
897 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
898 uint8_t *buf, int page)
900 chip->read_buf(mtd, buf, mtd->writesize);
901 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
906 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
907 * @mtd: mtd info structure
908 * @chip: nand chip info structure
909 * @buf: buffer to store read data
911 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
912 uint8_t *buf, int page)
914 int i, eccsize = chip->ecc.size;
915 int eccbytes = chip->ecc.bytes;
916 int eccsteps = chip->ecc.steps;
918 uint8_t *ecc_calc = chip->buffers->ecccalc;
919 uint8_t *ecc_code = chip->buffers->ecccode;
920 uint32_t *eccpos = chip->ecc.layout->eccpos;
922 chip->ecc.read_page_raw(mtd, chip, buf, page);
924 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
925 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
927 for (i = 0; i < chip->ecc.total; i++)
928 ecc_code[i] = chip->oob_poi[eccpos[i]];
930 eccsteps = chip->ecc.steps;
933 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
936 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
938 mtd->ecc_stats.failed++;
940 mtd->ecc_stats.corrected += stat;
946 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
947 * @mtd: mtd info structure
948 * @chip: nand chip info structure
949 * @dataofs offset of requested data within the page
950 * @readlen data length
951 * @buf: buffer to store read data
953 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
955 int start_step, end_step, num_steps;
956 uint32_t *eccpos = chip->ecc.layout->eccpos;
958 int data_col_addr, i, gaps = 0;
959 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
960 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
962 /* Column address wihin the page aligned to ECC size (256bytes). */
963 start_step = data_offs / chip->ecc.size;
964 end_step = (data_offs + readlen - 1) / chip->ecc.size;
965 num_steps = end_step - start_step + 1;
967 /* Data size aligned to ECC ecc.size*/
968 datafrag_len = num_steps * chip->ecc.size;
969 eccfrag_len = num_steps * chip->ecc.bytes;
971 data_col_addr = start_step * chip->ecc.size;
972 /* If we read not a page aligned data */
973 if (data_col_addr != 0)
974 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
976 p = bufpoi + data_col_addr;
977 chip->read_buf(mtd, p, datafrag_len);
980 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
981 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
983 /* The performance is faster if to position offsets
984 according to ecc.pos. Let make sure here that
985 there are no gaps in ecc positions */
986 for (i = 0; i < eccfrag_len - 1; i++) {
987 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
988 eccpos[i + start_step * chip->ecc.bytes + 1]) {
994 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
995 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
997 /* send the command to read the particular ecc bytes */
998 /* take care about buswidth alignment in read_buf */
999 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1000 aligned_len = eccfrag_len;
1001 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1003 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1006 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1007 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1010 for (i = 0; i < eccfrag_len; i++)
1011 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1013 p = bufpoi + data_col_addr;
1014 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1017 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1019 mtd->ecc_stats.failed++;
1021 mtd->ecc_stats.corrected += stat;
1027 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1028 * @mtd: mtd info structure
1029 * @chip: nand chip info structure
1030 * @buf: buffer to store read data
1032 * Not for syndrome calculating ecc controllers which need a special oob layout
1034 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1035 uint8_t *buf, int page)
1037 int i, eccsize = chip->ecc.size;
1038 int eccbytes = chip->ecc.bytes;
1039 int eccsteps = chip->ecc.steps;
1041 uint8_t *ecc_calc = chip->buffers->ecccalc;
1042 uint8_t *ecc_code = chip->buffers->ecccode;
1043 uint32_t *eccpos = chip->ecc.layout->eccpos;
1045 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1046 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1047 chip->read_buf(mtd, p, eccsize);
1048 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1050 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1052 for (i = 0; i < chip->ecc.total; i++)
1053 ecc_code[i] = chip->oob_poi[eccpos[i]];
1055 eccsteps = chip->ecc.steps;
1058 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1061 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1063 mtd->ecc_stats.failed++;
1065 mtd->ecc_stats.corrected += stat;
1071 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1072 * @mtd: mtd info structure
1073 * @chip: nand chip info structure
1074 * @buf: buffer to store read data
1076 * Hardware ECC for large page chips, require OOB to be read first.
1077 * For this ECC mode, the write_page method is re-used from ECC_HW.
1078 * These methods read/write ECC from the OOB area, unlike the
1079 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1080 * "infix ECC" scheme and reads/writes ECC from the data area, by
1081 * overwriting the NAND manufacturer bad block markings.
1083 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1084 struct nand_chip *chip, uint8_t *buf, int page)
1086 int i, eccsize = chip->ecc.size;
1087 int eccbytes = chip->ecc.bytes;
1088 int eccsteps = chip->ecc.steps;
1090 uint8_t *ecc_code = chip->buffers->ecccode;
1091 uint32_t *eccpos = chip->ecc.layout->eccpos;
1092 uint8_t *ecc_calc = chip->buffers->ecccalc;
1094 /* Read the OOB area first */
1095 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1096 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1097 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1099 for (i = 0; i < chip->ecc.total; i++)
1100 ecc_code[i] = chip->oob_poi[eccpos[i]];
1102 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1105 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1106 chip->read_buf(mtd, p, eccsize);
1107 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1109 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1111 mtd->ecc_stats.failed++;
1113 mtd->ecc_stats.corrected += stat;
1119 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1120 * @mtd: mtd info structure
1121 * @chip: nand chip info structure
1122 * @buf: buffer to store read data
1124 * The hw generator calculates the error syndrome automatically. Therefor
1125 * we need a special oob layout and handling.
1127 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1128 uint8_t *buf, int page)
1130 int i, eccsize = chip->ecc.size;
1131 int eccbytes = chip->ecc.bytes;
1132 int eccsteps = chip->ecc.steps;
1134 uint8_t *oob = chip->oob_poi;
1136 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1139 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1140 chip->read_buf(mtd, p, eccsize);
1142 if (chip->ecc.prepad) {
1143 chip->read_buf(mtd, oob, chip->ecc.prepad);
1144 oob += chip->ecc.prepad;
1147 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1148 chip->read_buf(mtd, oob, eccbytes);
1149 stat = chip->ecc.correct(mtd, p, oob, NULL);
1152 mtd->ecc_stats.failed++;
1154 mtd->ecc_stats.corrected += stat;
1158 if (chip->ecc.postpad) {
1159 chip->read_buf(mtd, oob, chip->ecc.postpad);
1160 oob += chip->ecc.postpad;
1164 /* Calculate remaining oob bytes */
1165 i = mtd->oobsize - (oob - chip->oob_poi);
1167 chip->read_buf(mtd, oob, i);
1173 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1174 * @chip: nand chip structure
1175 * @oob: oob destination address
1176 * @ops: oob ops structure
1177 * @len: size of oob to transfer
1179 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1180 struct mtd_oob_ops *ops, size_t len)
1186 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1189 case MTD_OOB_AUTO: {
1190 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1191 uint32_t boffs = 0, roffs = ops->ooboffs;
1194 for(; free->length && len; free++, len -= bytes) {
1195 /* Read request not from offset 0 ? */
1196 if (unlikely(roffs)) {
1197 if (roffs >= free->length) {
1198 roffs -= free->length;
1201 boffs = free->offset + roffs;
1202 bytes = min_t(size_t, len,
1203 (free->length - roffs));
1206 bytes = min_t(size_t, len, free->length);
1207 boffs = free->offset;
1209 memcpy(oob, chip->oob_poi + boffs, bytes);
1221 * nand_do_read_ops - [Internal] Read data with ECC
1223 * @mtd: MTD device structure
1224 * @from: offset to read from
1225 * @ops: oob ops structure
1227 * Internal function. Called with chip held.
1229 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1230 struct mtd_oob_ops *ops)
1232 int chipnr, page, realpage, col, bytes, aligned;
1233 struct nand_chip *chip = mtd->priv;
1234 struct mtd_ecc_stats stats;
1235 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1238 uint32_t readlen = ops->len;
1239 uint32_t oobreadlen = ops->ooblen;
1240 uint8_t *bufpoi, *oob, *buf;
1242 stats = mtd->ecc_stats;
1244 chipnr = (int)(from >> chip->chip_shift);
1245 chip->select_chip(mtd, chipnr);
1247 realpage = (int)(from >> chip->page_shift);
1248 page = realpage & chip->pagemask;
1250 col = (int)(from & (mtd->writesize - 1));
1256 bytes = min(mtd->writesize - col, readlen);
1257 aligned = (bytes == mtd->writesize);
1259 /* Is the current page in the buffer ? */
1260 if (realpage != chip->pagebuf || oob) {
1261 bufpoi = aligned ? buf : chip->buffers->databuf;
1263 if (likely(sndcmd)) {
1264 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1268 /* Now read the page into the buffer */
1269 if (unlikely(ops->mode == MTD_OOB_RAW))
1270 ret = chip->ecc.read_page_raw(mtd, chip,
1272 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1273 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1275 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1280 /* Transfer not aligned data */
1282 if (!NAND_SUBPAGE_READ(chip) && !oob)
1283 chip->pagebuf = realpage;
1284 memcpy(buf, chip->buffers->databuf + col, bytes);
1289 if (unlikely(oob)) {
1290 /* Raw mode does data:oob:data:oob */
1291 if (ops->mode != MTD_OOB_RAW) {
1292 int toread = min(oobreadlen,
1293 chip->ecc.layout->oobavail);
1295 oob = nand_transfer_oob(chip,
1297 oobreadlen -= toread;
1300 buf = nand_transfer_oob(chip,
1301 buf, ops, mtd->oobsize);
1304 if (!(chip->options & NAND_NO_READRDY)) {
1306 * Apply delay or wait for ready/busy pin. Do
1307 * this before the AUTOINCR check, so no
1308 * problems arise if a chip which does auto
1309 * increment is marked as NOAUTOINCR by the
1312 if (!chip->dev_ready)
1313 udelay(chip->chip_delay);
1315 nand_wait_ready(mtd);
1318 memcpy(buf, chip->buffers->databuf + col, bytes);
1327 /* For subsequent reads align to page boundary. */
1329 /* Increment page address */
1332 page = realpage & chip->pagemask;
1333 /* Check, if we cross a chip boundary */
1336 chip->select_chip(mtd, -1);
1337 chip->select_chip(mtd, chipnr);
1340 /* Check, if the chip supports auto page increment
1341 * or if we have hit a block boundary.
1343 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1347 ops->retlen = ops->len - (size_t) readlen;
1349 ops->oobretlen = ops->ooblen - oobreadlen;
1354 if (mtd->ecc_stats.failed - stats.failed)
1357 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1361 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1362 * @mtd: MTD device structure
1363 * @from: offset to read from
1364 * @len: number of bytes to read
1365 * @retlen: pointer to variable to store the number of read bytes
1366 * @buf: the databuffer to put data
1368 * Get hold of the chip and call nand_do_read
1370 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1371 size_t *retlen, uint8_t *buf)
1373 struct nand_chip *chip = mtd->priv;
1376 /* Do not allow reads past end of device */
1377 if ((from + len) > mtd->size)
1382 nand_get_device(chip, mtd, FL_READING);
1384 chip->ops.len = len;
1385 chip->ops.datbuf = buf;
1386 chip->ops.oobbuf = NULL;
1388 ret = nand_do_read_ops(mtd, from, &chip->ops);
1390 *retlen = chip->ops.retlen;
1392 nand_release_device(mtd);
1398 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1399 * @mtd: mtd info structure
1400 * @chip: nand chip info structure
1401 * @page: page number to read
1402 * @sndcmd: flag whether to issue read command or not
1404 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1405 int page, int sndcmd)
1408 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1411 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1416 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1418 * @mtd: mtd info structure
1419 * @chip: nand chip info structure
1420 * @page: page number to read
1421 * @sndcmd: flag whether to issue read command or not
1423 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1424 int page, int sndcmd)
1426 uint8_t *buf = chip->oob_poi;
1427 int length = mtd->oobsize;
1428 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1429 int eccsize = chip->ecc.size;
1430 uint8_t *bufpoi = buf;
1431 int i, toread, sndrnd = 0, pos;
1433 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1434 for (i = 0; i < chip->ecc.steps; i++) {
1436 pos = eccsize + i * (eccsize + chunk);
1437 if (mtd->writesize > 512)
1438 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1440 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1443 toread = min_t(int, length, chunk);
1444 chip->read_buf(mtd, bufpoi, toread);
1449 chip->read_buf(mtd, bufpoi, length);
1455 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1456 * @mtd: mtd info structure
1457 * @chip: nand chip info structure
1458 * @page: page number to write
1460 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1464 const uint8_t *buf = chip->oob_poi;
1465 int length = mtd->oobsize;
1467 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1468 chip->write_buf(mtd, buf, length);
1469 /* Send command to program the OOB data */
1470 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1472 status = chip->waitfunc(mtd, chip);
1474 return status & NAND_STATUS_FAIL ? -EIO : 0;
1478 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1479 * with syndrome - only for large page flash !
1480 * @mtd: mtd info structure
1481 * @chip: nand chip info structure
1482 * @page: page number to write
1484 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1485 struct nand_chip *chip, int page)
1487 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1488 int eccsize = chip->ecc.size, length = mtd->oobsize;
1489 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1490 const uint8_t *bufpoi = chip->oob_poi;
1493 * data-ecc-data-ecc ... ecc-oob
1495 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1497 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1498 pos = steps * (eccsize + chunk);
1503 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1504 for (i = 0; i < steps; i++) {
1506 if (mtd->writesize <= 512) {
1507 uint32_t fill = 0xFFFFFFFF;
1511 int num = min_t(int, len, 4);
1512 chip->write_buf(mtd, (uint8_t *)&fill,
1517 pos = eccsize + i * (eccsize + chunk);
1518 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1522 len = min_t(int, length, chunk);
1523 chip->write_buf(mtd, bufpoi, len);
1528 chip->write_buf(mtd, bufpoi, length);
1530 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1531 status = chip->waitfunc(mtd, chip);
1533 return status & NAND_STATUS_FAIL ? -EIO : 0;
1537 * nand_do_read_oob - [Intern] NAND read out-of-band
1538 * @mtd: MTD device structure
1539 * @from: offset to read from
1540 * @ops: oob operations description structure
1542 * NAND read out-of-band data from the spare area
1544 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1545 struct mtd_oob_ops *ops)
1547 int page, realpage, chipnr, sndcmd = 1;
1548 struct nand_chip *chip = mtd->priv;
1549 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1550 int readlen = ops->ooblen;
1552 uint8_t *buf = ops->oobbuf;
1554 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1555 (unsigned long long)from, readlen);
1557 if (ops->mode == MTD_OOB_AUTO)
1558 len = chip->ecc.layout->oobavail;
1562 if (unlikely(ops->ooboffs >= len)) {
1563 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1564 "Attempt to start read outside oob\n");
1568 /* Do not allow reads past end of device */
1569 if (unlikely(from >= mtd->size ||
1570 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1571 (from >> chip->page_shift)) * len)) {
1572 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1573 "Attempt read beyond end of device\n");
1577 chipnr = (int)(from >> chip->chip_shift);
1578 chip->select_chip(mtd, chipnr);
1580 /* Shift to get page */
1581 realpage = (int)(from >> chip->page_shift);
1582 page = realpage & chip->pagemask;
1585 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1587 len = min(len, readlen);
1588 buf = nand_transfer_oob(chip, buf, ops, len);
1590 if (!(chip->options & NAND_NO_READRDY)) {
1592 * Apply delay or wait for ready/busy pin. Do this
1593 * before the AUTOINCR check, so no problems arise if a
1594 * chip which does auto increment is marked as
1595 * NOAUTOINCR by the board driver.
1597 if (!chip->dev_ready)
1598 udelay(chip->chip_delay);
1600 nand_wait_ready(mtd);
1607 /* Increment page address */
1610 page = realpage & chip->pagemask;
1611 /* Check, if we cross a chip boundary */
1614 chip->select_chip(mtd, -1);
1615 chip->select_chip(mtd, chipnr);
1618 /* Check, if the chip supports auto page increment
1619 * or if we have hit a block boundary.
1621 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1625 ops->oobretlen = ops->ooblen;
1630 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1631 * @mtd: MTD device structure
1632 * @from: offset to read from
1633 * @ops: oob operation description structure
1635 * NAND read data and/or out-of-band data
1637 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1638 struct mtd_oob_ops *ops)
1640 struct nand_chip *chip = mtd->priv;
1641 int ret = -ENOTSUPP;
1645 /* Do not allow reads past end of device */
1646 if (ops->datbuf && (from + ops->len) > mtd->size) {
1647 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1648 "Attempt read beyond end of device\n");
1652 nand_get_device(chip, mtd, FL_READING);
1665 ret = nand_do_read_oob(mtd, from, ops);
1667 ret = nand_do_read_ops(mtd, from, ops);
1670 nand_release_device(mtd);
1676 * nand_write_page_raw - [Intern] raw page write function
1677 * @mtd: mtd info structure
1678 * @chip: nand chip info structure
1681 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1684 chip->write_buf(mtd, buf, mtd->writesize);
1685 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1689 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1690 * @mtd: mtd info structure
1691 * @chip: nand chip info structure
1694 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1697 int i, eccsize = chip->ecc.size;
1698 int eccbytes = chip->ecc.bytes;
1699 int eccsteps = chip->ecc.steps;
1700 uint8_t *ecc_calc = chip->buffers->ecccalc;
1701 const uint8_t *p = buf;
1702 uint32_t *eccpos = chip->ecc.layout->eccpos;
1704 /* Software ecc calculation */
1705 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1706 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1708 for (i = 0; i < chip->ecc.total; i++)
1709 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1711 chip->ecc.write_page_raw(mtd, chip, buf);
1715 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1716 * @mtd: mtd info structure
1717 * @chip: nand chip info structure
1720 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1723 int i, eccsize = chip->ecc.size;
1724 int eccbytes = chip->ecc.bytes;
1725 int eccsteps = chip->ecc.steps;
1726 uint8_t *ecc_calc = chip->buffers->ecccalc;
1727 const uint8_t *p = buf;
1728 uint32_t *eccpos = chip->ecc.layout->eccpos;
1730 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1731 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1732 chip->write_buf(mtd, p, eccsize);
1733 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1736 for (i = 0; i < chip->ecc.total; i++)
1737 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1739 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1743 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1744 * @mtd: mtd info structure
1745 * @chip: nand chip info structure
1748 * The hw generator calculates the error syndrome automatically. Therefor
1749 * we need a special oob layout and handling.
1751 static void nand_write_page_syndrome(struct mtd_info *mtd,
1752 struct nand_chip *chip, const uint8_t *buf)
1754 int i, eccsize = chip->ecc.size;
1755 int eccbytes = chip->ecc.bytes;
1756 int eccsteps = chip->ecc.steps;
1757 const uint8_t *p = buf;
1758 uint8_t *oob = chip->oob_poi;
1760 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1762 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1763 chip->write_buf(mtd, p, eccsize);
1765 if (chip->ecc.prepad) {
1766 chip->write_buf(mtd, oob, chip->ecc.prepad);
1767 oob += chip->ecc.prepad;
1770 chip->ecc.calculate(mtd, p, oob);
1771 chip->write_buf(mtd, oob, eccbytes);
1774 if (chip->ecc.postpad) {
1775 chip->write_buf(mtd, oob, chip->ecc.postpad);
1776 oob += chip->ecc.postpad;
1780 /* Calculate remaining oob bytes */
1781 i = mtd->oobsize - (oob - chip->oob_poi);
1783 chip->write_buf(mtd, oob, i);
1787 * nand_write_page - [REPLACEABLE] write one page
1788 * @mtd: MTD device structure
1789 * @chip: NAND chip descriptor
1790 * @buf: the data to write
1791 * @page: page number to write
1792 * @cached: cached programming
1793 * @raw: use _raw version of write_page
1795 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1796 const uint8_t *buf, int page, int cached, int raw)
1800 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1803 chip->ecc.write_page_raw(mtd, chip, buf);
1805 chip->ecc.write_page(mtd, chip, buf);
1808 * Cached progamming disabled for now, Not sure if its worth the
1809 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1813 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1815 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1816 status = chip->waitfunc(mtd, chip);
1818 * See if operation failed and additional status checks are
1821 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1822 status = chip->errstat(mtd, chip, FL_WRITING, status,
1825 if (status & NAND_STATUS_FAIL)
1828 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1829 status = chip->waitfunc(mtd, chip);
1832 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1833 /* Send command to read back the data */
1834 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1836 if (chip->verify_buf(mtd, buf, mtd->writesize))
1843 * nand_fill_oob - [Internal] Transfer client buffer to oob
1844 * @chip: nand chip structure
1845 * @oob: oob data buffer
1846 * @ops: oob ops structure
1848 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1849 struct mtd_oob_ops *ops)
1851 size_t len = ops->ooblen;
1857 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1860 case MTD_OOB_AUTO: {
1861 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1862 uint32_t boffs = 0, woffs = ops->ooboffs;
1865 for(; free->length && len; free++, len -= bytes) {
1866 /* Write request not from offset 0 ? */
1867 if (unlikely(woffs)) {
1868 if (woffs >= free->length) {
1869 woffs -= free->length;
1872 boffs = free->offset + woffs;
1873 bytes = min_t(size_t, len,
1874 (free->length - woffs));
1877 bytes = min_t(size_t, len, free->length);
1878 boffs = free->offset;
1880 memcpy(chip->oob_poi + boffs, oob, bytes);
1891 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1894 * nand_do_write_ops - [Internal] NAND write with ECC
1895 * @mtd: MTD device structure
1896 * @to: offset to write to
1897 * @ops: oob operations description structure
1899 * NAND write with ECC
1901 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1902 struct mtd_oob_ops *ops)
1904 int chipnr, realpage, page, blockmask, column;
1905 struct nand_chip *chip = mtd->priv;
1906 uint32_t writelen = ops->len;
1907 uint8_t *oob = ops->oobbuf;
1908 uint8_t *buf = ops->datbuf;
1915 /* reject writes, which are not page aligned */
1916 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1917 printk(KERN_NOTICE "nand_write: "
1918 "Attempt to write not page aligned data\n");
1922 column = to & (mtd->writesize - 1);
1923 subpage = column || (writelen & (mtd->writesize - 1));
1928 chipnr = (int)(to >> chip->chip_shift);
1929 chip->select_chip(mtd, chipnr);
1931 /* Check, if it is write protected */
1932 if (nand_check_wp(mtd)) {
1933 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1937 realpage = (int)(to >> chip->page_shift);
1938 page = realpage & chip->pagemask;
1939 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1941 /* Invalidate the page cache, when we write to the cached page */
1942 if (to <= (chip->pagebuf << chip->page_shift) &&
1943 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1946 /* If we're not given explicit OOB data, let it be 0xFF */
1948 memset(chip->oob_poi, 0xff, mtd->oobsize);
1951 int bytes = mtd->writesize;
1952 int cached = writelen > bytes && page != blockmask;
1953 uint8_t *wbuf = buf;
1955 /* Partial page write ? */
1956 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1958 bytes = min_t(int, bytes - column, (int) writelen);
1960 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1961 memcpy(&chip->buffers->databuf[column], buf, bytes);
1962 wbuf = chip->buffers->databuf;
1966 oob = nand_fill_oob(chip, oob, ops);
1968 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1969 (ops->mode == MTD_OOB_RAW));
1981 page = realpage & chip->pagemask;
1982 /* Check, if we cross a chip boundary */
1985 chip->select_chip(mtd, -1);
1986 chip->select_chip(mtd, chipnr);
1990 ops->retlen = ops->len - writelen;
1992 ops->oobretlen = ops->ooblen;
1997 * nand_write - [MTD Interface] NAND write with ECC
1998 * @mtd: MTD device structure
1999 * @to: offset to write to
2000 * @len: number of bytes to write
2001 * @retlen: pointer to variable to store the number of written bytes
2002 * @buf: the data to write
2004 * NAND write with ECC
2006 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2007 size_t *retlen, const uint8_t *buf)
2009 struct nand_chip *chip = mtd->priv;
2012 /* Do not allow reads past end of device */
2013 if ((to + len) > mtd->size)
2018 nand_get_device(chip, mtd, FL_WRITING);
2020 chip->ops.len = len;
2021 chip->ops.datbuf = (uint8_t *)buf;
2022 chip->ops.oobbuf = NULL;
2024 ret = nand_do_write_ops(mtd, to, &chip->ops);
2026 *retlen = chip->ops.retlen;
2028 nand_release_device(mtd);
2034 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2035 * @mtd: MTD device structure
2036 * @to: offset to write to
2037 * @ops: oob operation description structure
2039 * NAND write out-of-band
2041 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2042 struct mtd_oob_ops *ops)
2044 int chipnr, page, status, len;
2045 struct nand_chip *chip = mtd->priv;
2047 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
2048 (unsigned int)to, (int)ops->ooblen);
2050 if (ops->mode == MTD_OOB_AUTO)
2051 len = chip->ecc.layout->oobavail;
2055 /* Do not allow write past end of page */
2056 if ((ops->ooboffs + ops->ooblen) > len) {
2057 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2058 "Attempt to write past end of page\n");
2062 if (unlikely(ops->ooboffs >= len)) {
2063 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2064 "Attempt to start write outside oob\n");
2068 /* Do not allow reads past end of device */
2069 if (unlikely(to >= mtd->size ||
2070 ops->ooboffs + ops->ooblen >
2071 ((mtd->size >> chip->page_shift) -
2072 (to >> chip->page_shift)) * len)) {
2073 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2074 "Attempt write beyond end of device\n");
2078 chipnr = (int)(to >> chip->chip_shift);
2079 chip->select_chip(mtd, chipnr);
2081 /* Shift to get page */
2082 page = (int)(to >> chip->page_shift);
2085 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2086 * of my DiskOnChip 2000 test units) will clear the whole data page too
2087 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2088 * it in the doc2000 driver in August 1999. dwmw2.
2090 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2092 /* Check, if it is write protected */
2093 if (nand_check_wp(mtd))
2096 /* Invalidate the page cache, if we write to the cached page */
2097 if (page == chip->pagebuf)
2100 memset(chip->oob_poi, 0xff, mtd->oobsize);
2101 nand_fill_oob(chip, ops->oobbuf, ops);
2102 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2103 memset(chip->oob_poi, 0xff, mtd->oobsize);
2108 ops->oobretlen = ops->ooblen;
2114 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2115 * @mtd: MTD device structure
2116 * @to: offset to write to
2117 * @ops: oob operation description structure
2119 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2120 struct mtd_oob_ops *ops)
2122 struct nand_chip *chip = mtd->priv;
2123 int ret = -ENOTSUPP;
2127 /* Do not allow writes past end of device */
2128 if (ops->datbuf && (to + ops->len) > mtd->size) {
2129 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2130 "Attempt read beyond end of device\n");
2134 nand_get_device(chip, mtd, FL_WRITING);
2147 ret = nand_do_write_oob(mtd, to, ops);
2149 ret = nand_do_write_ops(mtd, to, ops);
2152 nand_release_device(mtd);
2157 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2158 * @mtd: MTD device structure
2159 * @page: the page address of the block which will be erased
2161 * Standard erase command for NAND chips
2163 static void single_erase_cmd(struct mtd_info *mtd, int page)
2165 struct nand_chip *chip = mtd->priv;
2166 /* Send commands to erase a block */
2167 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2168 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2172 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2173 * @mtd: MTD device structure
2174 * @page: the page address of the block which will be erased
2176 * AND multi block erase command function
2177 * Erase 4 consecutive blocks
2179 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2181 struct nand_chip *chip = mtd->priv;
2182 /* Send commands to erase a block */
2183 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2184 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2185 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2186 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2187 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2191 * nand_erase - [MTD Interface] erase block(s)
2192 * @mtd: MTD device structure
2193 * @instr: erase instruction
2195 * Erase one ore more blocks
2197 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2199 return nand_erase_nand(mtd, instr, 0);
2202 #define BBT_PAGE_MASK 0xffffff3f
2204 * nand_erase_nand - [Internal] erase block(s)
2205 * @mtd: MTD device structure
2206 * @instr: erase instruction
2207 * @allowbbt: allow erasing the bbt area
2209 * Erase one ore more blocks
2211 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2214 int page, len, status, pages_per_block, ret, chipnr;
2215 struct nand_chip *chip = mtd->priv;
2216 int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0};
2217 unsigned int bbt_masked_page = 0xffffffff;
2219 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2220 (unsigned int) instr->addr, (unsigned int) instr->len);
2222 /* Start address must align on block boundary */
2223 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2224 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2228 /* Length must align on block boundary */
2229 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2230 MTDDEBUG (MTD_DEBUG_LEVEL0,
2231 "nand_erase: Length not block aligned\n");
2235 /* Do not allow erase past end of device */
2236 if ((instr->len + instr->addr) > mtd->size) {
2237 MTDDEBUG (MTD_DEBUG_LEVEL0,
2238 "nand_erase: Erase past end of device\n");
2242 instr->fail_addr = 0xffffffff;
2244 /* Grab the lock and see if the device is available */
2245 nand_get_device(chip, mtd, FL_ERASING);
2247 /* Shift to get first page */
2248 page = (int)(instr->addr >> chip->page_shift);
2249 chipnr = (int)(instr->addr >> chip->chip_shift);
2251 /* Calculate pages in each block */
2252 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2254 /* Select the NAND device */
2255 chip->select_chip(mtd, chipnr);
2257 /* Check, if it is write protected */
2258 if (nand_check_wp(mtd)) {
2259 MTDDEBUG (MTD_DEBUG_LEVEL0,
2260 "nand_erase: Device is write protected!!!\n");
2261 instr->state = MTD_ERASE_FAILED;
2266 * If BBT requires refresh, set the BBT page mask to see if the BBT
2267 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2268 * can not be matched. This is also done when the bbt is actually
2269 * erased to avoid recusrsive updates
2271 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2272 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2274 /* Loop through the pages */
2277 instr->state = MTD_ERASING;
2281 * heck if we have a bad block, we do not erase bad blocks !
2283 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2284 chip->page_shift, 0, allowbbt)) {
2285 printk(KERN_WARNING "nand_erase: attempt to erase a "
2286 "bad block at page 0x%08x\n", page);
2287 instr->state = MTD_ERASE_FAILED;
2292 * Invalidate the page cache, if we erase the block which
2293 * contains the current cached page
2295 if (page <= chip->pagebuf && chip->pagebuf <
2296 (page + pages_per_block))
2299 chip->erase_cmd(mtd, page & chip->pagemask);
2301 status = chip->waitfunc(mtd, chip);
2304 * See if operation failed and additional status checks are
2307 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2308 status = chip->errstat(mtd, chip, FL_ERASING,
2311 /* See if block erase succeeded */
2312 if (status & NAND_STATUS_FAIL) {
2313 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2314 "Failed erase, page 0x%08x\n", page);
2315 instr->state = MTD_ERASE_FAILED;
2316 instr->fail_addr = (page << chip->page_shift);
2321 * If BBT requires refresh, set the BBT rewrite flag to the
2324 if (bbt_masked_page != 0xffffffff &&
2325 (page & BBT_PAGE_MASK) == bbt_masked_page)
2326 rewrite_bbt[chipnr] = (page << chip->page_shift);
2328 /* Increment page address and decrement length */
2329 len -= (1 << chip->phys_erase_shift);
2330 page += pages_per_block;
2332 /* Check, if we cross a chip boundary */
2333 if (len && !(page & chip->pagemask)) {
2335 chip->select_chip(mtd, -1);
2336 chip->select_chip(mtd, chipnr);
2339 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2340 * page mask to see if this BBT should be rewritten
2342 if (bbt_masked_page != 0xffffffff &&
2343 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2344 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2348 instr->state = MTD_ERASE_DONE;
2352 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2354 /* Deselect and wake up anyone waiting on the device */
2355 nand_release_device(mtd);
2357 /* Do call back function */
2359 mtd_erase_callback(instr);
2362 * If BBT requires refresh and erase was successful, rewrite any
2363 * selected bad block tables
2365 if (bbt_masked_page == 0xffffffff || ret)
2368 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2369 if (!rewrite_bbt[chipnr])
2371 /* update the BBT for chip */
2372 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2373 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2374 chip->bbt_td->pages[chipnr]);
2375 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2378 /* Return more or less happy */
2383 * nand_sync - [MTD Interface] sync
2384 * @mtd: MTD device structure
2386 * Sync is actually a wait for chip ready function
2388 static void nand_sync(struct mtd_info *mtd)
2390 struct nand_chip *chip = mtd->priv;
2392 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2394 /* Grab the lock and see if the device is available */
2395 nand_get_device(chip, mtd, FL_SYNCING);
2396 /* Release it and go back */
2397 nand_release_device(mtd);
2401 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2402 * @mtd: MTD device structure
2403 * @offs: offset relative to mtd start
2405 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2407 /* Check for invalid offset */
2408 if (offs > mtd->size)
2411 return nand_block_checkbad(mtd, offs, 1, 0);
2415 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2416 * @mtd: MTD device structure
2417 * @ofs: offset relative to mtd start
2419 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2421 struct nand_chip *chip = mtd->priv;
2424 if ((ret = nand_block_isbad(mtd, ofs))) {
2425 /* If it was bad already, return success and do nothing. */
2431 return chip->block_markbad(mtd, ofs);
2435 * nand_suspend - [MTD Interface] Suspend the NAND flash
2436 * @mtd: MTD device structure
2438 static int nand_suspend(struct mtd_info *mtd)
2440 struct nand_chip *chip = mtd->priv;
2442 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2446 * nand_resume - [MTD Interface] Resume the NAND flash
2447 * @mtd: MTD device structure
2449 static void nand_resume(struct mtd_info *mtd)
2451 struct nand_chip *chip = mtd->priv;
2453 if (chip->state == FL_PM_SUSPENDED)
2454 nand_release_device(mtd);
2456 printk(KERN_ERR "nand_resume() called for a chip which is not "
2457 "in suspended state\n");
2461 * Set default functions
2463 static void nand_set_defaults(struct nand_chip *chip, int busw)
2465 /* check for proper chip_delay setup, set 20us if not */
2466 if (!chip->chip_delay)
2467 chip->chip_delay = 20;
2469 /* check, if a user supplied command function given */
2470 if (chip->cmdfunc == NULL)
2471 chip->cmdfunc = nand_command;
2473 /* check, if a user supplied wait function given */
2474 if (chip->waitfunc == NULL)
2475 chip->waitfunc = nand_wait;
2477 if (!chip->select_chip)
2478 chip->select_chip = nand_select_chip;
2479 if (!chip->read_byte)
2480 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2481 if (!chip->read_word)
2482 chip->read_word = nand_read_word;
2483 if (!chip->block_bad)
2484 chip->block_bad = nand_block_bad;
2485 if (!chip->block_markbad)
2486 chip->block_markbad = nand_default_block_markbad;
2487 if (!chip->write_buf)
2488 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2489 if (!chip->read_buf)
2490 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2491 if (!chip->verify_buf)
2492 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2493 if (!chip->scan_bbt)
2494 chip->scan_bbt = nand_default_bbt;
2496 if (!chip->controller) {
2497 chip->controller = &chip->hwcontrol;
2499 /* XXX U-BOOT XXX */
2501 spin_lock_init(&chip->controller->lock);
2502 init_waitqueue_head(&chip->controller->wq);
2509 * Get the flash and manufacturer id and lookup if the type is supported
2511 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2512 struct nand_chip *chip,
2513 int busw, int *maf_id)
2515 struct nand_flash_dev *type = NULL;
2516 int i, dev_id, maf_idx;
2517 int tmp_id, tmp_manf;
2519 /* Select the device */
2520 chip->select_chip(mtd, 0);
2523 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2526 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2528 /* Send the command for reading device ID */
2529 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2531 /* Read manufacturer and device IDs */
2532 *maf_id = chip->read_byte(mtd);
2533 dev_id = chip->read_byte(mtd);
2535 /* Try again to make sure, as some systems the bus-hold or other
2536 * interface concerns can cause random data which looks like a
2537 * possibly credible NAND flash to appear. If the two results do
2538 * not match, ignore the device completely.
2541 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2543 /* Read manufacturer and device IDs */
2545 tmp_manf = chip->read_byte(mtd);
2546 tmp_id = chip->read_byte(mtd);
2548 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2549 printk(KERN_INFO "%s: second ID read did not match "
2550 "%02x,%02x against %02x,%02x\n", __func__,
2551 *maf_id, dev_id, tmp_manf, tmp_id);
2552 return ERR_PTR(-ENODEV);
2555 /* Lookup the flash id */
2556 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2557 if (dev_id == nand_flash_ids[i].id) {
2558 type = &nand_flash_ids[i];
2564 return ERR_PTR(-ENODEV);
2567 mtd->name = type->name;
2569 chip->chipsize = type->chipsize << 20;
2571 /* Newer devices have all the information in additional id bytes */
2572 if (!type->pagesize) {
2574 /* The 3rd id byte holds MLC / multichip data */
2575 chip->cellinfo = chip->read_byte(mtd);
2576 /* The 4th id byte is the important one */
2577 extid = chip->read_byte(mtd);
2579 mtd->writesize = 1024 << (extid & 0x3);
2582 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2584 /* Calc blocksize. Blocksize is multiples of 64KiB */
2585 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2587 /* Get buswidth information */
2588 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2592 * Old devices have chip data hardcoded in the device id table
2594 mtd->erasesize = type->erasesize;
2595 mtd->writesize = type->pagesize;
2596 mtd->oobsize = mtd->writesize / 32;
2597 busw = type->options & NAND_BUSWIDTH_16;
2600 /* Try to identify manufacturer */
2601 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2602 if (nand_manuf_ids[maf_idx].id == *maf_id)
2607 * Check, if buswidth is correct. Hardware drivers should set
2610 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2611 printk(KERN_INFO "NAND device: Manufacturer ID:"
2612 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2613 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2614 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2615 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2617 return ERR_PTR(-EINVAL);
2620 /* Calculate the address shift from the page size */
2621 chip->page_shift = ffs(mtd->writesize) - 1;
2622 /* Convert chipsize to number of pages per chip -1. */
2623 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2625 chip->bbt_erase_shift = chip->phys_erase_shift =
2626 ffs(mtd->erasesize) - 1;
2627 chip->chip_shift = ffs(chip->chipsize) - 1;
2629 /* Set the bad block position */
2630 chip->badblockpos = mtd->writesize > 512 ?
2631 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2633 /* Get chip options, preserve non chip based options */
2634 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2635 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2638 * Set chip as a default. Board drivers can override it, if necessary
2640 chip->options |= NAND_NO_AUTOINCR;
2642 /* Check if chip is a not a samsung device. Do not clear the
2643 * options for chips which are not having an extended id.
2645 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2646 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2648 /* Check for AND chips with 4 page planes */
2649 if (chip->options & NAND_4PAGE_ARRAY)
2650 chip->erase_cmd = multi_erase_cmd;
2652 chip->erase_cmd = single_erase_cmd;
2654 /* Do not replace user supplied command function ! */
2655 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2656 chip->cmdfunc = nand_command_lp;
2658 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2659 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2660 nand_manuf_ids[maf_idx].name, type->name);
2666 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2667 * @mtd: MTD device structure
2668 * @maxchips: Number of chips to scan for
2670 * This is the first phase of the normal nand_scan() function. It
2671 * reads the flash ID and sets up MTD fields accordingly.
2673 * The mtd->owner field must be set to the module of the caller.
2675 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2677 int i, busw, nand_maf_id;
2678 struct nand_chip *chip = mtd->priv;
2679 struct nand_flash_dev *type;
2681 /* Get buswidth to select the correct functions */
2682 busw = chip->options & NAND_BUSWIDTH_16;
2683 /* Set the default functions */
2684 nand_set_defaults(chip, busw);
2686 /* Read the flash type */
2687 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2690 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2691 printk(KERN_WARNING "No NAND device found!!!\n");
2693 chip->select_chip(mtd, -1);
2694 return PTR_ERR(type);
2697 /* Check for a chip array */
2698 for (i = 1; i < maxchips; i++) {
2699 chip->select_chip(mtd, i);
2700 /* See comment in nand_get_flash_type for reset */
2701 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2702 /* Send the command for reading device ID */
2703 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2704 /* Read manufacturer and device IDs */
2705 if (nand_maf_id != chip->read_byte(mtd) ||
2706 type->id != chip->read_byte(mtd))
2711 printk(KERN_INFO "%d NAND chips detected\n", i);
2714 /* Store the number of chips and calc total size for mtd */
2716 mtd->size = i * chip->chipsize;
2723 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2724 * @mtd: MTD device structure
2725 * @maxchips: Number of chips to scan for
2727 * This is the second phase of the normal nand_scan() function. It
2728 * fills out all the uninitialized function pointers with the defaults
2729 * and scans for a bad block table if appropriate.
2731 int nand_scan_tail(struct mtd_info *mtd)
2734 struct nand_chip *chip = mtd->priv;
2736 if (!(chip->options & NAND_OWN_BUFFERS))
2737 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2741 /* Set the internal oob buffer location, just after the page data */
2742 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2745 * If no default placement scheme is given, select an appropriate one
2747 if (!chip->ecc.layout) {
2748 switch (mtd->oobsize) {
2750 chip->ecc.layout = &nand_oob_8;
2753 chip->ecc.layout = &nand_oob_16;
2756 chip->ecc.layout = &nand_oob_64;
2759 chip->ecc.layout = &nand_oob_128;
2762 printk(KERN_WARNING "No oob scheme defined for "
2763 "oobsize %d\n", mtd->oobsize);
2768 if (!chip->write_page)
2769 chip->write_page = nand_write_page;
2772 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2773 * selected and we have 256 byte pagesize fallback to software ECC
2775 if (!chip->ecc.read_page_raw)
2776 chip->ecc.read_page_raw = nand_read_page_raw;
2777 if (!chip->ecc.write_page_raw)
2778 chip->ecc.write_page_raw = nand_write_page_raw;
2780 switch (chip->ecc.mode) {
2781 case NAND_ECC_HW_OOB_FIRST:
2782 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2783 if (!chip->ecc.calculate || !chip->ecc.correct ||
2785 printk(KERN_WARNING "No ECC functions supplied, "
2786 "Hardware ECC not possible\n");
2789 if (!chip->ecc.read_page)
2790 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2793 /* Use standard hwecc read page function ? */
2794 if (!chip->ecc.read_page)
2795 chip->ecc.read_page = nand_read_page_hwecc;
2796 if (!chip->ecc.write_page)
2797 chip->ecc.write_page = nand_write_page_hwecc;
2798 if (!chip->ecc.read_oob)
2799 chip->ecc.read_oob = nand_read_oob_std;
2800 if (!chip->ecc.write_oob)
2801 chip->ecc.write_oob = nand_write_oob_std;
2803 case NAND_ECC_HW_SYNDROME:
2804 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2805 !chip->ecc.hwctl) &&
2806 (!chip->ecc.read_page ||
2807 chip->ecc.read_page == nand_read_page_hwecc ||
2808 !chip->ecc.write_page ||
2809 chip->ecc.write_page == nand_write_page_hwecc)) {
2810 printk(KERN_WARNING "No ECC functions supplied, "
2811 "Hardware ECC not possible\n");
2814 /* Use standard syndrome read/write page function ? */
2815 if (!chip->ecc.read_page)
2816 chip->ecc.read_page = nand_read_page_syndrome;
2817 if (!chip->ecc.write_page)
2818 chip->ecc.write_page = nand_write_page_syndrome;
2819 if (!chip->ecc.read_oob)
2820 chip->ecc.read_oob = nand_read_oob_syndrome;
2821 if (!chip->ecc.write_oob)
2822 chip->ecc.write_oob = nand_write_oob_syndrome;
2824 if (mtd->writesize >= chip->ecc.size)
2826 printk(KERN_WARNING "%d byte HW ECC not possible on "
2827 "%d byte page size, fallback to SW ECC\n",
2828 chip->ecc.size, mtd->writesize);
2829 chip->ecc.mode = NAND_ECC_SOFT;
2832 chip->ecc.calculate = nand_calculate_ecc;
2833 chip->ecc.correct = nand_correct_data;
2834 chip->ecc.read_page = nand_read_page_swecc;
2835 chip->ecc.read_subpage = nand_read_subpage;
2836 chip->ecc.write_page = nand_write_page_swecc;
2837 chip->ecc.read_oob = nand_read_oob_std;
2838 chip->ecc.write_oob = nand_write_oob_std;
2839 chip->ecc.size = 256;
2840 chip->ecc.bytes = 3;
2844 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2845 "This is not recommended !!\n");
2846 chip->ecc.read_page = nand_read_page_raw;
2847 chip->ecc.write_page = nand_write_page_raw;
2848 chip->ecc.read_oob = nand_read_oob_std;
2849 chip->ecc.write_oob = nand_write_oob_std;
2850 chip->ecc.size = mtd->writesize;
2851 chip->ecc.bytes = 0;
2855 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2861 * The number of bytes available for a client to place data into
2862 * the out of band area
2864 chip->ecc.layout->oobavail = 0;
2865 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2866 chip->ecc.layout->oobavail +=
2867 chip->ecc.layout->oobfree[i].length;
2868 mtd->oobavail = chip->ecc.layout->oobavail;
2871 * Set the number of read / write steps for one page depending on ECC
2874 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2875 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2876 printk(KERN_WARNING "Invalid ecc parameters\n");
2879 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2882 * Allow subpage writes up to ecc.steps. Not possible for MLC
2885 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2886 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2887 switch(chip->ecc.steps) {
2889 mtd->subpage_sft = 1;
2893 mtd->subpage_sft = 2;
2897 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2899 /* Initialize state */
2900 chip->state = FL_READY;
2902 /* De-select the device */
2903 chip->select_chip(mtd, -1);
2905 /* Invalidate the pagebuffer reference */
2908 /* Fill in remaining MTD driver data */
2909 mtd->type = MTD_NANDFLASH;
2910 mtd->flags = MTD_CAP_NANDFLASH;
2911 mtd->erase = nand_erase;
2913 mtd->unpoint = NULL;
2914 mtd->read = nand_read;
2915 mtd->write = nand_write;
2916 mtd->read_oob = nand_read_oob;
2917 mtd->write_oob = nand_write_oob;
2918 mtd->sync = nand_sync;
2921 mtd->suspend = nand_suspend;
2922 mtd->resume = nand_resume;
2923 mtd->block_isbad = nand_block_isbad;
2924 mtd->block_markbad = nand_block_markbad;
2926 /* propagate ecc.layout to mtd_info */
2927 mtd->ecclayout = chip->ecc.layout;
2929 /* Check, if we should skip the bad block table scan */
2930 if (chip->options & NAND_SKIP_BBTSCAN)
2931 chip->options |= NAND_BBT_SCANNED;
2936 /* module_text_address() isn't exported, and it's mostly a pointless
2937 test if this is a module _anyway_ -- they'd have to try _really_ hard
2938 to call us from in-kernel code if the core NAND support is modular. */
2940 #define caller_is_module() (1)
2942 #define caller_is_module() \
2943 module_text_address((unsigned long)__builtin_return_address(0))
2947 * nand_scan - [NAND Interface] Scan for the NAND device
2948 * @mtd: MTD device structure
2949 * @maxchips: Number of chips to scan for
2951 * This fills out all the uninitialized function pointers
2952 * with the defaults.
2953 * The flash ID is read and the mtd/chip structures are
2954 * filled with the appropriate values.
2955 * The mtd->owner field must be set to the module of the caller
2958 int nand_scan(struct mtd_info *mtd, int maxchips)
2962 /* Many callers got this wrong, so check for it for a while... */
2963 /* XXX U-BOOT XXX */
2965 if (!mtd->owner && caller_is_module()) {
2966 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2971 ret = nand_scan_ident(mtd, maxchips);
2973 ret = nand_scan_tail(mtd);
2978 * nand_release - [NAND Interface] Free resources held by the NAND device
2979 * @mtd: MTD device structure
2981 void nand_release(struct mtd_info *mtd)
2983 struct nand_chip *chip = mtd->priv;
2985 #ifdef CONFIG_MTD_PARTITIONS
2986 /* Deregister partitions */
2987 del_mtd_partitions(mtd);
2989 /* Deregister the device */
2990 /* XXX U-BOOT XXX */
2992 del_mtd_device(mtd);
2995 /* Free bad block table memory */
2997 if (!(chip->options & NAND_OWN_BUFFERS))
2998 kfree(chip->buffers);
3001 /* XXX U-BOOT XXX */
3003 EXPORT_SYMBOL_GPL(nand_scan);
3004 EXPORT_SYMBOL_GPL(nand_scan_ident);
3005 EXPORT_SYMBOL_GPL(nand_scan_tail);
3006 EXPORT_SYMBOL_GPL(nand_release);
3008 static int __init nand_base_init(void)
3010 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3014 static void __exit nand_base_exit(void)
3016 led_trigger_unregister_simple(nand_led_trigger);
3019 module_init(nand_base_init);
3020 module_exit(nand_base_exit);
3022 MODULE_LICENSE("GPL");
3023 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3024 MODULE_DESCRIPTION("Generic NAND flash driver code");