5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
37 #define ENOTSUPP 524 /* Operation is not supported */
41 #include <linux/err.h>
42 #include <linux/mtd/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/nand_bch.h>
48 #ifdef CONFIG_MTD_PARTITIONS
49 #include <linux/mtd/partitions.h>
53 #include <asm/errno.h>
56 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
57 * a flash. NAND flash is initialized prior to interrupts so standard timers
58 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
59 * which is greater than (max NAND reset time / NAND status read time).
60 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
62 #ifndef CONFIG_SYS_NAND_RESET_CNT
63 #define CONFIG_SYS_NAND_RESET_CNT 200000
66 /* Define default oob placement schemes for large and small page devices */
67 static struct nand_ecclayout nand_oob_8 = {
77 static struct nand_ecclayout nand_oob_16 = {
79 .eccpos = {0, 1, 2, 3, 6, 7},
85 static struct nand_ecclayout nand_oob_64 = {
88 40, 41, 42, 43, 44, 45, 46, 47,
89 48, 49, 50, 51, 52, 53, 54, 55,
90 56, 57, 58, 59, 60, 61, 62, 63},
96 static struct nand_ecclayout nand_oob_128 = {
99 80, 81, 82, 83, 84, 85, 86, 87,
100 88, 89, 90, 91, 92, 93, 94, 95,
101 96, 97, 98, 99, 100, 101, 102, 103,
102 104, 105, 106, 107, 108, 109, 110, 111,
103 112, 113, 114, 115, 116, 117, 118, 119,
104 120, 121, 122, 123, 124, 125, 126, 127},
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
118 static int check_offs_len(struct mtd_info *mtd,
119 loff_t ofs, uint64_t len)
121 struct nand_chip *chip = mtd->priv;
124 /* Start address must align on block boundary */
125 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
126 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
130 /* Length must align on block boundary */
131 if (len & ((1 << chip->phys_erase_shift) - 1)) {
132 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
137 /* Do not allow past end of device */
138 if (ofs + len > mtd->size) {
139 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
148 * nand_release_device - [GENERIC] release chip
149 * @mtd: MTD device structure
151 * Deselect, release chip lock and wake up anyone waiting on the device
153 static void nand_release_device(struct mtd_info *mtd)
155 struct nand_chip *chip = mtd->priv;
157 /* De-select the NAND device */
158 chip->select_chip(mtd, -1);
162 * nand_read_byte - [DEFAULT] read one byte from the chip
163 * @mtd: MTD device structure
165 * Default read function for 8bit buswith
167 uint8_t nand_read_byte(struct mtd_info *mtd)
169 struct nand_chip *chip = mtd->priv;
170 return readb(chip->IO_ADDR_R);
174 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
175 * @mtd: MTD device structure
177 * Default read function for 16bit buswith with
178 * endianess conversion
180 static uint8_t nand_read_byte16(struct mtd_info *mtd)
182 struct nand_chip *chip = mtd->priv;
183 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
187 * nand_read_word - [DEFAULT] read one word from the chip
188 * @mtd: MTD device structure
190 * Default read function for 16bit buswith without
191 * endianess conversion
193 static u16 nand_read_word(struct mtd_info *mtd)
195 struct nand_chip *chip = mtd->priv;
196 return readw(chip->IO_ADDR_R);
200 * nand_select_chip - [DEFAULT] control CE line
201 * @mtd: MTD device structure
202 * @chipnr: chipnumber to select, -1 for deselect
204 * Default select function for 1 chip devices.
206 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
208 struct nand_chip *chip = mtd->priv;
212 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
223 * nand_write_buf - [DEFAULT] write buffer to chip
224 * @mtd: MTD device structure
226 * @len: number of bytes to write
228 * Default write function for 8bit buswith
230 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
233 struct nand_chip *chip = mtd->priv;
235 for (i = 0; i < len; i++)
236 writeb(buf[i], chip->IO_ADDR_W);
240 * nand_read_buf - [DEFAULT] read chip data into buffer
241 * @mtd: MTD device structure
242 * @buf: buffer to store date
243 * @len: number of bytes to read
245 * Default read function for 8bit buswith
247 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
250 struct nand_chip *chip = mtd->priv;
252 for (i = 0; i < len; i++)
253 buf[i] = readb(chip->IO_ADDR_R);
257 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
258 * @mtd: MTD device structure
259 * @buf: buffer containing the data to compare
260 * @len: number of bytes to compare
262 * Default verify function for 8bit buswith
264 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
267 struct nand_chip *chip = mtd->priv;
269 for (i = 0; i < len; i++)
270 if (buf[i] != readb(chip->IO_ADDR_R))
276 * nand_write_buf16 - [DEFAULT] write buffer to chip
277 * @mtd: MTD device structure
279 * @len: number of bytes to write
281 * Default write function for 16bit buswith
283 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
286 struct nand_chip *chip = mtd->priv;
287 u16 *p = (u16 *) buf;
290 for (i = 0; i < len; i++)
291 writew(p[i], chip->IO_ADDR_W);
296 * nand_read_buf16 - [DEFAULT] read chip data into buffer
297 * @mtd: MTD device structure
298 * @buf: buffer to store date
299 * @len: number of bytes to read
301 * Default read function for 16bit buswith
303 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
306 struct nand_chip *chip = mtd->priv;
307 u16 *p = (u16 *) buf;
310 for (i = 0; i < len; i++)
311 p[i] = readw(chip->IO_ADDR_R);
315 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
316 * @mtd: MTD device structure
317 * @buf: buffer containing the data to compare
318 * @len: number of bytes to compare
320 * Default verify function for 16bit buswith
322 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
325 struct nand_chip *chip = mtd->priv;
326 u16 *p = (u16 *) buf;
329 for (i = 0; i < len; i++)
330 if (p[i] != readw(chip->IO_ADDR_R))
337 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
338 * @mtd: MTD device structure
339 * @ofs: offset from device start
340 * @getchip: 0, if the chip is already selected
342 * Check, if the block is bad.
344 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
346 int page, chipnr, res = 0;
347 struct nand_chip *chip = mtd->priv;
350 if (chip->options & NAND_BBT_SCANLASTPAGE)
351 ofs += mtd->erasesize - mtd->writesize;
353 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
356 chipnr = (int)(ofs >> chip->chip_shift);
358 nand_get_device(chip, mtd, FL_READING);
360 /* Select the NAND device */
361 chip->select_chip(mtd, chipnr);
364 if (chip->options & NAND_BUSWIDTH_16) {
365 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
367 bad = cpu_to_le16(chip->read_word(mtd));
368 if (chip->badblockpos & 0x1)
373 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
374 bad = chip->read_byte(mtd);
377 if (likely(chip->badblockbits == 8))
380 res = hweight8(bad) < chip->badblockbits;
383 nand_release_device(mtd);
389 * nand_default_block_markbad - [DEFAULT] mark a block bad
390 * @mtd: MTD device structure
391 * @ofs: offset from device start
393 * This is the default implementation, which can be overridden by
394 * a hardware specific driver.
396 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
398 struct nand_chip *chip = mtd->priv;
399 uint8_t buf[2] = { 0, 0 };
400 int block, ret, i = 0;
402 if (chip->options & NAND_BBT_SCANLASTPAGE)
403 ofs += mtd->erasesize - mtd->writesize;
405 /* Get block number */
406 block = (int)(ofs >> chip->bbt_erase_shift);
408 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
410 /* Do we have a flash based bad block table ? */
411 if (chip->options & NAND_USE_FLASH_BBT)
412 ret = nand_update_bbt(mtd, ofs);
414 nand_get_device(chip, mtd, FL_WRITING);
416 /* Write to first two pages and to byte 1 and 6 if necessary.
417 * If we write to more than one location, the first error
418 * encountered quits the procedure. We write two bytes per
419 * location, so we dont have to mess with 16 bit access.
422 chip->ops.len = chip->ops.ooblen = 2;
423 chip->ops.datbuf = NULL;
424 chip->ops.oobbuf = buf;
425 chip->ops.ooboffs = chip->badblockpos & ~0x01;
427 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
429 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
430 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
432 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
435 ofs += mtd->writesize;
436 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
439 nand_release_device(mtd);
442 mtd->ecc_stats.badblocks++;
448 * nand_check_wp - [GENERIC] check if the chip is write protected
449 * @mtd: MTD device structure
450 * Check, if the device is write protected
452 * The function expects, that the device is already selected
454 static int nand_check_wp(struct mtd_info *mtd)
456 struct nand_chip *chip = mtd->priv;
458 /* broken xD cards report WP despite being writable */
459 if (chip->options & NAND_BROKEN_XD)
462 /* Check the WP bit */
463 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
464 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
468 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
469 * @mtd: MTD device structure
470 * @ofs: offset from device start
471 * @getchip: 0, if the chip is already selected
472 * @allowbbt: 1, if its allowed to access the bbt area
474 * Check, if the block is bad. Either by reading the bad block table or
475 * calling of the scan function.
477 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
480 struct nand_chip *chip = mtd->priv;
482 if (!(chip->options & NAND_BBT_SCANNED)) {
483 chip->options |= NAND_BBT_SCANNED;
488 return chip->block_bad(mtd, ofs, getchip);
490 /* Return info from the table */
491 return nand_isbad_bbt(mtd, ofs, allowbbt);
495 * Wait for the ready pin, after a command
496 * The timeout is catched later.
498 void nand_wait_ready(struct mtd_info *mtd)
500 struct nand_chip *chip = mtd->priv;
501 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
504 time_start = get_timer(0);
506 /* wait until command is processed or timeout occures */
507 while (get_timer(time_start) < timeo) {
509 if (chip->dev_ready(mtd))
515 * nand_command - [DEFAULT] Send command to NAND device
516 * @mtd: MTD device structure
517 * @command: the command to be sent
518 * @column: the column address for this command, -1 if none
519 * @page_addr: the page address for this command, -1 if none
521 * Send command to NAND device. This function is used for small page
522 * devices (256/512 Bytes per page)
524 static void nand_command(struct mtd_info *mtd, unsigned int command,
525 int column, int page_addr)
527 register struct nand_chip *chip = mtd->priv;
528 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
529 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
532 * Write out the command to the device.
534 if (command == NAND_CMD_SEQIN) {
537 if (column >= mtd->writesize) {
539 column -= mtd->writesize;
540 readcmd = NAND_CMD_READOOB;
541 } else if (column < 256) {
542 /* First 256 bytes --> READ0 */
543 readcmd = NAND_CMD_READ0;
546 readcmd = NAND_CMD_READ1;
548 chip->cmd_ctrl(mtd, readcmd, ctrl);
549 ctrl &= ~NAND_CTRL_CHANGE;
551 chip->cmd_ctrl(mtd, command, ctrl);
554 * Address cycle, when necessary
556 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
557 /* Serially input address */
559 /* Adjust columns for 16 bit buswidth */
560 if (chip->options & NAND_BUSWIDTH_16)
562 chip->cmd_ctrl(mtd, column, ctrl);
563 ctrl &= ~NAND_CTRL_CHANGE;
565 if (page_addr != -1) {
566 chip->cmd_ctrl(mtd, page_addr, ctrl);
567 ctrl &= ~NAND_CTRL_CHANGE;
568 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
569 /* One more address cycle for devices > 32MiB */
570 if (chip->chipsize > (32 << 20))
571 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
573 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
576 * program and erase have their own busy handlers
577 * status and sequential in needs no delay
581 case NAND_CMD_PAGEPROG:
582 case NAND_CMD_ERASE1:
583 case NAND_CMD_ERASE2:
585 case NAND_CMD_STATUS:
591 udelay(chip->chip_delay);
592 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
593 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
595 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
596 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
600 /* This applies to read commands */
603 * If we don't have access to the busy pin, we apply the given
606 if (!chip->dev_ready) {
607 udelay(chip->chip_delay);
611 /* Apply this short delay always to ensure that we do wait tWB in
612 * any case on any machine. */
615 nand_wait_ready(mtd);
619 * nand_command_lp - [DEFAULT] Send command to NAND large page device
620 * @mtd: MTD device structure
621 * @command: the command to be sent
622 * @column: the column address for this command, -1 if none
623 * @page_addr: the page address for this command, -1 if none
625 * Send command to NAND device. This is the version for the new large page
626 * devices We dont have the separate regions as we have in the small page
627 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
629 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
630 int column, int page_addr)
632 register struct nand_chip *chip = mtd->priv;
633 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
635 /* Emulate NAND_CMD_READOOB */
636 if (command == NAND_CMD_READOOB) {
637 column += mtd->writesize;
638 command = NAND_CMD_READ0;
641 /* Command latch cycle */
642 chip->cmd_ctrl(mtd, command & 0xff,
643 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
645 if (column != -1 || page_addr != -1) {
646 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
648 /* Serially input address */
650 /* Adjust columns for 16 bit buswidth */
651 if (chip->options & NAND_BUSWIDTH_16)
653 chip->cmd_ctrl(mtd, column, ctrl);
654 ctrl &= ~NAND_CTRL_CHANGE;
655 chip->cmd_ctrl(mtd, column >> 8, ctrl);
657 if (page_addr != -1) {
658 chip->cmd_ctrl(mtd, page_addr, ctrl);
659 chip->cmd_ctrl(mtd, page_addr >> 8,
660 NAND_NCE | NAND_ALE);
661 /* One more address cycle for devices > 128MiB */
662 if (chip->chipsize > (128 << 20))
663 chip->cmd_ctrl(mtd, page_addr >> 16,
664 NAND_NCE | NAND_ALE);
667 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
670 * program and erase have their own busy handlers
671 * status, sequential in, and deplete1 need no delay
675 case NAND_CMD_CACHEDPROG:
676 case NAND_CMD_PAGEPROG:
677 case NAND_CMD_ERASE1:
678 case NAND_CMD_ERASE2:
681 case NAND_CMD_STATUS:
682 case NAND_CMD_DEPLETE1:
686 * read error status commands require only a short delay
688 case NAND_CMD_STATUS_ERROR:
689 case NAND_CMD_STATUS_ERROR0:
690 case NAND_CMD_STATUS_ERROR1:
691 case NAND_CMD_STATUS_ERROR2:
692 case NAND_CMD_STATUS_ERROR3:
693 udelay(chip->chip_delay);
699 udelay(chip->chip_delay);
700 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
701 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
702 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
703 NAND_NCE | NAND_CTRL_CHANGE);
704 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
708 case NAND_CMD_RNDOUT:
709 /* No ready / busy check necessary */
710 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
711 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
712 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
713 NAND_NCE | NAND_CTRL_CHANGE);
717 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
718 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
719 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
720 NAND_NCE | NAND_CTRL_CHANGE);
722 /* This applies to read commands */
725 * If we don't have access to the busy pin, we apply the given
728 if (!chip->dev_ready) {
729 udelay(chip->chip_delay);
734 /* Apply this short delay always to ensure that we do wait tWB in
735 * any case on any machine. */
738 nand_wait_ready(mtd);
742 * nand_get_device - [GENERIC] Get chip for selected access
743 * @chip: the nand chip descriptor
744 * @mtd: MTD device structure
745 * @new_state: the state which is requested
747 * Get the device and lock it for exclusive access
750 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
752 chip->state = new_state;
757 * nand_wait - [DEFAULT] wait until the command is done
758 * @mtd: MTD device structure
759 * @chip: NAND chip structure
761 * Wait for command done. This applies to erase and program only
762 * Erase can take up to 400ms and program up to 20ms according to
763 * general NAND and SmartMedia specs
765 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
768 int state = chip->state;
771 if (state == FL_ERASING)
772 timeo = (CONFIG_SYS_HZ * 400) / 1000;
774 timeo = (CONFIG_SYS_HZ * 20) / 1000;
776 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
777 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
779 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
781 time_start = get_timer(0);
784 if (get_timer(time_start) > timeo) {
789 if (chip->dev_ready) {
790 if (chip->dev_ready(mtd))
793 if (chip->read_byte(mtd) & NAND_STATUS_READY)
797 #ifdef PPCHAMELON_NAND_TIMER_HACK
798 time_start = get_timer(0);
799 while (get_timer(time_start) < 10)
801 #endif /* PPCHAMELON_NAND_TIMER_HACK */
803 return (int)chip->read_byte(mtd);
807 * nand_read_page_raw - [Intern] read raw page data without ecc
808 * @mtd: mtd info structure
809 * @chip: nand chip info structure
810 * @buf: buffer to store read data
811 * @page: page number to read
813 * Not for syndrome calculating ecc controllers, which use a special oob layout
815 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
816 uint8_t *buf, int page)
818 chip->read_buf(mtd, buf, mtd->writesize);
819 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
824 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
825 * @mtd: mtd info structure
826 * @chip: nand chip info structure
827 * @buf: buffer to store read data
828 * @page: page number to read
830 * We need a special oob layout and handling even when OOB isn't used.
832 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
833 struct nand_chip *chip,
834 uint8_t *buf, int page)
836 int eccsize = chip->ecc.size;
837 int eccbytes = chip->ecc.bytes;
838 uint8_t *oob = chip->oob_poi;
841 for (steps = chip->ecc.steps; steps > 0; steps--) {
842 chip->read_buf(mtd, buf, eccsize);
845 if (chip->ecc.prepad) {
846 chip->read_buf(mtd, oob, chip->ecc.prepad);
847 oob += chip->ecc.prepad;
850 chip->read_buf(mtd, oob, eccbytes);
853 if (chip->ecc.postpad) {
854 chip->read_buf(mtd, oob, chip->ecc.postpad);
855 oob += chip->ecc.postpad;
859 size = mtd->oobsize - (oob - chip->oob_poi);
861 chip->read_buf(mtd, oob, size);
867 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
868 * @mtd: mtd info structure
869 * @chip: nand chip info structure
870 * @buf: buffer to store read data
871 * @page: page number to read
873 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
874 uint8_t *buf, int page)
876 int i, eccsize = chip->ecc.size;
877 int eccbytes = chip->ecc.bytes;
878 int eccsteps = chip->ecc.steps;
880 uint8_t *ecc_calc = chip->buffers->ecccalc;
881 uint8_t *ecc_code = chip->buffers->ecccode;
882 uint32_t *eccpos = chip->ecc.layout->eccpos;
884 chip->ecc.read_page_raw(mtd, chip, buf, page);
886 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
887 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
889 for (i = 0; i < chip->ecc.total; i++)
890 ecc_code[i] = chip->oob_poi[eccpos[i]];
892 eccsteps = chip->ecc.steps;
895 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
898 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
900 mtd->ecc_stats.failed++;
902 mtd->ecc_stats.corrected += stat;
908 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
909 * @mtd: mtd info structure
910 * @chip: nand chip info structure
911 * @data_offs: offset of requested data within the page
912 * @readlen: data length
913 * @bufpoi: buffer to store read data
915 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
916 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
918 int start_step, end_step, num_steps;
919 uint32_t *eccpos = chip->ecc.layout->eccpos;
921 int data_col_addr, i, gaps = 0;
922 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
923 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
926 /* Column address wihin the page aligned to ECC size (256bytes). */
927 start_step = data_offs / chip->ecc.size;
928 end_step = (data_offs + readlen - 1) / chip->ecc.size;
929 num_steps = end_step - start_step + 1;
931 /* Data size aligned to ECC ecc.size*/
932 datafrag_len = num_steps * chip->ecc.size;
933 eccfrag_len = num_steps * chip->ecc.bytes;
935 data_col_addr = start_step * chip->ecc.size;
936 /* If we read not a page aligned data */
937 if (data_col_addr != 0)
938 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
940 p = bufpoi + data_col_addr;
941 chip->read_buf(mtd, p, datafrag_len);
944 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
945 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
947 /* The performance is faster if to position offsets
948 according to ecc.pos. Let make sure here that
949 there are no gaps in ecc positions */
950 for (i = 0; i < eccfrag_len - 1; i++) {
951 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
952 eccpos[i + start_step * chip->ecc.bytes + 1]) {
958 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
959 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
961 /* send the command to read the particular ecc bytes */
962 /* take care about buswidth alignment in read_buf */
963 index = start_step * chip->ecc.bytes;
965 aligned_pos = eccpos[index] & ~(busw - 1);
966 aligned_len = eccfrag_len;
967 if (eccpos[index] & (busw - 1))
969 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
972 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
973 mtd->writesize + aligned_pos, -1);
974 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
977 for (i = 0; i < eccfrag_len; i++)
978 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
980 p = bufpoi + data_col_addr;
981 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
984 stat = chip->ecc.correct(mtd, p,
985 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
987 mtd->ecc_stats.failed++;
989 mtd->ecc_stats.corrected += stat;
995 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
996 * @mtd: mtd info structure
997 * @chip: nand chip info structure
998 * @buf: buffer to store read data
999 * @page: page number to read
1001 * Not for syndrome calculating ecc controllers which need a special oob layout
1003 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1004 uint8_t *buf, int page)
1006 int i, eccsize = chip->ecc.size;
1007 int eccbytes = chip->ecc.bytes;
1008 int eccsteps = chip->ecc.steps;
1010 uint8_t *ecc_calc = chip->buffers->ecccalc;
1011 uint8_t *ecc_code = chip->buffers->ecccode;
1012 uint32_t *eccpos = chip->ecc.layout->eccpos;
1014 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1015 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1016 chip->read_buf(mtd, p, eccsize);
1017 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1019 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1021 for (i = 0; i < chip->ecc.total; i++)
1022 ecc_code[i] = chip->oob_poi[eccpos[i]];
1024 eccsteps = chip->ecc.steps;
1027 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1030 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1032 mtd->ecc_stats.failed++;
1034 mtd->ecc_stats.corrected += stat;
1040 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1041 * @mtd: mtd info structure
1042 * @chip: nand chip info structure
1043 * @buf: buffer to store read data
1044 * @page: page number to read
1046 * Hardware ECC for large page chips, require OOB to be read first.
1047 * For this ECC mode, the write_page method is re-used from ECC_HW.
1048 * These methods read/write ECC from the OOB area, unlike the
1049 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1050 * "infix ECC" scheme and reads/writes ECC from the data area, by
1051 * overwriting the NAND manufacturer bad block markings.
1053 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1054 struct nand_chip *chip, uint8_t *buf, int page)
1056 int i, eccsize = chip->ecc.size;
1057 int eccbytes = chip->ecc.bytes;
1058 int eccsteps = chip->ecc.steps;
1060 uint8_t *ecc_code = chip->buffers->ecccode;
1061 uint32_t *eccpos = chip->ecc.layout->eccpos;
1062 uint8_t *ecc_calc = chip->buffers->ecccalc;
1064 /* Read the OOB area first */
1065 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1066 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1067 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1069 for (i = 0; i < chip->ecc.total; i++)
1070 ecc_code[i] = chip->oob_poi[eccpos[i]];
1072 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1075 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1076 chip->read_buf(mtd, p, eccsize);
1077 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1079 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1081 mtd->ecc_stats.failed++;
1083 mtd->ecc_stats.corrected += stat;
1089 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1090 * @mtd: mtd info structure
1091 * @chip: nand chip info structure
1092 * @buf: buffer to store read data
1093 * @page: page number to read
1095 * The hw generator calculates the error syndrome automatically. Therefor
1096 * we need a special oob layout and handling.
1098 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1099 uint8_t *buf, int page)
1101 int i, eccsize = chip->ecc.size;
1102 int eccbytes = chip->ecc.bytes;
1103 int eccsteps = chip->ecc.steps;
1105 uint8_t *oob = chip->oob_poi;
1107 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1110 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1111 chip->read_buf(mtd, p, eccsize);
1113 if (chip->ecc.prepad) {
1114 chip->read_buf(mtd, oob, chip->ecc.prepad);
1115 oob += chip->ecc.prepad;
1118 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1119 chip->read_buf(mtd, oob, eccbytes);
1120 stat = chip->ecc.correct(mtd, p, oob, NULL);
1123 mtd->ecc_stats.failed++;
1125 mtd->ecc_stats.corrected += stat;
1129 if (chip->ecc.postpad) {
1130 chip->read_buf(mtd, oob, chip->ecc.postpad);
1131 oob += chip->ecc.postpad;
1135 /* Calculate remaining oob bytes */
1136 i = mtd->oobsize - (oob - chip->oob_poi);
1138 chip->read_buf(mtd, oob, i);
1144 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1145 * @chip: nand chip structure
1146 * @oob: oob destination address
1147 * @ops: oob ops structure
1148 * @len: size of oob to transfer
1150 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1151 struct mtd_oob_ops *ops, size_t len)
1153 switch (ops->mode) {
1157 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1160 case MTD_OOB_AUTO: {
1161 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1162 uint32_t boffs = 0, roffs = ops->ooboffs;
1165 for (; free->length && len; free++, len -= bytes) {
1166 /* Read request not from offset 0 ? */
1167 if (unlikely(roffs)) {
1168 if (roffs >= free->length) {
1169 roffs -= free->length;
1172 boffs = free->offset + roffs;
1173 bytes = min_t(size_t, len,
1174 (free->length - roffs));
1177 bytes = min_t(size_t, len, free->length);
1178 boffs = free->offset;
1180 memcpy(oob, chip->oob_poi + boffs, bytes);
1192 * nand_do_read_ops - [Internal] Read data with ECC
1194 * @mtd: MTD device structure
1195 * @from: offset to read from
1196 * @ops: oob ops structure
1198 * Internal function. Called with chip held.
1200 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1201 struct mtd_oob_ops *ops)
1203 int chipnr, page, realpage, col, bytes, aligned;
1204 struct nand_chip *chip = mtd->priv;
1205 struct mtd_ecc_stats stats;
1206 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1209 uint32_t readlen = ops->len;
1210 uint32_t oobreadlen = ops->ooblen;
1211 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1212 mtd->oobavail : mtd->oobsize;
1214 uint8_t *bufpoi, *oob, *buf;
1216 stats = mtd->ecc_stats;
1218 chipnr = (int)(from >> chip->chip_shift);
1219 chip->select_chip(mtd, chipnr);
1221 realpage = (int)(from >> chip->page_shift);
1222 page = realpage & chip->pagemask;
1224 col = (int)(from & (mtd->writesize - 1));
1232 bytes = min(mtd->writesize - col, readlen);
1233 aligned = (bytes == mtd->writesize);
1235 /* Is the current page in the buffer ? */
1236 if (realpage != chip->pagebuf || oob) {
1237 bufpoi = aligned ? buf : chip->buffers->databuf;
1239 if (likely(sndcmd)) {
1240 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1244 /* Now read the page into the buffer */
1245 if (unlikely(ops->mode == MTD_OOB_RAW))
1246 ret = chip->ecc.read_page_raw(mtd, chip,
1248 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1249 ret = chip->ecc.read_subpage(mtd, chip,
1250 col, bytes, bufpoi);
1252 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1257 /* Transfer not aligned data */
1259 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1260 !(mtd->ecc_stats.failed - stats.failed))
1261 chip->pagebuf = realpage;
1262 memcpy(buf, chip->buffers->databuf + col, bytes);
1267 if (unlikely(oob)) {
1269 int toread = min(oobreadlen, max_oobsize);
1272 oob = nand_transfer_oob(chip,
1274 oobreadlen -= toread;
1278 if (!(chip->options & NAND_NO_READRDY)) {
1280 * Apply delay or wait for ready/busy pin. Do
1281 * this before the AUTOINCR check, so no
1282 * problems arise if a chip which does auto
1283 * increment is marked as NOAUTOINCR by the
1286 if (!chip->dev_ready)
1287 udelay(chip->chip_delay);
1289 nand_wait_ready(mtd);
1292 memcpy(buf, chip->buffers->databuf + col, bytes);
1301 /* For subsequent reads align to page boundary. */
1303 /* Increment page address */
1306 page = realpage & chip->pagemask;
1307 /* Check, if we cross a chip boundary */
1310 chip->select_chip(mtd, -1);
1311 chip->select_chip(mtd, chipnr);
1314 /* Check, if the chip supports auto page increment
1315 * or if we have hit a block boundary.
1317 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1321 ops->retlen = ops->len - (size_t) readlen;
1323 ops->oobretlen = ops->ooblen - oobreadlen;
1328 if (mtd->ecc_stats.failed - stats.failed)
1331 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1335 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1336 * @mtd: MTD device structure
1337 * @from: offset to read from
1338 * @len: number of bytes to read
1339 * @retlen: pointer to variable to store the number of read bytes
1340 * @buf: the databuffer to put data
1342 * Get hold of the chip and call nand_do_read
1344 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1345 size_t *retlen, uint8_t *buf)
1347 struct nand_chip *chip = mtd->priv;
1350 /* Do not allow reads past end of device */
1351 if ((from + len) > mtd->size)
1356 nand_get_device(chip, mtd, FL_READING);
1358 chip->ops.len = len;
1359 chip->ops.datbuf = buf;
1360 chip->ops.oobbuf = NULL;
1362 ret = nand_do_read_ops(mtd, from, &chip->ops);
1364 *retlen = chip->ops.retlen;
1366 nand_release_device(mtd);
1372 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1373 * @mtd: mtd info structure
1374 * @chip: nand chip info structure
1375 * @page: page number to read
1376 * @sndcmd: flag whether to issue read command or not
1378 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1379 int page, int sndcmd)
1382 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1385 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1390 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1392 * @mtd: mtd info structure
1393 * @chip: nand chip info structure
1394 * @page: page number to read
1395 * @sndcmd: flag whether to issue read command or not
1397 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1398 int page, int sndcmd)
1400 uint8_t *buf = chip->oob_poi;
1401 int length = mtd->oobsize;
1402 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1403 int eccsize = chip->ecc.size;
1404 uint8_t *bufpoi = buf;
1405 int i, toread, sndrnd = 0, pos;
1407 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1408 for (i = 0; i < chip->ecc.steps; i++) {
1410 pos = eccsize + i * (eccsize + chunk);
1411 if (mtd->writesize > 512)
1412 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1414 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1417 toread = min_t(int, length, chunk);
1418 chip->read_buf(mtd, bufpoi, toread);
1423 chip->read_buf(mtd, bufpoi, length);
1429 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1430 * @mtd: mtd info structure
1431 * @chip: nand chip info structure
1432 * @page: page number to write
1434 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1438 const uint8_t *buf = chip->oob_poi;
1439 int length = mtd->oobsize;
1441 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1442 chip->write_buf(mtd, buf, length);
1443 /* Send command to program the OOB data */
1444 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1446 status = chip->waitfunc(mtd, chip);
1448 return status & NAND_STATUS_FAIL ? -EIO : 0;
1452 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1453 * with syndrome - only for large page flash !
1454 * @mtd: mtd info structure
1455 * @chip: nand chip info structure
1456 * @page: page number to write
1458 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1459 struct nand_chip *chip, int page)
1461 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1462 int eccsize = chip->ecc.size, length = mtd->oobsize;
1463 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1464 const uint8_t *bufpoi = chip->oob_poi;
1467 * data-ecc-data-ecc ... ecc-oob
1469 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1471 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1472 pos = steps * (eccsize + chunk);
1477 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1478 for (i = 0; i < steps; i++) {
1480 if (mtd->writesize <= 512) {
1481 uint32_t fill = 0xFFFFFFFF;
1485 int num = min_t(int, len, 4);
1486 chip->write_buf(mtd, (uint8_t *)&fill,
1491 pos = eccsize + i * (eccsize + chunk);
1492 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1496 len = min_t(int, length, chunk);
1497 chip->write_buf(mtd, bufpoi, len);
1502 chip->write_buf(mtd, bufpoi, length);
1504 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1505 status = chip->waitfunc(mtd, chip);
1507 return status & NAND_STATUS_FAIL ? -EIO : 0;
1511 * nand_do_read_oob - [Intern] NAND read out-of-band
1512 * @mtd: MTD device structure
1513 * @from: offset to read from
1514 * @ops: oob operations description structure
1516 * NAND read out-of-band data from the spare area
1518 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1519 struct mtd_oob_ops *ops)
1521 int page, realpage, chipnr, sndcmd = 1;
1522 struct nand_chip *chip = mtd->priv;
1523 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1524 int readlen = ops->ooblen;
1526 uint8_t *buf = ops->oobbuf;
1528 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1529 __func__, (unsigned long long)from, readlen);
1531 if (ops->mode == MTD_OOB_AUTO)
1532 len = chip->ecc.layout->oobavail;
1536 if (unlikely(ops->ooboffs >= len)) {
1537 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1538 "outside oob\n", __func__);
1542 /* Do not allow reads past end of device */
1543 if (unlikely(from >= mtd->size ||
1544 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1545 (from >> chip->page_shift)) * len)) {
1546 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1547 "of device\n", __func__);
1551 chipnr = (int)(from >> chip->chip_shift);
1552 chip->select_chip(mtd, chipnr);
1554 /* Shift to get page */
1555 realpage = (int)(from >> chip->page_shift);
1556 page = realpage & chip->pagemask;
1560 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1562 len = min(len, readlen);
1563 buf = nand_transfer_oob(chip, buf, ops, len);
1565 if (!(chip->options & NAND_NO_READRDY)) {
1567 * Apply delay or wait for ready/busy pin. Do this
1568 * before the AUTOINCR check, so no problems arise if a
1569 * chip which does auto increment is marked as
1570 * NOAUTOINCR by the board driver.
1572 if (!chip->dev_ready)
1573 udelay(chip->chip_delay);
1575 nand_wait_ready(mtd);
1582 /* Increment page address */
1585 page = realpage & chip->pagemask;
1586 /* Check, if we cross a chip boundary */
1589 chip->select_chip(mtd, -1);
1590 chip->select_chip(mtd, chipnr);
1593 /* Check, if the chip supports auto page increment
1594 * or if we have hit a block boundary.
1596 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1600 ops->oobretlen = ops->ooblen;
1605 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1606 * @mtd: MTD device structure
1607 * @from: offset to read from
1608 * @ops: oob operation description structure
1610 * NAND read data and/or out-of-band data
1612 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1613 struct mtd_oob_ops *ops)
1615 struct nand_chip *chip = mtd->priv;
1616 int ret = -ENOTSUPP;
1620 /* Do not allow reads past end of device */
1621 if (ops->datbuf && (from + ops->len) > mtd->size) {
1622 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1623 "beyond end of device\n", __func__);
1627 nand_get_device(chip, mtd, FL_READING);
1629 switch (ops->mode) {
1640 ret = nand_do_read_oob(mtd, from, ops);
1642 ret = nand_do_read_ops(mtd, from, ops);
1645 nand_release_device(mtd);
1651 * nand_write_page_raw - [Intern] raw page write function
1652 * @mtd: mtd info structure
1653 * @chip: nand chip info structure
1656 * Not for syndrome calculating ecc controllers, which use a special oob layout
1658 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1661 chip->write_buf(mtd, buf, mtd->writesize);
1662 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1666 * nand_write_page_raw_syndrome - [Intern] raw page write function
1667 * @mtd: mtd info structure
1668 * @chip: nand chip info structure
1671 * We need a special oob layout and handling even when ECC isn't checked.
1673 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1674 struct nand_chip *chip,
1677 int eccsize = chip->ecc.size;
1678 int eccbytes = chip->ecc.bytes;
1679 uint8_t *oob = chip->oob_poi;
1682 for (steps = chip->ecc.steps; steps > 0; steps--) {
1683 chip->write_buf(mtd, buf, eccsize);
1686 if (chip->ecc.prepad) {
1687 chip->write_buf(mtd, oob, chip->ecc.prepad);
1688 oob += chip->ecc.prepad;
1691 chip->read_buf(mtd, oob, eccbytes);
1694 if (chip->ecc.postpad) {
1695 chip->write_buf(mtd, oob, chip->ecc.postpad);
1696 oob += chip->ecc.postpad;
1700 size = mtd->oobsize - (oob - chip->oob_poi);
1702 chip->write_buf(mtd, oob, size);
1705 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1706 * @mtd: mtd info structure
1707 * @chip: nand chip info structure
1710 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1713 int i, eccsize = chip->ecc.size;
1714 int eccbytes = chip->ecc.bytes;
1715 int eccsteps = chip->ecc.steps;
1716 uint8_t *ecc_calc = chip->buffers->ecccalc;
1717 const uint8_t *p = buf;
1718 uint32_t *eccpos = chip->ecc.layout->eccpos;
1720 /* Software ecc calculation */
1721 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1722 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1724 for (i = 0; i < chip->ecc.total; i++)
1725 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1727 chip->ecc.write_page_raw(mtd, chip, buf);
1731 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1732 * @mtd: mtd info structure
1733 * @chip: nand chip info structure
1736 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1739 int i, eccsize = chip->ecc.size;
1740 int eccbytes = chip->ecc.bytes;
1741 int eccsteps = chip->ecc.steps;
1742 uint8_t *ecc_calc = chip->buffers->ecccalc;
1743 const uint8_t *p = buf;
1744 uint32_t *eccpos = chip->ecc.layout->eccpos;
1746 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1747 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1748 chip->write_buf(mtd, p, eccsize);
1749 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1752 for (i = 0; i < chip->ecc.total; i++)
1753 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1755 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1759 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1760 * @mtd: mtd info structure
1761 * @chip: nand chip info structure
1764 * The hw generator calculates the error syndrome automatically. Therefor
1765 * we need a special oob layout and handling.
1767 static void nand_write_page_syndrome(struct mtd_info *mtd,
1768 struct nand_chip *chip, const uint8_t *buf)
1770 int i, eccsize = chip->ecc.size;
1771 int eccbytes = chip->ecc.bytes;
1772 int eccsteps = chip->ecc.steps;
1773 const uint8_t *p = buf;
1774 uint8_t *oob = chip->oob_poi;
1776 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1778 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1779 chip->write_buf(mtd, p, eccsize);
1781 if (chip->ecc.prepad) {
1782 chip->write_buf(mtd, oob, chip->ecc.prepad);
1783 oob += chip->ecc.prepad;
1786 chip->ecc.calculate(mtd, p, oob);
1787 chip->write_buf(mtd, oob, eccbytes);
1790 if (chip->ecc.postpad) {
1791 chip->write_buf(mtd, oob, chip->ecc.postpad);
1792 oob += chip->ecc.postpad;
1796 /* Calculate remaining oob bytes */
1797 i = mtd->oobsize - (oob - chip->oob_poi);
1799 chip->write_buf(mtd, oob, i);
1803 * nand_write_page - [REPLACEABLE] write one page
1804 * @mtd: MTD device structure
1805 * @chip: NAND chip descriptor
1806 * @buf: the data to write
1807 * @page: page number to write
1808 * @cached: cached programming
1809 * @raw: use _raw version of write_page
1811 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1812 const uint8_t *buf, int page, int cached, int raw)
1816 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1819 chip->ecc.write_page_raw(mtd, chip, buf);
1821 chip->ecc.write_page(mtd, chip, buf);
1824 * Cached progamming disabled for now, Not sure if its worth the
1825 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1829 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1831 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1832 status = chip->waitfunc(mtd, chip);
1834 * See if operation failed and additional status checks are
1837 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1838 status = chip->errstat(mtd, chip, FL_WRITING, status,
1841 if (status & NAND_STATUS_FAIL)
1844 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1845 status = chip->waitfunc(mtd, chip);
1848 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1849 /* Send command to read back the data */
1850 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1852 if (chip->verify_buf(mtd, buf, mtd->writesize))
1859 * nand_fill_oob - [Internal] Transfer client buffer to oob
1860 * @chip: nand chip structure
1861 * @oob: oob data buffer
1862 * @len: oob data write length
1863 * @ops: oob ops structure
1865 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
1866 struct mtd_oob_ops *ops)
1868 switch (ops->mode) {
1872 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1875 case MTD_OOB_AUTO: {
1876 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1877 uint32_t boffs = 0, woffs = ops->ooboffs;
1880 for (; free->length && len; free++, len -= bytes) {
1881 /* Write request not from offset 0 ? */
1882 if (unlikely(woffs)) {
1883 if (woffs >= free->length) {
1884 woffs -= free->length;
1887 boffs = free->offset + woffs;
1888 bytes = min_t(size_t, len,
1889 (free->length - woffs));
1892 bytes = min_t(size_t, len, free->length);
1893 boffs = free->offset;
1895 memcpy(chip->oob_poi + boffs, oob, bytes);
1906 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1909 * nand_do_write_ops - [Internal] NAND write with ECC
1910 * @mtd: MTD device structure
1911 * @to: offset to write to
1912 * @ops: oob operations description structure
1914 * NAND write with ECC
1916 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1917 struct mtd_oob_ops *ops)
1919 int chipnr, realpage, page, blockmask, column;
1920 struct nand_chip *chip = mtd->priv;
1921 uint32_t writelen = ops->len;
1923 uint32_t oobwritelen = ops->ooblen;
1924 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
1925 mtd->oobavail : mtd->oobsize;
1927 uint8_t *oob = ops->oobbuf;
1928 uint8_t *buf = ops->datbuf;
1935 column = to & (mtd->writesize - 1);
1936 subpage = column || (writelen & (mtd->writesize - 1));
1941 chipnr = (int)(to >> chip->chip_shift);
1942 chip->select_chip(mtd, chipnr);
1944 /* Check, if it is write protected */
1945 if (nand_check_wp(mtd)) {
1946 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1950 realpage = (int)(to >> chip->page_shift);
1951 page = realpage & chip->pagemask;
1952 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1954 /* Invalidate the page cache, when we write to the cached page */
1955 if (to <= (chip->pagebuf << chip->page_shift) &&
1956 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1959 /* If we're not given explicit OOB data, let it be 0xFF */
1961 memset(chip->oob_poi, 0xff, mtd->oobsize);
1963 /* Don't allow multipage oob writes with offset */
1964 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
1970 int bytes = mtd->writesize;
1971 int cached = writelen > bytes && page != blockmask;
1972 uint8_t *wbuf = buf;
1974 /* Partial page write ? */
1975 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1977 bytes = min_t(int, bytes - column, (int) writelen);
1979 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1980 memcpy(&chip->buffers->databuf[column], buf, bytes);
1981 wbuf = chip->buffers->databuf;
1984 if (unlikely(oob)) {
1985 size_t len = min(oobwritelen, oobmaxlen);
1986 oob = nand_fill_oob(chip, oob, len, ops);
1990 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1991 (ops->mode == MTD_OOB_RAW));
2003 page = realpage & chip->pagemask;
2004 /* Check, if we cross a chip boundary */
2007 chip->select_chip(mtd, -1);
2008 chip->select_chip(mtd, chipnr);
2012 ops->retlen = ops->len - writelen;
2014 ops->oobretlen = ops->ooblen;
2019 * nand_write - [MTD Interface] NAND write with ECC
2020 * @mtd: MTD device structure
2021 * @to: offset to write to
2022 * @len: number of bytes to write
2023 * @retlen: pointer to variable to store the number of written bytes
2024 * @buf: the data to write
2026 * NAND write with ECC
2028 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2029 size_t *retlen, const uint8_t *buf)
2031 struct nand_chip *chip = mtd->priv;
2034 /* Do not allow writes past end of device */
2035 if ((to + len) > mtd->size)
2040 nand_get_device(chip, mtd, FL_WRITING);
2042 chip->ops.len = len;
2043 chip->ops.datbuf = (uint8_t *)buf;
2044 chip->ops.oobbuf = NULL;
2046 ret = nand_do_write_ops(mtd, to, &chip->ops);
2048 *retlen = chip->ops.retlen;
2050 nand_release_device(mtd);
2056 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2057 * @mtd: MTD device structure
2058 * @to: offset to write to
2059 * @ops: oob operation description structure
2061 * NAND write out-of-band
2063 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2064 struct mtd_oob_ops *ops)
2066 int chipnr, page, status, len;
2067 struct nand_chip *chip = mtd->priv;
2069 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2070 __func__, (unsigned int)to, (int)ops->ooblen);
2072 if (ops->mode == MTD_OOB_AUTO)
2073 len = chip->ecc.layout->oobavail;
2077 /* Do not allow write past end of page */
2078 if ((ops->ooboffs + ops->ooblen) > len) {
2079 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2080 "past end of page\n", __func__);
2084 if (unlikely(ops->ooboffs >= len)) {
2085 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2086 "write outside oob\n", __func__);
2090 /* Do not allow write past end of device */
2091 if (unlikely(to >= mtd->size ||
2092 ops->ooboffs + ops->ooblen >
2093 ((mtd->size >> chip->page_shift) -
2094 (to >> chip->page_shift)) * len)) {
2095 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2096 "end of device\n", __func__);
2100 chipnr = (int)(to >> chip->chip_shift);
2101 chip->select_chip(mtd, chipnr);
2103 /* Shift to get page */
2104 page = (int)(to >> chip->page_shift);
2107 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2108 * of my DiskOnChip 2000 test units) will clear the whole data page too
2109 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2110 * it in the doc2000 driver in August 1999. dwmw2.
2112 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2114 /* Check, if it is write protected */
2115 if (nand_check_wp(mtd))
2118 /* Invalidate the page cache, if we write to the cached page */
2119 if (page == chip->pagebuf)
2122 memset(chip->oob_poi, 0xff, mtd->oobsize);
2123 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
2124 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2125 memset(chip->oob_poi, 0xff, mtd->oobsize);
2130 ops->oobretlen = ops->ooblen;
2136 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2137 * @mtd: MTD device structure
2138 * @to: offset to write to
2139 * @ops: oob operation description structure
2141 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2142 struct mtd_oob_ops *ops)
2144 struct nand_chip *chip = mtd->priv;
2145 int ret = -ENOTSUPP;
2149 /* Do not allow writes past end of device */
2150 if (ops->datbuf && (to + ops->len) > mtd->size) {
2151 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2152 "end of device\n", __func__);
2156 nand_get_device(chip, mtd, FL_WRITING);
2158 switch (ops->mode) {
2169 ret = nand_do_write_oob(mtd, to, ops);
2171 ret = nand_do_write_ops(mtd, to, ops);
2174 nand_release_device(mtd);
2179 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2180 * @mtd: MTD device structure
2181 * @page: the page address of the block which will be erased
2183 * Standard erase command for NAND chips
2185 static void single_erase_cmd(struct mtd_info *mtd, int page)
2187 struct nand_chip *chip = mtd->priv;
2188 /* Send commands to erase a block */
2189 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2190 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2194 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2195 * @mtd: MTD device structure
2196 * @page: the page address of the block which will be erased
2198 * AND multi block erase command function
2199 * Erase 4 consecutive blocks
2201 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2203 struct nand_chip *chip = mtd->priv;
2204 /* Send commands to erase a block */
2205 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2206 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2207 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2208 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2209 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2213 * nand_erase - [MTD Interface] erase block(s)
2214 * @mtd: MTD device structure
2215 * @instr: erase instruction
2217 * Erase one ore more blocks
2219 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2221 return nand_erase_nand(mtd, instr, 0);
2224 #define BBT_PAGE_MASK 0xffffff3f
2226 * nand_erase_nand - [Internal] erase block(s)
2227 * @mtd: MTD device structure
2228 * @instr: erase instruction
2229 * @allowbbt: allow erasing the bbt area
2231 * Erase one ore more blocks
2233 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2236 int page, status, pages_per_block, ret, chipnr;
2237 struct nand_chip *chip = mtd->priv;
2238 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2239 unsigned int bbt_masked_page = 0xffffffff;
2242 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2243 __func__, (unsigned long long)instr->addr,
2244 (unsigned long long)instr->len);
2246 if (check_offs_len(mtd, instr->addr, instr->len))
2249 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2251 /* Grab the lock and see if the device is available */
2252 nand_get_device(chip, mtd, FL_ERASING);
2254 /* Shift to get first page */
2255 page = (int)(instr->addr >> chip->page_shift);
2256 chipnr = (int)(instr->addr >> chip->chip_shift);
2258 /* Calculate pages in each block */
2259 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2261 /* Select the NAND device */
2262 chip->select_chip(mtd, chipnr);
2264 /* Check, if it is write protected */
2265 if (nand_check_wp(mtd)) {
2266 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2268 instr->state = MTD_ERASE_FAILED;
2273 * If BBT requires refresh, set the BBT page mask to see if the BBT
2274 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2275 * can not be matched. This is also done when the bbt is actually
2276 * erased to avoid recusrsive updates
2278 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2279 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2281 /* Loop through the pages */
2284 instr->state = MTD_ERASING;
2289 * heck if we have a bad block, we do not erase bad blocks !
2291 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2292 chip->page_shift, 0, allowbbt)) {
2293 printk(KERN_WARNING "%s: attempt to erase a bad block "
2294 "at page 0x%08x\n", __func__, page);
2295 instr->state = MTD_ERASE_FAILED;
2300 * Invalidate the page cache, if we erase the block which
2301 * contains the current cached page
2303 if (page <= chip->pagebuf && chip->pagebuf <
2304 (page + pages_per_block))
2307 chip->erase_cmd(mtd, page & chip->pagemask);
2309 status = chip->waitfunc(mtd, chip);
2312 * See if operation failed and additional status checks are
2315 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2316 status = chip->errstat(mtd, chip, FL_ERASING,
2319 /* See if block erase succeeded */
2320 if (status & NAND_STATUS_FAIL) {
2321 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2322 "page 0x%08x\n", __func__, page);
2323 instr->state = MTD_ERASE_FAILED;
2325 ((loff_t)page << chip->page_shift);
2330 * If BBT requires refresh, set the BBT rewrite flag to the
2333 if (bbt_masked_page != 0xffffffff &&
2334 (page & BBT_PAGE_MASK) == bbt_masked_page)
2335 rewrite_bbt[chipnr] =
2336 ((loff_t)page << chip->page_shift);
2338 /* Increment page address and decrement length */
2339 len -= (1 << chip->phys_erase_shift);
2340 page += pages_per_block;
2342 /* Check, if we cross a chip boundary */
2343 if (len && !(page & chip->pagemask)) {
2345 chip->select_chip(mtd, -1);
2346 chip->select_chip(mtd, chipnr);
2349 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2350 * page mask to see if this BBT should be rewritten
2352 if (bbt_masked_page != 0xffffffff &&
2353 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2354 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2358 instr->state = MTD_ERASE_DONE;
2362 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2364 /* Deselect and wake up anyone waiting on the device */
2365 nand_release_device(mtd);
2367 /* Do call back function */
2369 mtd_erase_callback(instr);
2372 * If BBT requires refresh and erase was successful, rewrite any
2373 * selected bad block tables
2375 if (bbt_masked_page == 0xffffffff || ret)
2378 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2379 if (!rewrite_bbt[chipnr])
2381 /* update the BBT for chip */
2382 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2383 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2384 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2385 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2388 /* Return more or less happy */
2393 * nand_sync - [MTD Interface] sync
2394 * @mtd: MTD device structure
2396 * Sync is actually a wait for chip ready function
2398 static void nand_sync(struct mtd_info *mtd)
2400 struct nand_chip *chip = mtd->priv;
2402 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2404 /* Grab the lock and see if the device is available */
2405 nand_get_device(chip, mtd, FL_SYNCING);
2406 /* Release it and go back */
2407 nand_release_device(mtd);
2411 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2412 * @mtd: MTD device structure
2413 * @offs: offset relative to mtd start
2415 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2417 /* Check for invalid offset */
2418 if (offs > mtd->size)
2421 return nand_block_checkbad(mtd, offs, 1, 0);
2425 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2426 * @mtd: MTD device structure
2427 * @ofs: offset relative to mtd start
2429 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2431 struct nand_chip *chip = mtd->priv;
2434 ret = nand_block_isbad(mtd, ofs);
2436 /* If it was bad already, return success and do nothing. */
2442 return chip->block_markbad(mtd, ofs);
2446 * Set default functions
2448 static void nand_set_defaults(struct nand_chip *chip, int busw)
2450 /* check for proper chip_delay setup, set 20us if not */
2451 if (!chip->chip_delay)
2452 chip->chip_delay = 20;
2454 /* check, if a user supplied command function given */
2455 if (chip->cmdfunc == NULL)
2456 chip->cmdfunc = nand_command;
2458 /* check, if a user supplied wait function given */
2459 if (chip->waitfunc == NULL)
2460 chip->waitfunc = nand_wait;
2462 if (!chip->select_chip)
2463 chip->select_chip = nand_select_chip;
2464 if (!chip->read_byte)
2465 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2466 if (!chip->read_word)
2467 chip->read_word = nand_read_word;
2468 if (!chip->block_bad)
2469 chip->block_bad = nand_block_bad;
2470 if (!chip->block_markbad)
2471 chip->block_markbad = nand_default_block_markbad;
2472 if (!chip->write_buf)
2473 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2474 if (!chip->read_buf)
2475 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2476 if (!chip->verify_buf)
2477 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2478 if (!chip->scan_bbt)
2479 chip->scan_bbt = nand_default_bbt;
2480 if (!chip->controller)
2481 chip->controller = &chip->hwcontrol;
2484 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2486 * sanitize ONFI strings so we can safely print them
2488 static void sanitize_string(char *s, size_t len)
2492 /* null terminate */
2495 /* remove non printable chars */
2496 for (i = 0; i < len - 1; i++) {
2497 if (s[i] < ' ' || s[i] > 127)
2501 /* remove trailing spaces */
2505 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2510 for (i = 0; i < 8; i++)
2511 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2518 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2520 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2523 struct nand_onfi_params *p = &chip->onfi_params;
2527 /* try ONFI for unknow chip or LP */
2528 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2529 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2530 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2533 printk(KERN_INFO "ONFI flash detected\n");
2534 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2535 for (i = 0; i < 3; i++) {
2536 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2537 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2538 le16_to_cpu(p->crc)) {
2539 printk(KERN_INFO "ONFI param page %d valid\n", i);
2548 val = le16_to_cpu(p->revision);
2550 chip->onfi_version = 23;
2551 else if (val & (1 << 4))
2552 chip->onfi_version = 22;
2553 else if (val & (1 << 3))
2554 chip->onfi_version = 21;
2555 else if (val & (1 << 2))
2556 chip->onfi_version = 20;
2557 else if (val & (1 << 1))
2558 chip->onfi_version = 10;
2560 chip->onfi_version = 0;
2562 if (!chip->onfi_version) {
2563 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2568 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2569 sanitize_string(p->model, sizeof(p->model));
2571 mtd->name = p->model;
2572 mtd->writesize = le32_to_cpu(p->byte_per_page);
2573 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2574 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2575 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2577 if (le16_to_cpu(p->features) & 1)
2578 *busw = NAND_BUSWIDTH_16;
2580 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2581 chip->options |= (NAND_NO_READRDY |
2582 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2587 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2588 struct nand_chip *chip,
2596 * Get the flash and manufacturer id and lookup if the type is supported
2598 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2599 struct nand_chip *chip,
2601 int *maf_id, int *dev_id,
2602 const struct nand_flash_dev *type)
2608 /* Select the device */
2609 chip->select_chip(mtd, 0);
2612 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2615 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2617 /* Send the command for reading device ID */
2618 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2620 /* Read manufacturer and device IDs */
2621 *maf_id = chip->read_byte(mtd);
2622 *dev_id = chip->read_byte(mtd);
2624 /* Try again to make sure, as some systems the bus-hold or other
2625 * interface concerns can cause random data which looks like a
2626 * possibly credible NAND flash to appear. If the two results do
2627 * not match, ignore the device completely.
2630 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2632 for (i = 0; i < 2; i++)
2633 id_data[i] = chip->read_byte(mtd);
2635 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2636 printk(KERN_INFO "%s: second ID read did not match "
2637 "%02x,%02x against %02x,%02x\n", __func__,
2638 *maf_id, *dev_id, id_data[0], id_data[1]);
2639 return ERR_PTR(-ENODEV);
2643 type = nand_flash_ids;
2645 for (; type->name != NULL; type++)
2646 if (*dev_id == type->id)
2649 chip->onfi_version = 0;
2650 if (!type->name || !type->pagesize) {
2651 /* Check is chip is ONFI compliant */
2652 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2657 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2659 /* Read entire ID string */
2661 for (i = 0; i < 8; i++)
2662 id_data[i] = chip->read_byte(mtd);
2665 return ERR_PTR(-ENODEV);
2668 mtd->name = type->name;
2670 chip->chipsize = (uint64_t)type->chipsize << 20;
2672 if (!type->pagesize && chip->init_size) {
2673 /* set the pagesize, oobsize, erasesize by the driver*/
2674 busw = chip->init_size(mtd, chip, id_data);
2675 } else if (!type->pagesize) {
2677 /* The 3rd id byte holds MLC / multichip data */
2678 chip->cellinfo = id_data[2];
2679 /* The 4th id byte is the important one */
2683 * Field definitions are in the following datasheets:
2684 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2685 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
2687 * Check for wraparound + Samsung ID + nonzero 6th byte
2688 * to decide what to do.
2690 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2691 id_data[0] == NAND_MFR_SAMSUNG &&
2692 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2693 id_data[5] != 0x00) {
2695 mtd->writesize = 2048 << (extid & 0x03);
2698 switch (extid & 0x03) {
2713 /* Calc blocksize */
2714 mtd->erasesize = (128 * 1024) <<
2715 (((extid >> 1) & 0x04) | (extid & 0x03));
2719 mtd->writesize = 1024 << (extid & 0x03);
2722 mtd->oobsize = (8 << (extid & 0x01)) *
2723 (mtd->writesize >> 9);
2725 /* Calc blocksize. Blocksize is multiples of 64KiB */
2726 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2728 /* Get buswidth information */
2729 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2733 * Old devices have chip data hardcoded in the device id table
2735 mtd->erasesize = type->erasesize;
2736 mtd->writesize = type->pagesize;
2737 mtd->oobsize = mtd->writesize / 32;
2738 busw = type->options & NAND_BUSWIDTH_16;
2741 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
2742 * some Spansion chips have erasesize that conflicts with size
2743 * listed in nand_ids table
2744 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
2746 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
2747 id_data[5] == 0x00 && id_data[6] == 0x00 &&
2748 id_data[7] == 0x00 && mtd->writesize == 512) {
2749 mtd->erasesize = 128 * 1024;
2750 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
2753 /* Get chip options, preserve non chip based options */
2754 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2755 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2757 /* Check if chip is a not a samsung device. Do not clear the
2758 * options for chips which are not having an extended id.
2760 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2761 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2765 * Set chip as a default. Board drivers can override it, if necessary
2767 chip->options |= NAND_NO_AUTOINCR;
2769 /* Try to identify manufacturer */
2770 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2771 if (nand_manuf_ids[maf_idx].id == *maf_id)
2776 * Check, if buswidth is correct. Hardware drivers should set
2779 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2780 printk(KERN_INFO "NAND device: Manufacturer ID:"
2781 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2782 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2783 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2784 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2786 return ERR_PTR(-EINVAL);
2789 /* Calculate the address shift from the page size */
2790 chip->page_shift = ffs(mtd->writesize) - 1;
2791 /* Convert chipsize to number of pages per chip -1. */
2792 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2794 chip->bbt_erase_shift = chip->phys_erase_shift =
2795 ffs(mtd->erasesize) - 1;
2796 if (chip->chipsize & 0xffffffff)
2797 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2799 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
2800 chip->chip_shift += 32 - 1;
2803 chip->badblockbits = 8;
2805 /* Set the bad block position */
2806 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
2807 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
2809 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
2812 * Bad block marker is stored in the last page of each block
2813 * on Samsung and Hynix MLC devices; stored in first two pages
2814 * of each block on Micron devices with 2KiB pages and on
2815 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
2816 * only the first page.
2818 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2819 (*maf_id == NAND_MFR_SAMSUNG ||
2820 *maf_id == NAND_MFR_HYNIX))
2821 chip->options |= NAND_BBT_SCANLASTPAGE;
2822 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2823 (*maf_id == NAND_MFR_SAMSUNG ||
2824 *maf_id == NAND_MFR_HYNIX ||
2825 *maf_id == NAND_MFR_TOSHIBA ||
2826 *maf_id == NAND_MFR_AMD)) ||
2827 (mtd->writesize == 2048 &&
2828 *maf_id == NAND_MFR_MICRON))
2829 chip->options |= NAND_BBT_SCAN2NDPAGE;
2832 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
2834 if (!(busw & NAND_BUSWIDTH_16) &&
2835 *maf_id == NAND_MFR_STMICRO &&
2836 mtd->writesize == 2048) {
2837 chip->options |= NAND_BBT_SCANBYTE1AND6;
2838 chip->badblockpos = 0;
2841 /* Check for AND chips with 4 page planes */
2842 if (chip->options & NAND_4PAGE_ARRAY)
2843 chip->erase_cmd = multi_erase_cmd;
2845 chip->erase_cmd = single_erase_cmd;
2847 /* Do not replace user supplied command function ! */
2848 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2849 chip->cmdfunc = nand_command_lp;
2851 /* TODO onfi flash name */
2852 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2853 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
2854 nand_manuf_ids[maf_idx].name,
2855 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2856 chip->onfi_version ? chip->onfi_params.model : type->name);
2865 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2866 * @mtd: MTD device structure
2867 * @maxchips: Number of chips to scan for
2868 * @table: Alternative NAND ID table
2870 * This is the first phase of the normal nand_scan() function. It
2871 * reads the flash ID and sets up MTD fields accordingly.
2873 * The mtd->owner field must be set to the module of the caller.
2875 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2876 const struct nand_flash_dev *table)
2878 int i, busw, nand_maf_id, nand_dev_id;
2879 struct nand_chip *chip = mtd->priv;
2880 const struct nand_flash_dev *type;
2882 /* Get buswidth to select the correct functions */
2883 busw = chip->options & NAND_BUSWIDTH_16;
2884 /* Set the default functions */
2885 nand_set_defaults(chip, busw);
2887 /* Read the flash type */
2888 type = nand_get_flash_type(mtd, chip, busw,
2889 &nand_maf_id, &nand_dev_id, table);
2892 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2893 printk(KERN_WARNING "No NAND device found!!!\n");
2895 chip->select_chip(mtd, -1);
2896 return PTR_ERR(type);
2899 /* Check for a chip array */
2900 for (i = 1; i < maxchips; i++) {
2901 chip->select_chip(mtd, i);
2902 /* See comment in nand_get_flash_type for reset */
2903 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2904 /* Send the command for reading device ID */
2905 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2906 /* Read manufacturer and device IDs */
2907 if (nand_maf_id != chip->read_byte(mtd) ||
2908 nand_dev_id != chip->read_byte(mtd))
2913 printk(KERN_INFO "%d NAND chips detected\n", i);
2916 /* Store the number of chips and calc total size for mtd */
2918 mtd->size = i * chip->chipsize;
2925 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2926 * @mtd: MTD device structure
2928 * This is the second phase of the normal nand_scan() function. It
2929 * fills out all the uninitialized function pointers with the defaults
2930 * and scans for a bad block table if appropriate.
2932 int nand_scan_tail(struct mtd_info *mtd)
2935 struct nand_chip *chip = mtd->priv;
2937 if (!(chip->options & NAND_OWN_BUFFERS))
2938 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2942 /* Set the internal oob buffer location, just after the page data */
2943 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2946 * If no default placement scheme is given, select an appropriate one
2948 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
2949 switch (mtd->oobsize) {
2951 chip->ecc.layout = &nand_oob_8;
2954 chip->ecc.layout = &nand_oob_16;
2957 chip->ecc.layout = &nand_oob_64;
2960 chip->ecc.layout = &nand_oob_128;
2963 printk(KERN_WARNING "No oob scheme defined for "
2964 "oobsize %d\n", mtd->oobsize);
2968 if (!chip->write_page)
2969 chip->write_page = nand_write_page;
2972 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2973 * selected and we have 256 byte pagesize fallback to software ECC
2976 switch (chip->ecc.mode) {
2977 case NAND_ECC_HW_OOB_FIRST:
2978 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2979 if (!chip->ecc.calculate || !chip->ecc.correct ||
2981 printk(KERN_WARNING "No ECC functions supplied; "
2982 "Hardware ECC not possible\n");
2985 if (!chip->ecc.read_page)
2986 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2989 /* Use standard hwecc read page function ? */
2990 if (!chip->ecc.read_page)
2991 chip->ecc.read_page = nand_read_page_hwecc;
2992 if (!chip->ecc.write_page)
2993 chip->ecc.write_page = nand_write_page_hwecc;
2994 if (!chip->ecc.read_page_raw)
2995 chip->ecc.read_page_raw = nand_read_page_raw;
2996 if (!chip->ecc.write_page_raw)
2997 chip->ecc.write_page_raw = nand_write_page_raw;
2998 if (!chip->ecc.read_oob)
2999 chip->ecc.read_oob = nand_read_oob_std;
3000 if (!chip->ecc.write_oob)
3001 chip->ecc.write_oob = nand_write_oob_std;
3003 case NAND_ECC_HW_SYNDROME:
3004 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3005 !chip->ecc.hwctl) &&
3006 (!chip->ecc.read_page ||
3007 chip->ecc.read_page == nand_read_page_hwecc ||
3008 !chip->ecc.write_page ||
3009 chip->ecc.write_page == nand_write_page_hwecc)) {
3010 printk(KERN_WARNING "No ECC functions supplied; "
3011 "Hardware ECC not possible\n");
3014 /* Use standard syndrome read/write page function ? */
3015 if (!chip->ecc.read_page)
3016 chip->ecc.read_page = nand_read_page_syndrome;
3017 if (!chip->ecc.write_page)
3018 chip->ecc.write_page = nand_write_page_syndrome;
3019 if (!chip->ecc.read_page_raw)
3020 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3021 if (!chip->ecc.write_page_raw)
3022 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3023 if (!chip->ecc.read_oob)
3024 chip->ecc.read_oob = nand_read_oob_syndrome;
3025 if (!chip->ecc.write_oob)
3026 chip->ecc.write_oob = nand_write_oob_syndrome;
3028 if (mtd->writesize >= chip->ecc.size)
3030 printk(KERN_WARNING "%d byte HW ECC not possible on "
3031 "%d byte page size, fallback to SW ECC\n",
3032 chip->ecc.size, mtd->writesize);
3033 chip->ecc.mode = NAND_ECC_SOFT;
3036 chip->ecc.calculate = nand_calculate_ecc;
3037 chip->ecc.correct = nand_correct_data;
3038 chip->ecc.read_page = nand_read_page_swecc;
3039 chip->ecc.read_subpage = nand_read_subpage;
3040 chip->ecc.write_page = nand_write_page_swecc;
3041 chip->ecc.read_page_raw = nand_read_page_raw;
3042 chip->ecc.write_page_raw = nand_write_page_raw;
3043 chip->ecc.read_oob = nand_read_oob_std;
3044 chip->ecc.write_oob = nand_write_oob_std;
3045 if (!chip->ecc.size)
3046 chip->ecc.size = 256;
3047 chip->ecc.bytes = 3;
3050 case NAND_ECC_SOFT_BCH:
3051 if (!mtd_nand_has_bch()) {
3052 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3055 chip->ecc.calculate = nand_bch_calculate_ecc;
3056 chip->ecc.correct = nand_bch_correct_data;
3057 chip->ecc.read_page = nand_read_page_swecc;
3058 chip->ecc.read_subpage = nand_read_subpage;
3059 chip->ecc.write_page = nand_write_page_swecc;
3060 chip->ecc.read_page_raw = nand_read_page_raw;
3061 chip->ecc.write_page_raw = nand_write_page_raw;
3062 chip->ecc.read_oob = nand_read_oob_std;
3063 chip->ecc.write_oob = nand_write_oob_std;
3065 * Board driver should supply ecc.size and ecc.bytes values to
3066 * select how many bits are correctable; see nand_bch_init()
3068 * Otherwise, default to 4 bits for large page devices
3070 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3071 chip->ecc.size = 512;
3072 chip->ecc.bytes = 7;
3074 chip->ecc.priv = nand_bch_init(mtd,
3078 if (!chip->ecc.priv)
3079 printk(KERN_WARNING "BCH ECC initialization failed!\n");
3084 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3085 "This is not recommended !!\n");
3086 chip->ecc.read_page = nand_read_page_raw;
3087 chip->ecc.write_page = nand_write_page_raw;
3088 chip->ecc.read_oob = nand_read_oob_std;
3089 chip->ecc.read_page_raw = nand_read_page_raw;
3090 chip->ecc.write_page_raw = nand_write_page_raw;
3091 chip->ecc.write_oob = nand_write_oob_std;
3092 chip->ecc.size = mtd->writesize;
3093 chip->ecc.bytes = 0;
3097 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3103 * The number of bytes available for a client to place data into
3104 * the out of band area
3106 chip->ecc.layout->oobavail = 0;
3107 for (i = 0; chip->ecc.layout->oobfree[i].length
3108 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3109 chip->ecc.layout->oobavail +=
3110 chip->ecc.layout->oobfree[i].length;
3111 mtd->oobavail = chip->ecc.layout->oobavail;
3114 * Set the number of read / write steps for one page depending on ECC
3117 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3118 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3119 printk(KERN_WARNING "Invalid ecc parameters\n");
3122 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3125 * Allow subpage writes up to ecc.steps. Not possible for MLC
3128 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3129 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3130 switch (chip->ecc.steps) {
3132 mtd->subpage_sft = 1;
3137 mtd->subpage_sft = 2;
3141 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3143 /* Initialize state */
3144 chip->state = FL_READY;
3146 /* De-select the device */
3147 chip->select_chip(mtd, -1);
3149 /* Invalidate the pagebuffer reference */
3152 /* Fill in remaining MTD driver data */
3153 mtd->type = MTD_NANDFLASH;
3154 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3156 mtd->erase = nand_erase;
3158 mtd->unpoint = NULL;
3159 mtd->read = nand_read;
3160 mtd->write = nand_write;
3161 mtd->read_oob = nand_read_oob;
3162 mtd->write_oob = nand_write_oob;
3163 mtd->sync = nand_sync;
3166 mtd->block_isbad = nand_block_isbad;
3167 mtd->block_markbad = nand_block_markbad;
3169 /* propagate ecc.layout to mtd_info */
3170 mtd->ecclayout = chip->ecc.layout;
3172 /* Check, if we should skip the bad block table scan */
3173 if (chip->options & NAND_SKIP_BBTSCAN)
3174 chip->options |= NAND_BBT_SCANNED;
3180 * nand_scan - [NAND Interface] Scan for the NAND device
3181 * @mtd: MTD device structure
3182 * @maxchips: Number of chips to scan for
3184 * This fills out all the uninitialized function pointers
3185 * with the defaults.
3186 * The flash ID is read and the mtd/chip structures are
3187 * filled with the appropriate values.
3188 * The mtd->owner field must be set to the module of the caller
3191 int nand_scan(struct mtd_info *mtd, int maxchips)
3195 ret = nand_scan_ident(mtd, maxchips, NULL);
3197 ret = nand_scan_tail(mtd);
3202 * nand_release - [NAND Interface] Free resources held by the NAND device
3203 * @mtd: MTD device structure
3205 void nand_release(struct mtd_info *mtd)
3207 struct nand_chip *chip = mtd->priv;
3209 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3210 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3212 #ifdef CONFIG_MTD_PARTITIONS
3213 /* Deregister partitions */
3214 del_mtd_partitions(mtd);
3217 /* Free bad block table memory */
3219 if (!(chip->options & NAND_OWN_BUFFERS))
3220 kfree(chip->buffers);
3222 /* Free bad block descriptor memory */
3223 if (chip->badblock_pattern && chip->badblock_pattern->options
3224 & NAND_BBT_DYNAMICSTRUCT)
3225 kfree(chip->badblock_pattern);