3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #if CONFIG_IS_ENABLED(OF_CONTROL)
37 #include <linux/err.h>
38 #include <linux/compat.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #ifdef CONFIG_MTD_PARTITIONS
44 #include <linux/mtd/partitions.h>
47 #include <linux/errno.h>
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8 = {
60 static struct nand_ecclayout nand_oob_16 = {
62 .eccpos = {0, 1, 2, 3, 6, 7},
68 static struct nand_ecclayout nand_oob_64 = {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
79 static struct nand_ecclayout nand_oob_128 = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
93 static int nand_get_device(struct mtd_info *mtd, int new_state);
95 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
102 DEFINE_LED_TRIGGER(nand_led_trigger);
104 static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
107 struct nand_chip *chip = mtd_to_nand(mtd);
110 /* Start address must align on block boundary */
111 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__);
116 /* Length must align on block boundary */
117 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__);
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
129 * Release chip lock and wake up anyone waiting on the device.
131 static void nand_release_device(struct mtd_info *mtd)
133 struct nand_chip *chip = mtd_to_nand(mtd);
135 /* De-select the NAND device */
136 chip->select_chip(mtd, -1);
140 * nand_read_byte - [DEFAULT] read one byte from the chip
141 * @mtd: MTD device structure
143 * Default read function for 8bit buswidth
145 uint8_t nand_read_byte(struct mtd_info *mtd)
147 struct nand_chip *chip = mtd_to_nand(mtd);
148 return readb(chip->IO_ADDR_R);
152 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
153 * @mtd: MTD device structure
155 * Default read function for 16bit buswidth with endianness conversion.
158 static uint8_t nand_read_byte16(struct mtd_info *mtd)
160 struct nand_chip *chip = mtd_to_nand(mtd);
161 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
165 * nand_read_word - [DEFAULT] read one word from the chip
166 * @mtd: MTD device structure
168 * Default read function for 16bit buswidth without endianness conversion.
170 static u16 nand_read_word(struct mtd_info *mtd)
172 struct nand_chip *chip = mtd_to_nand(mtd);
173 return readw(chip->IO_ADDR_R);
177 * nand_select_chip - [DEFAULT] control CE line
178 * @mtd: MTD device structure
179 * @chipnr: chipnumber to select, -1 for deselect
181 * Default select function for 1 chip devices.
183 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
185 struct nand_chip *chip = mtd_to_nand(mtd);
189 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
200 * nand_write_byte - [DEFAULT] write single byte to chip
201 * @mtd: MTD device structure
202 * @byte: value to write
204 * Default function to write a byte to I/O[7:0]
206 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
208 struct nand_chip *chip = mtd_to_nand(mtd);
210 chip->write_buf(mtd, &byte, 1);
214 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
215 * @mtd: MTD device structure
216 * @byte: value to write
218 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
220 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
222 struct nand_chip *chip = mtd_to_nand(mtd);
223 uint16_t word = byte;
226 * It's not entirely clear what should happen to I/O[15:8] when writing
227 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
229 * When the host supports a 16-bit bus width, only data is
230 * transferred at the 16-bit width. All address and command line
231 * transfers shall use only the lower 8-bits of the data bus. During
232 * command transfers, the host may place any value on the upper
233 * 8-bits of the data bus. During address transfers, the host shall
234 * set the upper 8-bits of the data bus to 00h.
236 * One user of the write_byte callback is nand_onfi_set_features. The
237 * four parameters are specified to be written to I/O[7:0], but this is
238 * neither an address nor a command transfer. Let's assume a 0 on the
239 * upper I/O lines is OK.
241 chip->write_buf(mtd, (uint8_t *)&word, 2);
244 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
248 for (i = 0; i < len; i++)
249 writeb(buf[i], addr);
251 static void ioread8_rep(void *addr, uint8_t *buf, int len)
255 for (i = 0; i < len; i++)
256 buf[i] = readb(addr);
259 static void ioread16_rep(void *addr, void *buf, int len)
262 u16 *p = (u16 *) buf;
264 for (i = 0; i < len; i++)
268 static void iowrite16_rep(void *addr, void *buf, int len)
271 u16 *p = (u16 *) buf;
273 for (i = 0; i < len; i++)
278 * nand_write_buf - [DEFAULT] write buffer to chip
279 * @mtd: MTD device structure
281 * @len: number of bytes to write
283 * Default write function for 8bit buswidth.
285 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
287 struct nand_chip *chip = mtd_to_nand(mtd);
289 iowrite8_rep(chip->IO_ADDR_W, buf, len);
293 * nand_read_buf - [DEFAULT] read chip data into buffer
294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
298 * Default read function for 8bit buswidth.
300 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
302 struct nand_chip *chip = mtd_to_nand(mtd);
304 ioread8_rep(chip->IO_ADDR_R, buf, len);
308 * nand_write_buf16 - [DEFAULT] write buffer to chip
309 * @mtd: MTD device structure
311 * @len: number of bytes to write
313 * Default write function for 16bit buswidth.
315 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
317 struct nand_chip *chip = mtd_to_nand(mtd);
318 u16 *p = (u16 *) buf;
320 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
324 * nand_read_buf16 - [DEFAULT] read chip data into buffer
325 * @mtd: MTD device structure
326 * @buf: buffer to store date
327 * @len: number of bytes to read
329 * Default read function for 16bit buswidth.
331 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
333 struct nand_chip *chip = mtd_to_nand(mtd);
334 u16 *p = (u16 *) buf;
336 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
340 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
341 * @mtd: MTD device structure
342 * @ofs: offset from device start
344 * Check, if the block is bad.
346 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
348 int page, res = 0, i = 0;
349 struct nand_chip *chip = mtd_to_nand(mtd);
352 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
353 ofs += mtd->erasesize - mtd->writesize;
355 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
358 if (chip->options & NAND_BUSWIDTH_16) {
359 chip->cmdfunc(mtd, NAND_CMD_READOOB,
360 chip->badblockpos & 0xFE, page);
361 bad = cpu_to_le16(chip->read_word(mtd));
362 if (chip->badblockpos & 0x1)
367 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
369 bad = chip->read_byte(mtd);
372 if (likely(chip->badblockbits == 8))
375 res = hweight8(bad) < chip->badblockbits;
376 ofs += mtd->writesize;
377 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
379 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
385 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
386 * @mtd: MTD device structure
387 * @ofs: offset from device start
389 * This is the default implementation, which can be overridden by a hardware
390 * specific driver. It provides the details for writing a bad block marker to a
393 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
395 struct nand_chip *chip = mtd_to_nand(mtd);
396 struct mtd_oob_ops ops;
397 uint8_t buf[2] = { 0, 0 };
398 int ret = 0, res, i = 0;
400 memset(&ops, 0, sizeof(ops));
402 ops.ooboffs = chip->badblockpos;
403 if (chip->options & NAND_BUSWIDTH_16) {
404 ops.ooboffs &= ~0x01;
405 ops.len = ops.ooblen = 2;
407 ops.len = ops.ooblen = 1;
409 ops.mode = MTD_OPS_PLACE_OOB;
411 /* Write to first/last page(s) if necessary */
412 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
413 ofs += mtd->erasesize - mtd->writesize;
415 res = nand_do_write_oob(mtd, ofs, &ops);
420 ofs += mtd->writesize;
421 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
427 * nand_block_markbad_lowlevel - mark a block bad
428 * @mtd: MTD device structure
429 * @ofs: offset from device start
431 * This function performs the generic NAND bad block marking steps (i.e., bad
432 * block table(s) and/or marker(s)). We only allow the hardware driver to
433 * specify how to write bad block markers to OOB (chip->block_markbad).
435 * We try operations in the following order:
436 * (1) erase the affected block, to allow OOB marker to be written cleanly
437 * (2) write bad block marker to OOB area of affected block (unless flag
438 * NAND_BBT_NO_OOB_BBM is present)
440 * Note that we retain the first error encountered in (2) or (3), finish the
441 * procedures, and dump the error in the end.
443 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
445 struct nand_chip *chip = mtd_to_nand(mtd);
448 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
449 struct erase_info einfo;
451 /* Attempt erase before marking OOB */
452 memset(&einfo, 0, sizeof(einfo));
455 einfo.len = 1ULL << chip->phys_erase_shift;
456 nand_erase_nand(mtd, &einfo, 0);
458 /* Write bad block marker to OOB */
459 nand_get_device(mtd, FL_WRITING);
460 ret = chip->block_markbad(mtd, ofs);
461 nand_release_device(mtd);
464 /* Mark block bad in BBT */
466 res = nand_markbad_bbt(mtd, ofs);
472 mtd->ecc_stats.badblocks++;
478 * nand_check_wp - [GENERIC] check if the chip is write protected
479 * @mtd: MTD device structure
481 * Check, if the device is write protected. The function expects, that the
482 * device is already selected.
484 static int nand_check_wp(struct mtd_info *mtd)
486 struct nand_chip *chip = mtd_to_nand(mtd);
488 /* Broken xD cards report WP despite being writable */
489 if (chip->options & NAND_BROKEN_XD)
492 /* Check the WP bit */
493 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
494 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
498 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
499 * @mtd: MTD device structure
500 * @ofs: offset from device start
502 * Check if the block is marked as reserved.
504 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
506 struct nand_chip *chip = mtd_to_nand(mtd);
510 /* Return info from the table */
511 return nand_isreserved_bbt(mtd, ofs);
515 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
516 * @mtd: MTD device structure
517 * @ofs: offset from device start
518 * @allowbbt: 1, if its allowed to access the bbt area
520 * Check, if the block is bad. Either by reading the bad block table or
521 * calling of the scan function.
523 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
525 struct nand_chip *chip = mtd_to_nand(mtd);
527 if (!(chip->options & NAND_SKIP_BBTSCAN) &&
528 !(chip->options & NAND_BBT_SCANNED)) {
529 chip->options |= NAND_BBT_SCANNED;
534 return chip->block_bad(mtd, ofs);
536 /* Return info from the table */
537 return nand_isbad_bbt(mtd, ofs, allowbbt);
541 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
542 * @mtd: MTD device structure
544 * Wait for the ready pin after a command, and warn if a timeout occurs.
546 void nand_wait_ready(struct mtd_info *mtd)
548 struct nand_chip *chip = mtd_to_nand(mtd);
549 u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
552 time_start = get_timer(0);
553 /* Wait until command is processed or timeout occurs */
554 while (get_timer(time_start) < timeo) {
556 if (chip->dev_ready(mtd))
560 if (!chip->dev_ready(mtd))
561 pr_warn("timeout while waiting for chip to become ready\n");
563 EXPORT_SYMBOL_GPL(nand_wait_ready);
566 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
567 * @mtd: MTD device structure
568 * @timeo: Timeout in ms
570 * Wait for status ready (i.e. command done) or timeout.
572 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
574 register struct nand_chip *chip = mtd_to_nand(mtd);
577 timeo = (CONFIG_SYS_HZ * timeo) / 1000;
578 time_start = get_timer(0);
579 while (get_timer(time_start) < timeo) {
580 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
587 * nand_command - [DEFAULT] Send command to NAND device
588 * @mtd: MTD device structure
589 * @command: the command to be sent
590 * @column: the column address for this command, -1 if none
591 * @page_addr: the page address for this command, -1 if none
593 * Send command to NAND device. This function is used for small page devices
594 * (512 Bytes per page).
596 static void nand_command(struct mtd_info *mtd, unsigned int command,
597 int column, int page_addr)
599 register struct nand_chip *chip = mtd_to_nand(mtd);
600 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
602 /* Write out the command to the device */
603 if (command == NAND_CMD_SEQIN) {
606 if (column >= mtd->writesize) {
608 column -= mtd->writesize;
609 readcmd = NAND_CMD_READOOB;
610 } else if (column < 256) {
611 /* First 256 bytes --> READ0 */
612 readcmd = NAND_CMD_READ0;
615 readcmd = NAND_CMD_READ1;
617 chip->cmd_ctrl(mtd, readcmd, ctrl);
618 ctrl &= ~NAND_CTRL_CHANGE;
620 chip->cmd_ctrl(mtd, command, ctrl);
622 /* Address cycle, when necessary */
623 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
624 /* Serially input address */
626 /* Adjust columns for 16 bit buswidth */
627 if (chip->options & NAND_BUSWIDTH_16 &&
628 !nand_opcode_8bits(command))
630 chip->cmd_ctrl(mtd, column, ctrl);
631 ctrl &= ~NAND_CTRL_CHANGE;
633 if (page_addr != -1) {
634 chip->cmd_ctrl(mtd, page_addr, ctrl);
635 ctrl &= ~NAND_CTRL_CHANGE;
636 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
637 /* One more address cycle for devices > 32MiB */
638 if (chip->chipsize > (32 << 20))
639 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
641 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
644 * Program and erase have their own busy handlers status and sequential
649 case NAND_CMD_PAGEPROG:
650 case NAND_CMD_ERASE1:
651 case NAND_CMD_ERASE2:
653 case NAND_CMD_STATUS:
654 case NAND_CMD_READID:
655 case NAND_CMD_SET_FEATURES:
661 udelay(chip->chip_delay);
662 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
663 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
665 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
666 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
667 nand_wait_status_ready(mtd, 250);
670 /* This applies to read commands */
673 * If we don't have access to the busy pin, we apply the given
676 if (!chip->dev_ready) {
677 udelay(chip->chip_delay);
682 * Apply this short delay always to ensure that we do wait tWB in
683 * any case on any machine.
687 nand_wait_ready(mtd);
691 * nand_command_lp - [DEFAULT] Send command to NAND large page device
692 * @mtd: MTD device structure
693 * @command: the command to be sent
694 * @column: the column address for this command, -1 if none
695 * @page_addr: the page address for this command, -1 if none
697 * Send command to NAND device. This is the version for the new large page
698 * devices. We don't have the separate regions as we have in the small page
699 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
701 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
702 int column, int page_addr)
704 register struct nand_chip *chip = mtd_to_nand(mtd);
706 /* Emulate NAND_CMD_READOOB */
707 if (command == NAND_CMD_READOOB) {
708 column += mtd->writesize;
709 command = NAND_CMD_READ0;
712 /* Command latch cycle */
713 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
715 if (column != -1 || page_addr != -1) {
716 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
718 /* Serially input address */
720 /* Adjust columns for 16 bit buswidth */
721 if (chip->options & NAND_BUSWIDTH_16 &&
722 !nand_opcode_8bits(command))
724 chip->cmd_ctrl(mtd, column, ctrl);
725 ctrl &= ~NAND_CTRL_CHANGE;
726 chip->cmd_ctrl(mtd, column >> 8, ctrl);
728 if (page_addr != -1) {
729 chip->cmd_ctrl(mtd, page_addr, ctrl);
730 chip->cmd_ctrl(mtd, page_addr >> 8,
731 NAND_NCE | NAND_ALE);
732 /* One more address cycle for devices > 128MiB */
733 if (chip->chipsize > (128 << 20))
734 chip->cmd_ctrl(mtd, page_addr >> 16,
735 NAND_NCE | NAND_ALE);
738 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
741 * Program and erase have their own busy handlers status, sequential
742 * in and status need no delay.
746 case NAND_CMD_CACHEDPROG:
747 case NAND_CMD_PAGEPROG:
748 case NAND_CMD_ERASE1:
749 case NAND_CMD_ERASE2:
752 case NAND_CMD_STATUS:
753 case NAND_CMD_READID:
754 case NAND_CMD_SET_FEATURES:
760 udelay(chip->chip_delay);
761 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
762 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
763 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
764 NAND_NCE | NAND_CTRL_CHANGE);
765 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
766 nand_wait_status_ready(mtd, 250);
769 case NAND_CMD_RNDOUT:
770 /* No ready / busy check necessary */
771 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
772 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
773 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
774 NAND_NCE | NAND_CTRL_CHANGE);
778 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
779 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
780 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
781 NAND_NCE | NAND_CTRL_CHANGE);
783 /* This applies to read commands */
786 * If we don't have access to the busy pin, we apply the given
789 if (!chip->dev_ready) {
790 udelay(chip->chip_delay);
796 * Apply this short delay always to ensure that we do wait tWB in
797 * any case on any machine.
801 nand_wait_ready(mtd);
805 * panic_nand_get_device - [GENERIC] Get chip for selected access
806 * @chip: the nand chip descriptor
807 * @mtd: MTD device structure
808 * @new_state: the state which is requested
810 * Used when in panic, no locks are taken.
812 static void panic_nand_get_device(struct nand_chip *chip,
813 struct mtd_info *mtd, int new_state)
815 /* Hardware controller shared among independent devices */
816 chip->controller->active = chip;
817 chip->state = new_state;
821 * nand_get_device - [GENERIC] Get chip for selected access
822 * @mtd: MTD device structure
823 * @new_state: the state which is requested
825 * Get the device and lock it for exclusive access
828 nand_get_device(struct mtd_info *mtd, int new_state)
830 struct nand_chip *chip = mtd_to_nand(mtd);
831 chip->state = new_state;
836 * panic_nand_wait - [GENERIC] wait until the command is done
837 * @mtd: MTD device structure
838 * @chip: NAND chip structure
841 * Wait for command done. This is a helper function for nand_wait used when
842 * we are in interrupt context. May happen when in panic and trying to write
843 * an oops through mtdoops.
845 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
849 for (i = 0; i < timeo; i++) {
850 if (chip->dev_ready) {
851 if (chip->dev_ready(mtd))
854 if (chip->read_byte(mtd) & NAND_STATUS_READY)
862 * nand_wait - [DEFAULT] wait until the command is done
863 * @mtd: MTD device structure
864 * @chip: NAND chip structure
866 * Wait for command done. This applies to erase and program only.
868 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
871 unsigned long timeo = 400;
873 led_trigger_event(nand_led_trigger, LED_FULL);
876 * Apply this short delay always to ensure that we do wait tWB in any
877 * case on any machine.
881 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
883 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
886 time_start = get_timer(0);
887 while (get_timer(time_start) < timer) {
888 if (chip->dev_ready) {
889 if (chip->dev_ready(mtd))
892 if (chip->read_byte(mtd) & NAND_STATUS_READY)
896 led_trigger_event(nand_led_trigger, LED_OFF);
898 status = (int)chip->read_byte(mtd);
899 /* This can happen if in case of timeout or buggy dev_ready */
900 WARN_ON(!(status & NAND_STATUS_READY));
905 * nand_reset_data_interface - Reset data interface and timings
906 * @chip: The NAND chip
908 * Reset the Data interface and timings to ONFI mode 0.
910 * Returns 0 for success or negative error code otherwise.
912 static int nand_reset_data_interface(struct nand_chip *chip)
914 struct mtd_info *mtd = nand_to_mtd(chip);
915 const struct nand_data_interface *conf;
918 if (!chip->setup_data_interface)
922 * The ONFI specification says:
924 * To transition from NV-DDR or NV-DDR2 to the SDR data
925 * interface, the host shall use the Reset (FFh) command
926 * using SDR timing mode 0. A device in any timing mode is
927 * required to recognize Reset (FFh) command issued in SDR
931 * Configure the data interface in SDR mode and set the
932 * timings to timing mode 0.
935 conf = nand_get_default_data_interface();
936 ret = chip->setup_data_interface(mtd, conf, false);
938 pr_err("Failed to configure data interface to SDR timing mode 0\n");
944 * nand_setup_data_interface - Setup the best data interface and timings
945 * @chip: The NAND chip
947 * Find and configure the best data interface and NAND timings supported by
948 * the chip and the driver.
949 * First tries to retrieve supported timing modes from ONFI information,
950 * and if the NAND chip does not support ONFI, relies on the
951 * ->onfi_timing_mode_default specified in the nand_ids table.
953 * Returns 0 for success or negative error code otherwise.
955 static int nand_setup_data_interface(struct nand_chip *chip)
957 struct mtd_info *mtd = nand_to_mtd(chip);
960 if (!chip->setup_data_interface || !chip->data_interface)
964 * Ensure the timing mode has been changed on the chip side
965 * before changing timings on the controller side.
967 if (chip->onfi_version) {
968 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
969 chip->onfi_timing_mode_default,
972 ret = chip->onfi_set_features(mtd, chip,
973 ONFI_FEATURE_ADDR_TIMING_MODE,
979 ret = chip->setup_data_interface(mtd, chip->data_interface, false);
985 * nand_init_data_interface - find the best data interface and timings
986 * @chip: The NAND chip
988 * Find the best data interface and NAND timings supported by the chip
990 * First tries to retrieve supported timing modes from ONFI information,
991 * and if the NAND chip does not support ONFI, relies on the
992 * ->onfi_timing_mode_default specified in the nand_ids table. After this
993 * function nand_chip->data_interface is initialized with the best timing mode
996 * Returns 0 for success or negative error code otherwise.
998 static int nand_init_data_interface(struct nand_chip *chip)
1000 struct mtd_info *mtd = nand_to_mtd(chip);
1001 int modes, mode, ret;
1003 if (!chip->setup_data_interface)
1007 * First try to identify the best timings from ONFI parameters and
1008 * if the NAND does not support ONFI, fallback to the default ONFI
1011 modes = onfi_get_async_timing_mode(chip);
1012 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1013 if (!chip->onfi_timing_mode_default)
1016 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1019 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1021 if (!chip->data_interface)
1024 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1025 ret = onfi_init_data_interface(chip, chip->data_interface,
1026 NAND_SDR_IFACE, mode);
1030 ret = chip->setup_data_interface(mtd, chip->data_interface,
1033 chip->onfi_timing_mode_default = mode;
1041 static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
1043 kfree(chip->data_interface);
1047 * nand_reset - Reset and initialize a NAND device
1048 * @chip: The NAND chip
1049 * @chipnr: Internal die id
1051 * Returns 0 for success or negative error code otherwise
1053 int nand_reset(struct nand_chip *chip, int chipnr)
1055 struct mtd_info *mtd = nand_to_mtd(chip);
1058 ret = nand_reset_data_interface(chip);
1063 * The CS line has to be released before we can apply the new NAND
1064 * interface settings, hence this weird ->select_chip() dance.
1066 chip->select_chip(mtd, chipnr);
1067 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1068 chip->select_chip(mtd, -1);
1070 chip->select_chip(mtd, chipnr);
1071 ret = nand_setup_data_interface(chip);
1072 chip->select_chip(mtd, -1);
1080 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1081 * @buf: buffer to test
1082 * @len: buffer length
1083 * @bitflips_threshold: maximum number of bitflips
1085 * Check if a buffer contains only 0xff, which means the underlying region
1086 * has been erased and is ready to be programmed.
1087 * The bitflips_threshold specify the maximum number of bitflips before
1088 * considering the region is not erased.
1089 * Note: The logic of this function has been extracted from the memweight
1090 * implementation, except that nand_check_erased_buf function exit before
1091 * testing the whole buffer if the number of bitflips exceed the
1092 * bitflips_threshold value.
1094 * Returns a positive number of bitflips less than or equal to
1095 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1098 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1100 const unsigned char *bitmap = buf;
1104 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1106 weight = hweight8(*bitmap);
1107 bitflips += BITS_PER_BYTE - weight;
1108 if (unlikely(bitflips > bitflips_threshold))
1112 for (; len >= 4; len -= 4, bitmap += 4) {
1113 weight = hweight32(*((u32 *)bitmap));
1114 bitflips += 32 - weight;
1115 if (unlikely(bitflips > bitflips_threshold))
1119 for (; len > 0; len--, bitmap++) {
1120 weight = hweight8(*bitmap);
1121 bitflips += BITS_PER_BYTE - weight;
1122 if (unlikely(bitflips > bitflips_threshold))
1130 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1132 * @data: data buffer to test
1133 * @datalen: data length
1135 * @ecclen: ECC length
1136 * @extraoob: extra OOB buffer
1137 * @extraooblen: extra OOB length
1138 * @bitflips_threshold: maximum number of bitflips
1140 * Check if a data buffer and its associated ECC and OOB data contains only
1141 * 0xff pattern, which means the underlying region has been erased and is
1142 * ready to be programmed.
1143 * The bitflips_threshold specify the maximum number of bitflips before
1144 * considering the region as not erased.
1147 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1148 * different from the NAND page size. When fixing bitflips, ECC engines will
1149 * report the number of errors per chunk, and the NAND core infrastructure
1150 * expect you to return the maximum number of bitflips for the whole page.
1151 * This is why you should always use this function on a single chunk and
1152 * not on the whole page. After checking each chunk you should update your
1153 * max_bitflips value accordingly.
1154 * 2/ When checking for bitflips in erased pages you should not only check
1155 * the payload data but also their associated ECC data, because a user might
1156 * have programmed almost all bits to 1 but a few. In this case, we
1157 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1159 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1160 * data are protected by the ECC engine.
1161 * It could also be used if you support subpages and want to attach some
1162 * extra OOB data to an ECC chunk.
1164 * Returns a positive number of bitflips less than or equal to
1165 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1166 * threshold. In case of success, the passed buffers are filled with 0xff.
1168 int nand_check_erased_ecc_chunk(void *data, int datalen,
1169 void *ecc, int ecclen,
1170 void *extraoob, int extraooblen,
1171 int bitflips_threshold)
1173 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1175 data_bitflips = nand_check_erased_buf(data, datalen,
1176 bitflips_threshold);
1177 if (data_bitflips < 0)
1178 return data_bitflips;
1180 bitflips_threshold -= data_bitflips;
1182 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1183 if (ecc_bitflips < 0)
1184 return ecc_bitflips;
1186 bitflips_threshold -= ecc_bitflips;
1188 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1189 bitflips_threshold);
1190 if (extraoob_bitflips < 0)
1191 return extraoob_bitflips;
1194 memset(data, 0xff, datalen);
1197 memset(ecc, 0xff, ecclen);
1199 if (extraoob_bitflips)
1200 memset(extraoob, 0xff, extraooblen);
1202 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1204 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1207 * nand_read_page_raw - [INTERN] read raw page data without ecc
1208 * @mtd: mtd info structure
1209 * @chip: nand chip info structure
1210 * @buf: buffer to store read data
1211 * @oob_required: caller requires OOB data read to chip->oob_poi
1212 * @page: page number to read
1214 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1216 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1217 uint8_t *buf, int oob_required, int page)
1219 chip->read_buf(mtd, buf, mtd->writesize);
1221 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1226 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1227 * @mtd: mtd info structure
1228 * @chip: nand chip info structure
1229 * @buf: buffer to store read data
1230 * @oob_required: caller requires OOB data read to chip->oob_poi
1231 * @page: page number to read
1233 * We need a special oob layout and handling even when OOB isn't used.
1235 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1236 struct nand_chip *chip, uint8_t *buf,
1237 int oob_required, int page)
1239 int eccsize = chip->ecc.size;
1240 int eccbytes = chip->ecc.bytes;
1241 uint8_t *oob = chip->oob_poi;
1244 for (steps = chip->ecc.steps; steps > 0; steps--) {
1245 chip->read_buf(mtd, buf, eccsize);
1248 if (chip->ecc.prepad) {
1249 chip->read_buf(mtd, oob, chip->ecc.prepad);
1250 oob += chip->ecc.prepad;
1253 chip->read_buf(mtd, oob, eccbytes);
1256 if (chip->ecc.postpad) {
1257 chip->read_buf(mtd, oob, chip->ecc.postpad);
1258 oob += chip->ecc.postpad;
1262 size = mtd->oobsize - (oob - chip->oob_poi);
1264 chip->read_buf(mtd, oob, size);
1270 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1271 * @mtd: mtd info structure
1272 * @chip: nand chip info structure
1273 * @buf: buffer to store read data
1274 * @oob_required: caller requires OOB data read to chip->oob_poi
1275 * @page: page number to read
1277 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1278 uint8_t *buf, int oob_required, int page)
1280 int i, eccsize = chip->ecc.size;
1281 int eccbytes = chip->ecc.bytes;
1282 int eccsteps = chip->ecc.steps;
1284 uint8_t *ecc_calc = chip->buffers->ecccalc;
1285 uint8_t *ecc_code = chip->buffers->ecccode;
1286 uint32_t *eccpos = chip->ecc.layout->eccpos;
1287 unsigned int max_bitflips = 0;
1289 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1291 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1292 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1294 for (i = 0; i < chip->ecc.total; i++)
1295 ecc_code[i] = chip->oob_poi[eccpos[i]];
1297 eccsteps = chip->ecc.steps;
1300 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1303 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1305 mtd->ecc_stats.failed++;
1307 mtd->ecc_stats.corrected += stat;
1308 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1311 return max_bitflips;
1315 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1316 * @mtd: mtd info structure
1317 * @chip: nand chip info structure
1318 * @data_offs: offset of requested data within the page
1319 * @readlen: data length
1320 * @bufpoi: buffer to store read data
1321 * @page: page number to read
1323 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1324 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1327 int start_step, end_step, num_steps;
1328 uint32_t *eccpos = chip->ecc.layout->eccpos;
1330 int data_col_addr, i, gaps = 0;
1331 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1332 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1334 unsigned int max_bitflips = 0;
1336 /* Column address within the page aligned to ECC size (256bytes) */
1337 start_step = data_offs / chip->ecc.size;
1338 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1339 num_steps = end_step - start_step + 1;
1340 index = start_step * chip->ecc.bytes;
1342 /* Data size aligned to ECC ecc.size */
1343 datafrag_len = num_steps * chip->ecc.size;
1344 eccfrag_len = num_steps * chip->ecc.bytes;
1346 data_col_addr = start_step * chip->ecc.size;
1347 /* If we read not a page aligned data */
1348 if (data_col_addr != 0)
1349 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1351 p = bufpoi + data_col_addr;
1352 chip->read_buf(mtd, p, datafrag_len);
1355 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1356 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1359 * The performance is faster if we position offsets according to
1360 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1362 for (i = 0; i < eccfrag_len - 1; i++) {
1363 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1369 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1370 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1373 * Send the command to read the particular ECC bytes take care
1374 * about buswidth alignment in read_buf.
1376 aligned_pos = eccpos[index] & ~(busw - 1);
1377 aligned_len = eccfrag_len;
1378 if (eccpos[index] & (busw - 1))
1380 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1383 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1384 mtd->writesize + aligned_pos, -1);
1385 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1388 for (i = 0; i < eccfrag_len; i++)
1389 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1391 p = bufpoi + data_col_addr;
1392 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1395 stat = chip->ecc.correct(mtd, p,
1396 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1397 if (stat == -EBADMSG &&
1398 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1399 /* check for empty pages with bitflips */
1400 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1401 &chip->buffers->ecccode[i],
1404 chip->ecc.strength);
1408 mtd->ecc_stats.failed++;
1410 mtd->ecc_stats.corrected += stat;
1411 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1414 return max_bitflips;
1418 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1419 * @mtd: mtd info structure
1420 * @chip: nand chip info structure
1421 * @buf: buffer to store read data
1422 * @oob_required: caller requires OOB data read to chip->oob_poi
1423 * @page: page number to read
1425 * Not for syndrome calculating ECC controllers which need a special oob layout.
1427 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1428 uint8_t *buf, int oob_required, int page)
1430 int i, eccsize = chip->ecc.size;
1431 int eccbytes = chip->ecc.bytes;
1432 int eccsteps = chip->ecc.steps;
1434 uint8_t *ecc_calc = chip->buffers->ecccalc;
1435 uint8_t *ecc_code = chip->buffers->ecccode;
1436 uint32_t *eccpos = chip->ecc.layout->eccpos;
1437 unsigned int max_bitflips = 0;
1439 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1440 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1441 chip->read_buf(mtd, p, eccsize);
1442 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1444 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1446 for (i = 0; i < chip->ecc.total; i++)
1447 ecc_code[i] = chip->oob_poi[eccpos[i]];
1449 eccsteps = chip->ecc.steps;
1452 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1455 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1456 if (stat == -EBADMSG &&
1457 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1458 /* check for empty pages with bitflips */
1459 stat = nand_check_erased_ecc_chunk(p, eccsize,
1460 &ecc_code[i], eccbytes,
1462 chip->ecc.strength);
1466 mtd->ecc_stats.failed++;
1468 mtd->ecc_stats.corrected += stat;
1469 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1472 return max_bitflips;
1476 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1477 * @mtd: mtd info structure
1478 * @chip: nand chip info structure
1479 * @buf: buffer to store read data
1480 * @oob_required: caller requires OOB data read to chip->oob_poi
1481 * @page: page number to read
1483 * Hardware ECC for large page chips, require OOB to be read first. For this
1484 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1485 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1486 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1487 * the data area, by overwriting the NAND manufacturer bad block markings.
1489 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1490 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1492 int i, eccsize = chip->ecc.size;
1493 int eccbytes = chip->ecc.bytes;
1494 int eccsteps = chip->ecc.steps;
1496 uint8_t *ecc_code = chip->buffers->ecccode;
1497 uint32_t *eccpos = chip->ecc.layout->eccpos;
1498 uint8_t *ecc_calc = chip->buffers->ecccalc;
1499 unsigned int max_bitflips = 0;
1501 /* Read the OOB area first */
1502 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1503 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1504 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1506 for (i = 0; i < chip->ecc.total; i++)
1507 ecc_code[i] = chip->oob_poi[eccpos[i]];
1509 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1512 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1513 chip->read_buf(mtd, p, eccsize);
1514 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1516 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1517 if (stat == -EBADMSG &&
1518 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1519 /* check for empty pages with bitflips */
1520 stat = nand_check_erased_ecc_chunk(p, eccsize,
1521 &ecc_code[i], eccbytes,
1523 chip->ecc.strength);
1527 mtd->ecc_stats.failed++;
1529 mtd->ecc_stats.corrected += stat;
1530 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1533 return max_bitflips;
1537 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1538 * @mtd: mtd info structure
1539 * @chip: nand chip info structure
1540 * @buf: buffer to store read data
1541 * @oob_required: caller requires OOB data read to chip->oob_poi
1542 * @page: page number to read
1544 * The hw generator calculates the error syndrome automatically. Therefore we
1545 * need a special oob layout and handling.
1547 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1548 uint8_t *buf, int oob_required, int page)
1550 int i, eccsize = chip->ecc.size;
1551 int eccbytes = chip->ecc.bytes;
1552 int eccsteps = chip->ecc.steps;
1553 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
1555 uint8_t *oob = chip->oob_poi;
1556 unsigned int max_bitflips = 0;
1558 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1561 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1562 chip->read_buf(mtd, p, eccsize);
1564 if (chip->ecc.prepad) {
1565 chip->read_buf(mtd, oob, chip->ecc.prepad);
1566 oob += chip->ecc.prepad;
1569 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1570 chip->read_buf(mtd, oob, eccbytes);
1571 stat = chip->ecc.correct(mtd, p, oob, NULL);
1575 if (chip->ecc.postpad) {
1576 chip->read_buf(mtd, oob, chip->ecc.postpad);
1577 oob += chip->ecc.postpad;
1580 if (stat == -EBADMSG &&
1581 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1582 /* check for empty pages with bitflips */
1583 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1587 chip->ecc.strength);
1591 mtd->ecc_stats.failed++;
1593 mtd->ecc_stats.corrected += stat;
1594 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1598 /* Calculate remaining oob bytes */
1599 i = mtd->oobsize - (oob - chip->oob_poi);
1601 chip->read_buf(mtd, oob, i);
1603 return max_bitflips;
1607 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1608 * @chip: nand chip structure
1609 * @oob: oob destination address
1610 * @ops: oob ops structure
1611 * @len: size of oob to transfer
1613 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1614 struct mtd_oob_ops *ops, size_t len)
1616 switch (ops->mode) {
1618 case MTD_OPS_PLACE_OOB:
1620 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1623 case MTD_OPS_AUTO_OOB: {
1624 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1625 uint32_t boffs = 0, roffs = ops->ooboffs;
1628 for (; free->length && len; free++, len -= bytes) {
1629 /* Read request not from offset 0? */
1630 if (unlikely(roffs)) {
1631 if (roffs >= free->length) {
1632 roffs -= free->length;
1635 boffs = free->offset + roffs;
1636 bytes = min_t(size_t, len,
1637 (free->length - roffs));
1640 bytes = min_t(size_t, len, free->length);
1641 boffs = free->offset;
1643 memcpy(oob, chip->oob_poi + boffs, bytes);
1655 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1656 * @mtd: MTD device structure
1657 * @retry_mode: the retry mode to use
1659 * Some vendors supply a special command to shift the Vt threshold, to be used
1660 * when there are too many bitflips in a page (i.e., ECC error). After setting
1661 * a new threshold, the host should retry reading the page.
1663 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1665 struct nand_chip *chip = mtd_to_nand(mtd);
1667 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1669 if (retry_mode >= chip->read_retries)
1672 if (!chip->setup_read_retry)
1675 return chip->setup_read_retry(mtd, retry_mode);
1679 * nand_do_read_ops - [INTERN] Read data with ECC
1680 * @mtd: MTD device structure
1681 * @from: offset to read from
1682 * @ops: oob ops structure
1684 * Internal function. Called with chip held.
1686 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1687 struct mtd_oob_ops *ops)
1689 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1690 struct nand_chip *chip = mtd_to_nand(mtd);
1692 uint32_t readlen = ops->len;
1693 uint32_t oobreadlen = ops->ooblen;
1694 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
1696 uint8_t *bufpoi, *oob, *buf;
1698 unsigned int max_bitflips = 0;
1700 bool ecc_fail = false;
1702 chipnr = (int)(from >> chip->chip_shift);
1703 chip->select_chip(mtd, chipnr);
1705 realpage = (int)(from >> chip->page_shift);
1706 page = realpage & chip->pagemask;
1708 col = (int)(from & (mtd->writesize - 1));
1712 oob_required = oob ? 1 : 0;
1715 unsigned int ecc_failures = mtd->ecc_stats.failed;
1718 bytes = min(mtd->writesize - col, readlen);
1719 aligned = (bytes == mtd->writesize);
1726 /* Is the current page in the buffer? */
1727 if (realpage != chip->pagebuf || oob) {
1728 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1730 if (use_bufpoi && aligned)
1731 pr_debug("%s: using read bounce buffer for buf@%p\n",
1735 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1738 * Now read the page into the buffer. Absent an error,
1739 * the read methods return max bitflips per ecc step.
1741 if (unlikely(ops->mode == MTD_OPS_RAW))
1742 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1745 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1747 ret = chip->ecc.read_subpage(mtd, chip,
1751 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1752 oob_required, page);
1755 /* Invalidate page cache */
1760 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1762 /* Transfer not aligned data */
1764 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1765 !(mtd->ecc_stats.failed - ecc_failures) &&
1766 (ops->mode != MTD_OPS_RAW)) {
1767 chip->pagebuf = realpage;
1768 chip->pagebuf_bitflips = ret;
1770 /* Invalidate page cache */
1773 memcpy(buf, chip->buffers->databuf + col, bytes);
1776 if (unlikely(oob)) {
1777 int toread = min(oobreadlen, max_oobsize);
1780 oob = nand_transfer_oob(chip,
1782 oobreadlen -= toread;
1786 if (chip->options & NAND_NEED_READRDY) {
1787 /* Apply delay or wait for ready/busy pin */
1788 if (!chip->dev_ready)
1789 udelay(chip->chip_delay);
1791 nand_wait_ready(mtd);
1794 if (mtd->ecc_stats.failed - ecc_failures) {
1795 if (retry_mode + 1 < chip->read_retries) {
1797 ret = nand_setup_read_retry(mtd,
1802 /* Reset failures; retry */
1803 mtd->ecc_stats.failed = ecc_failures;
1806 /* No more retry modes; real failure */
1813 memcpy(buf, chip->buffers->databuf + col, bytes);
1815 max_bitflips = max_t(unsigned int, max_bitflips,
1816 chip->pagebuf_bitflips);
1821 /* Reset to retry mode 0 */
1823 ret = nand_setup_read_retry(mtd, 0);
1832 /* For subsequent reads align to page boundary */
1834 /* Increment page address */
1837 page = realpage & chip->pagemask;
1838 /* Check, if we cross a chip boundary */
1841 chip->select_chip(mtd, -1);
1842 chip->select_chip(mtd, chipnr);
1845 chip->select_chip(mtd, -1);
1847 ops->retlen = ops->len - (size_t) readlen;
1849 ops->oobretlen = ops->ooblen - oobreadlen;
1857 return max_bitflips;
1861 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1862 * @mtd: MTD device structure
1863 * @from: offset to read from
1864 * @len: number of bytes to read
1865 * @retlen: pointer to variable to store the number of read bytes
1866 * @buf: the databuffer to put data
1868 * Get hold of the chip and call nand_do_read.
1870 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1871 size_t *retlen, uint8_t *buf)
1873 struct mtd_oob_ops ops;
1876 nand_get_device(mtd, FL_READING);
1877 memset(&ops, 0, sizeof(ops));
1880 ops.mode = MTD_OPS_PLACE_OOB;
1881 ret = nand_do_read_ops(mtd, from, &ops);
1882 *retlen = ops.retlen;
1883 nand_release_device(mtd);
1888 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1889 * @mtd: mtd info structure
1890 * @chip: nand chip info structure
1891 * @page: page number to read
1893 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1896 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1897 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1902 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1904 * @mtd: mtd info structure
1905 * @chip: nand chip info structure
1906 * @page: page number to read
1908 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1911 int length = mtd->oobsize;
1912 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1913 int eccsize = chip->ecc.size;
1914 uint8_t *bufpoi = chip->oob_poi;
1915 int i, toread, sndrnd = 0, pos;
1917 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1918 for (i = 0; i < chip->ecc.steps; i++) {
1920 pos = eccsize + i * (eccsize + chunk);
1921 if (mtd->writesize > 512)
1922 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1924 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1927 toread = min_t(int, length, chunk);
1928 chip->read_buf(mtd, bufpoi, toread);
1933 chip->read_buf(mtd, bufpoi, length);
1939 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1940 * @mtd: mtd info structure
1941 * @chip: nand chip info structure
1942 * @page: page number to write
1944 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1948 const uint8_t *buf = chip->oob_poi;
1949 int length = mtd->oobsize;
1951 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1952 chip->write_buf(mtd, buf, length);
1953 /* Send command to program the OOB data */
1954 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1956 status = chip->waitfunc(mtd, chip);
1958 return status & NAND_STATUS_FAIL ? -EIO : 0;
1962 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1963 * with syndrome - only for large page flash
1964 * @mtd: mtd info structure
1965 * @chip: nand chip info structure
1966 * @page: page number to write
1968 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1969 struct nand_chip *chip, int page)
1971 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1972 int eccsize = chip->ecc.size, length = mtd->oobsize;
1973 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1974 const uint8_t *bufpoi = chip->oob_poi;
1977 * data-ecc-data-ecc ... ecc-oob
1979 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1981 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1982 pos = steps * (eccsize + chunk);
1987 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1988 for (i = 0; i < steps; i++) {
1990 if (mtd->writesize <= 512) {
1991 uint32_t fill = 0xFFFFFFFF;
1995 int num = min_t(int, len, 4);
1996 chip->write_buf(mtd, (uint8_t *)&fill,
2001 pos = eccsize + i * (eccsize + chunk);
2002 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2006 len = min_t(int, length, chunk);
2007 chip->write_buf(mtd, bufpoi, len);
2012 chip->write_buf(mtd, bufpoi, length);
2014 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2015 status = chip->waitfunc(mtd, chip);
2017 return status & NAND_STATUS_FAIL ? -EIO : 0;
2021 * nand_do_read_oob - [INTERN] NAND read out-of-band
2022 * @mtd: MTD device structure
2023 * @from: offset to read from
2024 * @ops: oob operations description structure
2026 * NAND read out-of-band data from the spare area.
2028 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2029 struct mtd_oob_ops *ops)
2031 int page, realpage, chipnr;
2032 struct nand_chip *chip = mtd_to_nand(mtd);
2033 struct mtd_ecc_stats stats;
2034 int readlen = ops->ooblen;
2036 uint8_t *buf = ops->oobbuf;
2039 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2040 __func__, (unsigned long long)from, readlen);
2042 stats = mtd->ecc_stats;
2044 len = mtd_oobavail(mtd, ops);
2046 if (unlikely(ops->ooboffs >= len)) {
2047 pr_debug("%s: attempt to start read outside oob\n",
2052 /* Do not allow reads past end of device */
2053 if (unlikely(from >= mtd->size ||
2054 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2055 (from >> chip->page_shift)) * len)) {
2056 pr_debug("%s: attempt to read beyond end of device\n",
2061 chipnr = (int)(from >> chip->chip_shift);
2062 chip->select_chip(mtd, chipnr);
2064 /* Shift to get page */
2065 realpage = (int)(from >> chip->page_shift);
2066 page = realpage & chip->pagemask;
2071 if (ops->mode == MTD_OPS_RAW)
2072 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2074 ret = chip->ecc.read_oob(mtd, chip, page);
2079 len = min(len, readlen);
2080 buf = nand_transfer_oob(chip, buf, ops, len);
2082 if (chip->options & NAND_NEED_READRDY) {
2083 /* Apply delay or wait for ready/busy pin */
2084 if (!chip->dev_ready)
2085 udelay(chip->chip_delay);
2087 nand_wait_ready(mtd);
2094 /* Increment page address */
2097 page = realpage & chip->pagemask;
2098 /* Check, if we cross a chip boundary */
2101 chip->select_chip(mtd, -1);
2102 chip->select_chip(mtd, chipnr);
2105 chip->select_chip(mtd, -1);
2107 ops->oobretlen = ops->ooblen - readlen;
2112 if (mtd->ecc_stats.failed - stats.failed)
2115 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2119 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2120 * @mtd: MTD device structure
2121 * @from: offset to read from
2122 * @ops: oob operation description structure
2124 * NAND read data and/or out-of-band data.
2126 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2127 struct mtd_oob_ops *ops)
2129 int ret = -ENOTSUPP;
2133 /* Do not allow reads past end of device */
2134 if (ops->datbuf && (from + ops->len) > mtd->size) {
2135 pr_debug("%s: attempt to read beyond end of device\n",
2140 nand_get_device(mtd, FL_READING);
2142 switch (ops->mode) {
2143 case MTD_OPS_PLACE_OOB:
2144 case MTD_OPS_AUTO_OOB:
2153 ret = nand_do_read_oob(mtd, from, ops);
2155 ret = nand_do_read_ops(mtd, from, ops);
2158 nand_release_device(mtd);
2164 * nand_write_page_raw - [INTERN] raw page write function
2165 * @mtd: mtd info structure
2166 * @chip: nand chip info structure
2168 * @oob_required: must write chip->oob_poi to OOB
2169 * @page: page number to write
2171 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2173 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2174 const uint8_t *buf, int oob_required, int page)
2176 chip->write_buf(mtd, buf, mtd->writesize);
2178 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2184 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2185 * @mtd: mtd info structure
2186 * @chip: nand chip info structure
2188 * @oob_required: must write chip->oob_poi to OOB
2189 * @page: page number to write
2191 * We need a special oob layout and handling even when ECC isn't checked.
2193 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2194 struct nand_chip *chip,
2195 const uint8_t *buf, int oob_required,
2198 int eccsize = chip->ecc.size;
2199 int eccbytes = chip->ecc.bytes;
2200 uint8_t *oob = chip->oob_poi;
2203 for (steps = chip->ecc.steps; steps > 0; steps--) {
2204 chip->write_buf(mtd, buf, eccsize);
2207 if (chip->ecc.prepad) {
2208 chip->write_buf(mtd, oob, chip->ecc.prepad);
2209 oob += chip->ecc.prepad;
2212 chip->write_buf(mtd, oob, eccbytes);
2215 if (chip->ecc.postpad) {
2216 chip->write_buf(mtd, oob, chip->ecc.postpad);
2217 oob += chip->ecc.postpad;
2221 size = mtd->oobsize - (oob - chip->oob_poi);
2223 chip->write_buf(mtd, oob, size);
2228 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2229 * @mtd: mtd info structure
2230 * @chip: nand chip info structure
2232 * @oob_required: must write chip->oob_poi to OOB
2233 * @page: page number to write
2235 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2236 const uint8_t *buf, int oob_required,
2239 int i, eccsize = chip->ecc.size;
2240 int eccbytes = chip->ecc.bytes;
2241 int eccsteps = chip->ecc.steps;
2242 uint8_t *ecc_calc = chip->buffers->ecccalc;
2243 const uint8_t *p = buf;
2244 uint32_t *eccpos = chip->ecc.layout->eccpos;
2246 /* Software ECC calculation */
2247 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2248 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2250 for (i = 0; i < chip->ecc.total; i++)
2251 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2253 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
2257 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2258 * @mtd: mtd info structure
2259 * @chip: nand chip info structure
2261 * @oob_required: must write chip->oob_poi to OOB
2262 * @page: page number to write
2264 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2265 const uint8_t *buf, int oob_required,
2268 int i, eccsize = chip->ecc.size;
2269 int eccbytes = chip->ecc.bytes;
2270 int eccsteps = chip->ecc.steps;
2271 uint8_t *ecc_calc = chip->buffers->ecccalc;
2272 const uint8_t *p = buf;
2273 uint32_t *eccpos = chip->ecc.layout->eccpos;
2275 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2276 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2277 chip->write_buf(mtd, p, eccsize);
2278 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2281 for (i = 0; i < chip->ecc.total; i++)
2282 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2284 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2291 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2292 * @mtd: mtd info structure
2293 * @chip: nand chip info structure
2294 * @offset: column address of subpage within the page
2295 * @data_len: data length
2297 * @oob_required: must write chip->oob_poi to OOB
2298 * @page: page number to write
2300 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2301 struct nand_chip *chip, uint32_t offset,
2302 uint32_t data_len, const uint8_t *buf,
2303 int oob_required, int page)
2305 uint8_t *oob_buf = chip->oob_poi;
2306 uint8_t *ecc_calc = chip->buffers->ecccalc;
2307 int ecc_size = chip->ecc.size;
2308 int ecc_bytes = chip->ecc.bytes;
2309 int ecc_steps = chip->ecc.steps;
2310 uint32_t *eccpos = chip->ecc.layout->eccpos;
2311 uint32_t start_step = offset / ecc_size;
2312 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2313 int oob_bytes = mtd->oobsize / ecc_steps;
2316 for (step = 0; step < ecc_steps; step++) {
2317 /* configure controller for WRITE access */
2318 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2320 /* write data (untouched subpages already masked by 0xFF) */
2321 chip->write_buf(mtd, buf, ecc_size);
2323 /* mask ECC of un-touched subpages by padding 0xFF */
2324 if ((step < start_step) || (step > end_step))
2325 memset(ecc_calc, 0xff, ecc_bytes);
2327 chip->ecc.calculate(mtd, buf, ecc_calc);
2329 /* mask OOB of un-touched subpages by padding 0xFF */
2330 /* if oob_required, preserve OOB metadata of written subpage */
2331 if (!oob_required || (step < start_step) || (step > end_step))
2332 memset(oob_buf, 0xff, oob_bytes);
2335 ecc_calc += ecc_bytes;
2336 oob_buf += oob_bytes;
2339 /* copy calculated ECC for whole page to chip->buffer->oob */
2340 /* this include masked-value(0xFF) for unwritten subpages */
2341 ecc_calc = chip->buffers->ecccalc;
2342 for (i = 0; i < chip->ecc.total; i++)
2343 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2345 /* write OOB buffer to NAND device */
2346 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2353 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2354 * @mtd: mtd info structure
2355 * @chip: nand chip info structure
2357 * @oob_required: must write chip->oob_poi to OOB
2358 * @page: page number to write
2360 * The hw generator calculates the error syndrome automatically. Therefore we
2361 * need a special oob layout and handling.
2363 static int nand_write_page_syndrome(struct mtd_info *mtd,
2364 struct nand_chip *chip,
2365 const uint8_t *buf, int oob_required,
2368 int i, eccsize = chip->ecc.size;
2369 int eccbytes = chip->ecc.bytes;
2370 int eccsteps = chip->ecc.steps;
2371 const uint8_t *p = buf;
2372 uint8_t *oob = chip->oob_poi;
2374 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2376 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2377 chip->write_buf(mtd, p, eccsize);
2379 if (chip->ecc.prepad) {
2380 chip->write_buf(mtd, oob, chip->ecc.prepad);
2381 oob += chip->ecc.prepad;
2384 chip->ecc.calculate(mtd, p, oob);
2385 chip->write_buf(mtd, oob, eccbytes);
2388 if (chip->ecc.postpad) {
2389 chip->write_buf(mtd, oob, chip->ecc.postpad);
2390 oob += chip->ecc.postpad;
2394 /* Calculate remaining oob bytes */
2395 i = mtd->oobsize - (oob - chip->oob_poi);
2397 chip->write_buf(mtd, oob, i);
2403 * nand_write_page - [REPLACEABLE] write one page
2404 * @mtd: MTD device structure
2405 * @chip: NAND chip descriptor
2406 * @offset: address offset within the page
2407 * @data_len: length of actual data to be written
2408 * @buf: the data to write
2409 * @oob_required: must write chip->oob_poi to OOB
2410 * @page: page number to write
2411 * @cached: cached programming
2412 * @raw: use _raw version of write_page
2414 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2415 uint32_t offset, int data_len, const uint8_t *buf,
2416 int oob_required, int page, int cached, int raw)
2418 int status, subpage;
2420 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2421 chip->ecc.write_subpage)
2422 subpage = offset || (data_len < mtd->writesize);
2426 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2429 status = chip->ecc.write_page_raw(mtd, chip, buf,
2430 oob_required, page);
2432 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2433 buf, oob_required, page);
2435 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2442 * Cached progamming disabled for now. Not sure if it's worth the
2443 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2447 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2449 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2450 status = chip->waitfunc(mtd, chip);
2452 * See if operation failed and additional status checks are
2455 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2456 status = chip->errstat(mtd, chip, FL_WRITING, status,
2459 if (status & NAND_STATUS_FAIL)
2462 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2463 status = chip->waitfunc(mtd, chip);
2470 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2471 * @mtd: MTD device structure
2472 * @oob: oob data buffer
2473 * @len: oob data write length
2474 * @ops: oob ops structure
2476 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2477 struct mtd_oob_ops *ops)
2479 struct nand_chip *chip = mtd_to_nand(mtd);
2482 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2483 * data from a previous OOB read.
2485 memset(chip->oob_poi, 0xff, mtd->oobsize);
2487 switch (ops->mode) {
2489 case MTD_OPS_PLACE_OOB:
2491 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2494 case MTD_OPS_AUTO_OOB: {
2495 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2496 uint32_t boffs = 0, woffs = ops->ooboffs;
2499 for (; free->length && len; free++, len -= bytes) {
2500 /* Write request not from offset 0? */
2501 if (unlikely(woffs)) {
2502 if (woffs >= free->length) {
2503 woffs -= free->length;
2506 boffs = free->offset + woffs;
2507 bytes = min_t(size_t, len,
2508 (free->length - woffs));
2511 bytes = min_t(size_t, len, free->length);
2512 boffs = free->offset;
2514 memcpy(chip->oob_poi + boffs, oob, bytes);
2525 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2528 * nand_do_write_ops - [INTERN] NAND write with ECC
2529 * @mtd: MTD device structure
2530 * @to: offset to write to
2531 * @ops: oob operations description structure
2533 * NAND write with ECC.
2535 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2536 struct mtd_oob_ops *ops)
2538 int chipnr, realpage, page, blockmask, column;
2539 struct nand_chip *chip = mtd_to_nand(mtd);
2540 uint32_t writelen = ops->len;
2542 uint32_t oobwritelen = ops->ooblen;
2543 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
2545 uint8_t *oob = ops->oobbuf;
2546 uint8_t *buf = ops->datbuf;
2548 int oob_required = oob ? 1 : 0;
2554 /* Reject writes, which are not page aligned */
2555 if (NOTALIGNED(to)) {
2556 pr_notice("%s: attempt to write non page aligned data\n",
2561 column = to & (mtd->writesize - 1);
2563 chipnr = (int)(to >> chip->chip_shift);
2564 chip->select_chip(mtd, chipnr);
2566 /* Check, if it is write protected */
2567 if (nand_check_wp(mtd)) {
2572 realpage = (int)(to >> chip->page_shift);
2573 page = realpage & chip->pagemask;
2574 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2576 /* Invalidate the page cache, when we write to the cached page */
2577 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2578 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2581 /* Don't allow multipage oob writes with offset */
2582 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2588 int bytes = mtd->writesize;
2589 int cached = writelen > bytes && page != blockmask;
2590 uint8_t *wbuf = buf;
2592 int part_pagewr = (column || writelen < mtd->writesize);
2600 /* Partial page write?, or need to use bounce buffer */
2602 pr_debug("%s: using write bounce buffer for buf@%p\n",
2606 bytes = min_t(int, bytes - column, writelen);
2608 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2609 memcpy(&chip->buffers->databuf[column], buf, bytes);
2610 wbuf = chip->buffers->databuf;
2613 if (unlikely(oob)) {
2614 size_t len = min(oobwritelen, oobmaxlen);
2615 oob = nand_fill_oob(mtd, oob, len, ops);
2618 /* We still need to erase leftover OOB data */
2619 memset(chip->oob_poi, 0xff, mtd->oobsize);
2621 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2622 oob_required, page, cached,
2623 (ops->mode == MTD_OPS_RAW));
2635 page = realpage & chip->pagemask;
2636 /* Check, if we cross a chip boundary */
2639 chip->select_chip(mtd, -1);
2640 chip->select_chip(mtd, chipnr);
2644 ops->retlen = ops->len - writelen;
2646 ops->oobretlen = ops->ooblen;
2649 chip->select_chip(mtd, -1);
2654 * panic_nand_write - [MTD Interface] NAND write with ECC
2655 * @mtd: MTD device structure
2656 * @to: offset to write to
2657 * @len: number of bytes to write
2658 * @retlen: pointer to variable to store the number of written bytes
2659 * @buf: the data to write
2661 * NAND write with ECC. Used when performing writes in interrupt context, this
2662 * may for example be called by mtdoops when writing an oops while in panic.
2664 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2665 size_t *retlen, const uint8_t *buf)
2667 struct nand_chip *chip = mtd_to_nand(mtd);
2668 struct mtd_oob_ops ops;
2671 /* Wait for the device to get ready */
2672 panic_nand_wait(mtd, chip, 400);
2674 /* Grab the device */
2675 panic_nand_get_device(chip, mtd, FL_WRITING);
2677 memset(&ops, 0, sizeof(ops));
2679 ops.datbuf = (uint8_t *)buf;
2680 ops.mode = MTD_OPS_PLACE_OOB;
2682 ret = nand_do_write_ops(mtd, to, &ops);
2684 *retlen = ops.retlen;
2689 * nand_write - [MTD Interface] NAND write with ECC
2690 * @mtd: MTD device structure
2691 * @to: offset to write to
2692 * @len: number of bytes to write
2693 * @retlen: pointer to variable to store the number of written bytes
2694 * @buf: the data to write
2696 * NAND write with ECC.
2698 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2699 size_t *retlen, const uint8_t *buf)
2701 struct mtd_oob_ops ops;
2704 nand_get_device(mtd, FL_WRITING);
2705 memset(&ops, 0, sizeof(ops));
2707 ops.datbuf = (uint8_t *)buf;
2708 ops.mode = MTD_OPS_PLACE_OOB;
2709 ret = nand_do_write_ops(mtd, to, &ops);
2710 *retlen = ops.retlen;
2711 nand_release_device(mtd);
2716 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2717 * @mtd: MTD device structure
2718 * @to: offset to write to
2719 * @ops: oob operation description structure
2721 * NAND write out-of-band.
2723 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2724 struct mtd_oob_ops *ops)
2726 int chipnr, page, status, len;
2727 struct nand_chip *chip = mtd_to_nand(mtd);
2729 pr_debug("%s: to = 0x%08x, len = %i\n",
2730 __func__, (unsigned int)to, (int)ops->ooblen);
2732 len = mtd_oobavail(mtd, ops);
2734 /* Do not allow write past end of page */
2735 if ((ops->ooboffs + ops->ooblen) > len) {
2736 pr_debug("%s: attempt to write past end of page\n",
2741 if (unlikely(ops->ooboffs >= len)) {
2742 pr_debug("%s: attempt to start write outside oob\n",
2747 /* Do not allow write past end of device */
2748 if (unlikely(to >= mtd->size ||
2749 ops->ooboffs + ops->ooblen >
2750 ((mtd->size >> chip->page_shift) -
2751 (to >> chip->page_shift)) * len)) {
2752 pr_debug("%s: attempt to write beyond end of device\n",
2757 chipnr = (int)(to >> chip->chip_shift);
2760 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2761 * of my DiskOnChip 2000 test units) will clear the whole data page too
2762 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2763 * it in the doc2000 driver in August 1999. dwmw2.
2765 nand_reset(chip, chipnr);
2767 chip->select_chip(mtd, chipnr);
2769 /* Shift to get page */
2770 page = (int)(to >> chip->page_shift);
2772 /* Check, if it is write protected */
2773 if (nand_check_wp(mtd)) {
2774 chip->select_chip(mtd, -1);
2778 /* Invalidate the page cache, if we write to the cached page */
2779 if (page == chip->pagebuf)
2782 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2784 if (ops->mode == MTD_OPS_RAW)
2785 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2787 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2789 chip->select_chip(mtd, -1);
2794 ops->oobretlen = ops->ooblen;
2800 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2801 * @mtd: MTD device structure
2802 * @to: offset to write to
2803 * @ops: oob operation description structure
2805 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2806 struct mtd_oob_ops *ops)
2808 int ret = -ENOTSUPP;
2812 /* Do not allow writes past end of device */
2813 if (ops->datbuf && (to + ops->len) > mtd->size) {
2814 pr_debug("%s: attempt to write beyond end of device\n",
2819 nand_get_device(mtd, FL_WRITING);
2821 switch (ops->mode) {
2822 case MTD_OPS_PLACE_OOB:
2823 case MTD_OPS_AUTO_OOB:
2832 ret = nand_do_write_oob(mtd, to, ops);
2834 ret = nand_do_write_ops(mtd, to, ops);
2837 nand_release_device(mtd);
2842 * single_erase - [GENERIC] NAND standard block erase command function
2843 * @mtd: MTD device structure
2844 * @page: the page address of the block which will be erased
2846 * Standard erase command for NAND chips. Returns NAND status.
2848 static int single_erase(struct mtd_info *mtd, int page)
2850 struct nand_chip *chip = mtd_to_nand(mtd);
2851 /* Send commands to erase a block */
2852 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2853 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2855 return chip->waitfunc(mtd, chip);
2859 * nand_erase - [MTD Interface] erase block(s)
2860 * @mtd: MTD device structure
2861 * @instr: erase instruction
2863 * Erase one ore more blocks.
2865 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2867 return nand_erase_nand(mtd, instr, 0);
2871 * nand_erase_nand - [INTERN] erase block(s)
2872 * @mtd: MTD device structure
2873 * @instr: erase instruction
2874 * @allowbbt: allow erasing the bbt area
2876 * Erase one ore more blocks.
2878 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2881 int page, status, pages_per_block, ret, chipnr;
2882 struct nand_chip *chip = mtd_to_nand(mtd);
2885 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2886 __func__, (unsigned long long)instr->addr,
2887 (unsigned long long)instr->len);
2889 if (check_offs_len(mtd, instr->addr, instr->len))
2892 /* Grab the lock and see if the device is available */
2893 nand_get_device(mtd, FL_ERASING);
2895 /* Shift to get first page */
2896 page = (int)(instr->addr >> chip->page_shift);
2897 chipnr = (int)(instr->addr >> chip->chip_shift);
2899 /* Calculate pages in each block */
2900 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2902 /* Select the NAND device */
2903 chip->select_chip(mtd, chipnr);
2905 /* Check, if it is write protected */
2906 if (nand_check_wp(mtd)) {
2907 pr_debug("%s: device is write protected!\n",
2909 instr->state = MTD_ERASE_FAILED;
2913 /* Loop through the pages */
2916 instr->state = MTD_ERASING;
2921 /* Check if we have a bad block, we do not erase bad blocks! */
2922 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2923 chip->page_shift, allowbbt)) {
2924 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2926 instr->state = MTD_ERASE_FAILED;
2931 * Invalidate the page cache, if we erase the block which
2932 * contains the current cached page.
2934 if (page <= chip->pagebuf && chip->pagebuf <
2935 (page + pages_per_block))
2938 status = chip->erase(mtd, page & chip->pagemask);
2941 * See if operation failed and additional status checks are
2944 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2945 status = chip->errstat(mtd, chip, FL_ERASING,
2948 /* See if block erase succeeded */
2949 if (status & NAND_STATUS_FAIL) {
2950 pr_debug("%s: failed erase, page 0x%08x\n",
2952 instr->state = MTD_ERASE_FAILED;
2954 ((loff_t)page << chip->page_shift);
2958 /* Increment page address and decrement length */
2959 len -= (1ULL << chip->phys_erase_shift);
2960 page += pages_per_block;
2962 /* Check, if we cross a chip boundary */
2963 if (len && !(page & chip->pagemask)) {
2965 chip->select_chip(mtd, -1);
2966 chip->select_chip(mtd, chipnr);
2969 instr->state = MTD_ERASE_DONE;
2973 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2975 /* Deselect and wake up anyone waiting on the device */
2976 chip->select_chip(mtd, -1);
2977 nand_release_device(mtd);
2979 /* Do call back function */
2981 mtd_erase_callback(instr);
2983 /* Return more or less happy */
2988 * nand_sync - [MTD Interface] sync
2989 * @mtd: MTD device structure
2991 * Sync is actually a wait for chip ready function.
2993 static void nand_sync(struct mtd_info *mtd)
2995 pr_debug("%s: called\n", __func__);
2997 /* Grab the lock and see if the device is available */
2998 nand_get_device(mtd, FL_SYNCING);
2999 /* Release it and go back */
3000 nand_release_device(mtd);
3004 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3005 * @mtd: MTD device structure
3006 * @offs: offset relative to mtd start
3008 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
3010 struct nand_chip *chip = mtd_to_nand(mtd);
3011 int chipnr = (int)(offs >> chip->chip_shift);
3014 /* Select the NAND device */
3015 nand_get_device(mtd, FL_READING);
3016 chip->select_chip(mtd, chipnr);
3018 ret = nand_block_checkbad(mtd, offs, 0);
3020 chip->select_chip(mtd, -1);
3021 nand_release_device(mtd);
3027 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3028 * @mtd: MTD device structure
3029 * @ofs: offset relative to mtd start
3031 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3035 ret = nand_block_isbad(mtd, ofs);
3037 /* If it was bad already, return success and do nothing */
3043 return nand_block_markbad_lowlevel(mtd, ofs);
3047 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3048 * @mtd: MTD device structure
3049 * @chip: nand chip info structure
3050 * @addr: feature address.
3051 * @subfeature_param: the subfeature parameters, a four bytes array.
3053 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3054 int addr, uint8_t *subfeature_param)
3059 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3060 if (!chip->onfi_version ||
3061 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3062 & ONFI_OPT_CMD_SET_GET_FEATURES))
3066 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3067 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3068 chip->write_byte(mtd, subfeature_param[i]);
3070 status = chip->waitfunc(mtd, chip);
3071 if (status & NAND_STATUS_FAIL)
3077 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3078 * @mtd: MTD device structure
3079 * @chip: nand chip info structure
3080 * @addr: feature address.
3081 * @subfeature_param: the subfeature parameters, a four bytes array.
3083 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3084 int addr, uint8_t *subfeature_param)
3088 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3089 if (!chip->onfi_version ||
3090 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3091 & ONFI_OPT_CMD_SET_GET_FEATURES))
3095 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3096 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3097 *subfeature_param++ = chip->read_byte(mtd);
3101 /* Set default functions */
3102 static void nand_set_defaults(struct nand_chip *chip, int busw)
3104 /* check for proper chip_delay setup, set 20us if not */
3105 if (!chip->chip_delay)
3106 chip->chip_delay = 20;
3108 /* check, if a user supplied command function given */
3109 if (chip->cmdfunc == NULL)
3110 chip->cmdfunc = nand_command;
3112 /* check, if a user supplied wait function given */
3113 if (chip->waitfunc == NULL)
3114 chip->waitfunc = nand_wait;
3116 if (!chip->select_chip)
3117 chip->select_chip = nand_select_chip;
3119 /* set for ONFI nand */
3120 if (!chip->onfi_set_features)
3121 chip->onfi_set_features = nand_onfi_set_features;
3122 if (!chip->onfi_get_features)
3123 chip->onfi_get_features = nand_onfi_get_features;
3125 /* If called twice, pointers that depend on busw may need to be reset */
3126 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3127 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3128 if (!chip->read_word)
3129 chip->read_word = nand_read_word;
3130 if (!chip->block_bad)
3131 chip->block_bad = nand_block_bad;
3132 if (!chip->block_markbad)
3133 chip->block_markbad = nand_default_block_markbad;
3134 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3135 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3136 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3137 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3138 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3139 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3140 if (!chip->scan_bbt)
3141 chip->scan_bbt = nand_default_bbt;
3143 if (!chip->controller) {
3144 chip->controller = &chip->hwcontrol;
3145 spin_lock_init(&chip->controller->lock);
3146 init_waitqueue_head(&chip->controller->wq);
3151 /* Sanitize ONFI strings so we can safely print them */
3152 static void sanitize_string(char *s, size_t len)
3156 /* Null terminate */
3159 /* Remove non printable chars */
3160 for (i = 0; i < len - 1; i++) {
3161 if (s[i] < ' ' || s[i] > 127)
3165 /* Remove trailing spaces */
3169 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3174 for (i = 0; i < 8; i++)
3175 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3181 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3182 /* Parse the Extended Parameter Page. */
3183 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3184 struct nand_chip *chip, struct nand_onfi_params *p)
3186 struct onfi_ext_param_page *ep;
3187 struct onfi_ext_section *s;
3188 struct onfi_ext_ecc_info *ecc;
3194 len = le16_to_cpu(p->ext_param_page_length) * 16;
3195 ep = kmalloc(len, GFP_KERNEL);
3199 /* Send our own NAND_CMD_PARAM. */
3200 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3202 /* Use the Change Read Column command to skip the ONFI param pages. */
3203 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3204 sizeof(*p) * p->num_of_param_pages , -1);
3206 /* Read out the Extended Parameter Page. */
3207 chip->read_buf(mtd, (uint8_t *)ep, len);
3208 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3209 != le16_to_cpu(ep->crc))) {
3210 pr_debug("fail in the CRC.\n");
3215 * Check the signature.
3216 * Do not strictly follow the ONFI spec, maybe changed in future.
3218 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3219 pr_debug("The signature is invalid.\n");
3223 /* find the ECC section. */
3224 cursor = (uint8_t *)(ep + 1);
3225 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3226 s = ep->sections + i;
3227 if (s->type == ONFI_SECTION_TYPE_2)
3229 cursor += s->length * 16;
3231 if (i == ONFI_EXT_SECTION_MAX) {
3232 pr_debug("We can not find the ECC section.\n");
3236 /* get the info we want. */
3237 ecc = (struct onfi_ext_ecc_info *)cursor;
3239 if (!ecc->codeword_size) {
3240 pr_debug("Invalid codeword size\n");
3244 chip->ecc_strength_ds = ecc->ecc_bits;
3245 chip->ecc_step_ds = 1 << ecc->codeword_size;
3253 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3255 struct nand_chip *chip = mtd_to_nand(mtd);
3256 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3258 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3263 * Configure chip properties from Micron vendor-specific ONFI table
3265 static void nand_onfi_detect_micron(struct nand_chip *chip,
3266 struct nand_onfi_params *p)
3268 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3270 if (le16_to_cpu(p->vendor_revision) < 1)
3273 chip->read_retries = micron->read_retry_options;
3274 chip->setup_read_retry = nand_setup_read_retry_micron;
3278 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3280 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3283 struct nand_onfi_params *p = &chip->onfi_params;
3287 /* Try ONFI for unknown chip or LP */
3288 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3289 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3290 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3293 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3294 for (i = 0; i < 3; i++) {
3295 for (j = 0; j < sizeof(*p); j++)
3296 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3297 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3298 le16_to_cpu(p->crc)) {
3304 pr_err("Could not find valid ONFI parameter page; aborting\n");
3309 val = le16_to_cpu(p->revision);
3311 chip->onfi_version = 23;
3312 else if (val & (1 << 4))
3313 chip->onfi_version = 22;
3314 else if (val & (1 << 3))
3315 chip->onfi_version = 21;
3316 else if (val & (1 << 2))
3317 chip->onfi_version = 20;
3318 else if (val & (1 << 1))
3319 chip->onfi_version = 10;
3321 if (!chip->onfi_version) {
3322 pr_info("unsupported ONFI version: %d\n", val);
3326 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3327 sanitize_string(p->model, sizeof(p->model));
3329 mtd->name = p->model;
3331 mtd->writesize = le32_to_cpu(p->byte_per_page);
3334 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3335 * (don't ask me who thought of this...). MTD assumes that these
3336 * dimensions will be power-of-2, so just truncate the remaining area.
3338 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3339 mtd->erasesize *= mtd->writesize;
3341 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3343 /* See erasesize comment */
3344 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3345 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3346 chip->bits_per_cell = p->bits_per_cell;
3348 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3349 *busw = NAND_BUSWIDTH_16;
3353 if (p->ecc_bits != 0xff) {
3354 chip->ecc_strength_ds = p->ecc_bits;
3355 chip->ecc_step_ds = 512;
3356 } else if (chip->onfi_version >= 21 &&
3357 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3360 * The nand_flash_detect_ext_param_page() uses the
3361 * Change Read Column command which maybe not supported
3362 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3363 * now. We do not replace user supplied command function.
3365 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3366 chip->cmdfunc = nand_command_lp;
3368 /* The Extended Parameter Page is supported since ONFI 2.1. */
3369 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3370 pr_warn("Failed to detect ONFI extended param page\n");
3372 pr_warn("Could not retrieve ONFI ECC requirements\n");
3375 if (p->jedec_id == NAND_MFR_MICRON)
3376 nand_onfi_detect_micron(chip, p);
3381 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3389 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3391 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3394 struct nand_jedec_params *p = &chip->jedec_params;
3395 struct jedec_ecc_info *ecc;
3399 /* Try JEDEC for unknown chip or LP */
3400 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3401 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3402 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3403 chip->read_byte(mtd) != 'C')
3406 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3407 for (i = 0; i < 3; i++) {
3408 for (j = 0; j < sizeof(*p); j++)
3409 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3411 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3412 le16_to_cpu(p->crc))
3417 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3422 val = le16_to_cpu(p->revision);
3424 chip->jedec_version = 10;
3425 else if (val & (1 << 1))
3426 chip->jedec_version = 1; /* vendor specific version */
3428 if (!chip->jedec_version) {
3429 pr_info("unsupported JEDEC version: %d\n", val);
3433 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3434 sanitize_string(p->model, sizeof(p->model));
3436 mtd->name = p->model;
3438 mtd->writesize = le32_to_cpu(p->byte_per_page);
3440 /* Please reference to the comment for nand_flash_detect_onfi. */
3441 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3442 mtd->erasesize *= mtd->writesize;
3444 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3446 /* Please reference to the comment for nand_flash_detect_onfi. */
3447 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3448 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3449 chip->bits_per_cell = p->bits_per_cell;
3451 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3452 *busw = NAND_BUSWIDTH_16;
3457 ecc = &p->ecc_info[0];
3459 if (ecc->codeword_size >= 9) {
3460 chip->ecc_strength_ds = ecc->ecc_bits;
3461 chip->ecc_step_ds = 1 << ecc->codeword_size;
3463 pr_warn("Invalid codeword size\n");
3470 * nand_id_has_period - Check if an ID string has a given wraparound period
3471 * @id_data: the ID string
3472 * @arrlen: the length of the @id_data array
3473 * @period: the period of repitition
3475 * Check if an ID string is repeated within a given sequence of bytes at
3476 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3477 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3478 * if the repetition has a period of @period; otherwise, returns zero.
3480 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3483 for (i = 0; i < period; i++)
3484 for (j = i + period; j < arrlen; j += period)
3485 if (id_data[i] != id_data[j])
3491 * nand_id_len - Get the length of an ID string returned by CMD_READID
3492 * @id_data: the ID string
3493 * @arrlen: the length of the @id_data array
3495 * Returns the length of the ID string, according to known wraparound/trailing
3496 * zero patterns. If no pattern exists, returns the length of the array.
3498 static int nand_id_len(u8 *id_data, int arrlen)
3500 int last_nonzero, period;
3502 /* Find last non-zero byte */
3503 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3504 if (id_data[last_nonzero])
3508 if (last_nonzero < 0)
3511 /* Calculate wraparound period */
3512 for (period = 1; period < arrlen; period++)
3513 if (nand_id_has_period(id_data, arrlen, period))
3516 /* There's a repeated pattern */
3517 if (period < arrlen)
3520 /* There are trailing zeros */
3521 if (last_nonzero < arrlen - 1)
3522 return last_nonzero + 1;
3524 /* No pattern detected */
3528 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3529 static int nand_get_bits_per_cell(u8 cellinfo)
3533 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3534 bits >>= NAND_CI_CELLTYPE_SHIFT;
3539 * Many new NAND share similar device ID codes, which represent the size of the
3540 * chip. The rest of the parameters must be decoded according to generic or
3541 * manufacturer-specific "extended ID" decoding patterns.
3543 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3544 u8 id_data[8], int *busw)
3547 /* The 3rd id byte holds MLC / multichip data */
3548 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3549 /* The 4th id byte is the important one */
3552 id_len = nand_id_len(id_data, 8);
3555 * Field definitions are in the following datasheets:
3556 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3557 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3558 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3560 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3561 * ID to decide what to do.
3563 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3564 !nand_is_slc(chip) && id_data[5] != 0x00) {
3566 mtd->writesize = 2048 << (extid & 0x03);
3569 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3589 default: /* Other cases are "reserved" (unknown) */
3590 mtd->oobsize = 1024;
3594 /* Calc blocksize */
3595 mtd->erasesize = (128 * 1024) <<
3596 (((extid >> 1) & 0x04) | (extid & 0x03));
3598 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3599 !nand_is_slc(chip)) {
3603 mtd->writesize = 2048 << (extid & 0x03);
3606 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3630 /* Calc blocksize */
3631 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3633 mtd->erasesize = (128 * 1024) << tmp;
3634 else if (tmp == 0x03)
3635 mtd->erasesize = 768 * 1024;
3637 mtd->erasesize = (64 * 1024) << tmp;
3641 mtd->writesize = 1024 << (extid & 0x03);
3644 mtd->oobsize = (8 << (extid & 0x01)) *
3645 (mtd->writesize >> 9);
3647 /* Calc blocksize. Blocksize is multiples of 64KiB */
3648 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3650 /* Get buswidth information */
3651 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3654 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3655 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3657 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3659 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3661 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3662 nand_is_slc(chip) &&
3663 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3664 !(id_data[4] & 0x80) /* !BENAND */) {
3665 mtd->oobsize = 32 * mtd->writesize >> 9;
3672 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3673 * decodes a matching ID table entry and assigns the MTD size parameters for
3676 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3677 struct nand_flash_dev *type, u8 id_data[8],
3680 int maf_id = id_data[0];
3682 mtd->erasesize = type->erasesize;
3683 mtd->writesize = type->pagesize;
3684 mtd->oobsize = mtd->writesize / 32;
3685 *busw = type->options & NAND_BUSWIDTH_16;
3687 /* All legacy ID NAND are small-page, SLC */
3688 chip->bits_per_cell = 1;
3691 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3692 * some Spansion chips have erasesize that conflicts with size
3693 * listed in nand_ids table.
3694 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3696 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3697 && id_data[6] == 0x00 && id_data[7] == 0x00
3698 && mtd->writesize == 512) {
3699 mtd->erasesize = 128 * 1024;
3700 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3705 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3706 * heuristic patterns using various detected parameters (e.g., manufacturer,
3707 * page size, cell-type information).
3709 static void nand_decode_bbm_options(struct mtd_info *mtd,
3710 struct nand_chip *chip, u8 id_data[8])
3712 int maf_id = id_data[0];
3714 /* Set the bad block position */
3715 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3716 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3718 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3721 * Bad block marker is stored in the last page of each block on Samsung
3722 * and Hynix MLC devices; stored in first two pages of each block on
3723 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3724 * AMD/Spansion, and Macronix. All others scan only the first page.
3726 if (!nand_is_slc(chip) &&
3727 (maf_id == NAND_MFR_SAMSUNG ||
3728 maf_id == NAND_MFR_HYNIX))
3729 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3730 else if ((nand_is_slc(chip) &&
3731 (maf_id == NAND_MFR_SAMSUNG ||
3732 maf_id == NAND_MFR_HYNIX ||
3733 maf_id == NAND_MFR_TOSHIBA ||
3734 maf_id == NAND_MFR_AMD ||
3735 maf_id == NAND_MFR_MACRONIX)) ||
3736 (mtd->writesize == 2048 &&
3737 maf_id == NAND_MFR_MICRON))
3738 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3741 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3743 return type->id_len;
3746 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3747 struct nand_flash_dev *type, u8 *id_data, int *busw)
3749 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3750 mtd->writesize = type->pagesize;
3751 mtd->erasesize = type->erasesize;
3752 mtd->oobsize = type->oobsize;
3754 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3755 chip->chipsize = (uint64_t)type->chipsize << 20;
3756 chip->options |= type->options;
3757 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3758 chip->ecc_step_ds = NAND_ECC_STEP(type);
3759 chip->onfi_timing_mode_default =
3760 type->onfi_timing_mode_default;
3762 *busw = type->options & NAND_BUSWIDTH_16;
3765 mtd->name = type->name;
3773 * Get the flash and manufacturer id and lookup if the type is supported.
3775 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3776 struct nand_chip *chip,
3777 int *maf_id, int *dev_id,
3778 struct nand_flash_dev *type)
3785 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3788 nand_reset(chip, 0);
3790 /* Select the device */
3791 chip->select_chip(mtd, 0);
3793 /* Send the command for reading device ID */
3794 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3796 /* Read manufacturer and device IDs */
3797 *maf_id = chip->read_byte(mtd);
3798 *dev_id = chip->read_byte(mtd);
3801 * Try again to make sure, as some systems the bus-hold or other
3802 * interface concerns can cause random data which looks like a
3803 * possibly credible NAND flash to appear. If the two results do
3804 * not match, ignore the device completely.
3807 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3809 /* Read entire ID string */
3810 for (i = 0; i < 8; i++)
3811 id_data[i] = chip->read_byte(mtd);
3813 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3814 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3815 *maf_id, *dev_id, id_data[0], id_data[1]);
3816 return ERR_PTR(-ENODEV);
3820 type = nand_flash_ids;
3822 for (; type->name != NULL; type++) {
3823 if (is_full_id_nand(type)) {
3824 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3826 } else if (*dev_id == type->dev_id) {
3831 chip->onfi_version = 0;
3832 if (!type->name || !type->pagesize) {
3833 /* Check if the chip is ONFI compliant */
3834 if (nand_flash_detect_onfi(mtd, chip, &busw))
3837 /* Check if the chip is JEDEC compliant */
3838 if (nand_flash_detect_jedec(mtd, chip, &busw))
3843 return ERR_PTR(-ENODEV);
3846 mtd->name = type->name;
3848 chip->chipsize = (uint64_t)type->chipsize << 20;
3850 if (!type->pagesize) {
3851 /* Decode parameters from extended ID */
3852 nand_decode_ext_id(mtd, chip, id_data, &busw);
3854 nand_decode_id(mtd, chip, type, id_data, &busw);
3856 /* Get chip options */
3857 chip->options |= type->options;
3860 * Check if chip is not a Samsung device. Do not clear the
3861 * options for chips which do not have an extended id.
3863 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3864 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3867 /* Try to identify manufacturer */
3868 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3869 if (nand_manuf_ids[maf_idx].id == *maf_id)
3873 if (chip->options & NAND_BUSWIDTH_AUTO) {
3874 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3875 chip->options |= busw;
3876 nand_set_defaults(chip, busw);
3877 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3879 * Check, if buswidth is correct. Hardware drivers should set
3882 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3884 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3885 pr_warn("bus width %d instead %d bit\n",
3886 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3888 return ERR_PTR(-EINVAL);
3891 nand_decode_bbm_options(mtd, chip, id_data);
3893 /* Calculate the address shift from the page size */
3894 chip->page_shift = ffs(mtd->writesize) - 1;
3895 /* Convert chipsize to number of pages per chip -1 */
3896 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3898 chip->bbt_erase_shift = chip->phys_erase_shift =
3899 ffs(mtd->erasesize) - 1;
3900 if (chip->chipsize & 0xffffffff)
3901 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3903 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3904 chip->chip_shift += 32 - 1;
3907 chip->badblockbits = 8;
3908 chip->erase = single_erase;
3910 /* Do not replace user supplied command function! */
3911 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3912 chip->cmdfunc = nand_command_lp;
3914 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3917 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3918 if (chip->onfi_version)
3919 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3920 chip->onfi_params.model);
3921 else if (chip->jedec_version)
3922 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3923 chip->jedec_params.model);
3925 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3928 if (chip->jedec_version)
3929 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3930 chip->jedec_params.model);
3932 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3935 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3939 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3940 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3941 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
3945 #if CONFIG_IS_ENABLED(OF_CONTROL)
3946 DECLARE_GLOBAL_DATA_PTR;
3948 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
3950 int ret, ecc_mode = -1, ecc_strength, ecc_step;
3951 const void *blob = gd->fdt_blob;
3954 ret = fdtdec_get_int(blob, node, "nand-bus-width", -1);
3956 chip->options |= NAND_BUSWIDTH_16;
3958 if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt"))
3959 chip->bbt_options |= NAND_BBT_USE_FLASH;
3961 str = fdt_getprop(blob, node, "nand-ecc-mode", NULL);
3963 if (!strcmp(str, "none"))
3964 ecc_mode = NAND_ECC_NONE;
3965 else if (!strcmp(str, "soft"))
3966 ecc_mode = NAND_ECC_SOFT;
3967 else if (!strcmp(str, "hw"))
3968 ecc_mode = NAND_ECC_HW;
3969 else if (!strcmp(str, "hw_syndrome"))
3970 ecc_mode = NAND_ECC_HW_SYNDROME;
3971 else if (!strcmp(str, "hw_oob_first"))
3972 ecc_mode = NAND_ECC_HW_OOB_FIRST;
3973 else if (!strcmp(str, "soft_bch"))
3974 ecc_mode = NAND_ECC_SOFT_BCH;
3978 ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1);
3979 ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1);
3981 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
3982 (!(ecc_step >= 0) && ecc_strength >= 0)) {
3983 pr_err("must set both strength and step size in DT\n");
3988 chip->ecc.mode = ecc_mode;
3990 if (ecc_strength >= 0)
3991 chip->ecc.strength = ecc_strength;
3994 chip->ecc.size = ecc_step;
3996 if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL))
3997 chip->ecc.options |= NAND_ECC_MAXIMIZE;
4002 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
4006 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
4009 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4010 * @mtd: MTD device structure
4011 * @maxchips: number of chips to scan for
4012 * @table: alternative NAND ID table
4014 * This is the first phase of the normal nand_scan() function. It reads the
4015 * flash ID and sets up MTD fields accordingly.
4018 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4019 struct nand_flash_dev *table)
4021 int i, nand_maf_id, nand_dev_id;
4022 struct nand_chip *chip = mtd_to_nand(mtd);
4023 struct nand_flash_dev *type;
4026 if (chip->flash_node) {
4027 ret = nand_dt_init(mtd, chip, chip->flash_node);
4032 /* Set the default functions */
4033 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
4035 /* Read the flash type */
4036 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4037 &nand_dev_id, table);
4040 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
4041 pr_warn("No NAND device found\n");
4042 chip->select_chip(mtd, -1);
4043 return PTR_ERR(type);
4046 /* Initialize the ->data_interface field. */
4047 ret = nand_init_data_interface(chip);
4052 * Setup the data interface correctly on the chip and controller side.
4053 * This explicit call to nand_setup_data_interface() is only required
4054 * for the first die, because nand_reset() has been called before
4055 * ->data_interface and ->default_onfi_timing_mode were set.
4056 * For the other dies, nand_reset() will automatically switch to the
4059 ret = nand_setup_data_interface(chip);
4063 chip->select_chip(mtd, -1);
4065 /* Check for a chip array */
4066 for (i = 1; i < maxchips; i++) {
4067 /* See comment in nand_get_flash_type for reset */
4068 nand_reset(chip, i);
4070 chip->select_chip(mtd, i);
4071 /* Send the command for reading device ID */
4072 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4073 /* Read manufacturer and device IDs */
4074 if (nand_maf_id != chip->read_byte(mtd) ||
4075 nand_dev_id != chip->read_byte(mtd)) {
4076 chip->select_chip(mtd, -1);
4079 chip->select_chip(mtd, -1);
4084 pr_info("%d chips detected\n", i);
4087 /* Store the number of chips and calc total size for mtd */
4089 mtd->size = i * chip->chipsize;
4093 EXPORT_SYMBOL(nand_scan_ident);
4096 * Check if the chip configuration meet the datasheet requirements.
4098 * If our configuration corrects A bits per B bytes and the minimum
4099 * required correction level is X bits per Y bytes, then we must ensure
4100 * both of the following are true:
4102 * (1) A / B >= X / Y
4105 * Requirement (1) ensures we can correct for the required bitflip density.
4106 * Requirement (2) ensures we can correct even when all bitflips are clumped
4107 * in the same sector.
4109 static bool nand_ecc_strength_good(struct mtd_info *mtd)
4111 struct nand_chip *chip = mtd_to_nand(mtd);
4112 struct nand_ecc_ctrl *ecc = &chip->ecc;
4115 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4116 /* Not enough information */
4120 * We get the number of corrected bits per page to compare
4121 * the correction density.
4123 corr = (mtd->writesize * ecc->strength) / ecc->size;
4124 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4126 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4130 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4131 * @mtd: MTD device structure
4133 * This is the second phase of the normal nand_scan() function. It fills out
4134 * all the uninitialized function pointers with the defaults and scans for a
4135 * bad block table if appropriate.
4137 int nand_scan_tail(struct mtd_info *mtd)
4140 struct nand_chip *chip = mtd_to_nand(mtd);
4141 struct nand_ecc_ctrl *ecc = &chip->ecc;
4142 struct nand_buffers *nbuf;
4144 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4145 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4146 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4148 if (!(chip->options & NAND_OWN_BUFFERS)) {
4149 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4150 chip->buffers = nbuf;
4156 /* Set the internal oob buffer location, just after the page data */
4157 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4160 * If no default placement scheme is given, select an appropriate one.
4162 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4163 switch (mtd->oobsize) {
4165 ecc->layout = &nand_oob_8;
4168 ecc->layout = &nand_oob_16;
4171 ecc->layout = &nand_oob_64;
4174 ecc->layout = &nand_oob_128;
4177 pr_warn("No oob scheme defined for oobsize %d\n",
4183 if (!chip->write_page)
4184 chip->write_page = nand_write_page;
4187 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4188 * selected and we have 256 byte pagesize fallback to software ECC
4191 switch (ecc->mode) {
4192 case NAND_ECC_HW_OOB_FIRST:
4193 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4194 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4195 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4198 if (!ecc->read_page)
4199 ecc->read_page = nand_read_page_hwecc_oob_first;
4202 /* Use standard hwecc read page function? */
4203 if (!ecc->read_page)
4204 ecc->read_page = nand_read_page_hwecc;
4205 if (!ecc->write_page)
4206 ecc->write_page = nand_write_page_hwecc;
4207 if (!ecc->read_page_raw)
4208 ecc->read_page_raw = nand_read_page_raw;
4209 if (!ecc->write_page_raw)
4210 ecc->write_page_raw = nand_write_page_raw;
4212 ecc->read_oob = nand_read_oob_std;
4213 if (!ecc->write_oob)
4214 ecc->write_oob = nand_write_oob_std;
4215 if (!ecc->read_subpage)
4216 ecc->read_subpage = nand_read_subpage;
4217 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
4218 ecc->write_subpage = nand_write_subpage_hwecc;
4220 case NAND_ECC_HW_SYNDROME:
4221 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4223 ecc->read_page == nand_read_page_hwecc ||
4225 ecc->write_page == nand_write_page_hwecc)) {
4226 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4229 /* Use standard syndrome read/write page function? */
4230 if (!ecc->read_page)
4231 ecc->read_page = nand_read_page_syndrome;
4232 if (!ecc->write_page)
4233 ecc->write_page = nand_write_page_syndrome;
4234 if (!ecc->read_page_raw)
4235 ecc->read_page_raw = nand_read_page_raw_syndrome;
4236 if (!ecc->write_page_raw)
4237 ecc->write_page_raw = nand_write_page_raw_syndrome;
4239 ecc->read_oob = nand_read_oob_syndrome;
4240 if (!ecc->write_oob)
4241 ecc->write_oob = nand_write_oob_syndrome;
4243 if (mtd->writesize >= ecc->size) {
4244 if (!ecc->strength) {
4245 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4250 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4251 ecc->size, mtd->writesize);
4252 ecc->mode = NAND_ECC_SOFT;
4255 ecc->calculate = nand_calculate_ecc;
4256 ecc->correct = nand_correct_data;
4257 ecc->read_page = nand_read_page_swecc;
4258 ecc->read_subpage = nand_read_subpage;
4259 ecc->write_page = nand_write_page_swecc;
4260 ecc->read_page_raw = nand_read_page_raw;
4261 ecc->write_page_raw = nand_write_page_raw;
4262 ecc->read_oob = nand_read_oob_std;
4263 ecc->write_oob = nand_write_oob_std;
4270 case NAND_ECC_SOFT_BCH:
4271 if (!mtd_nand_has_bch()) {
4272 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4275 ecc->calculate = nand_bch_calculate_ecc;
4276 ecc->correct = nand_bch_correct_data;
4277 ecc->read_page = nand_read_page_swecc;
4278 ecc->read_subpage = nand_read_subpage;
4279 ecc->write_page = nand_write_page_swecc;
4280 ecc->read_page_raw = nand_read_page_raw;
4281 ecc->write_page_raw = nand_write_page_raw;
4282 ecc->read_oob = nand_read_oob_std;
4283 ecc->write_oob = nand_write_oob_std;
4285 * Board driver should supply ecc.size and ecc.strength values
4286 * to select how many bits are correctable. Otherwise, default
4287 * to 4 bits for large page devices.
4289 if (!ecc->size && (mtd->oobsize >= 64)) {
4294 /* See nand_bch_init() for details. */
4296 ecc->priv = nand_bch_init(mtd);
4298 pr_warn("BCH ECC initialization failed!\n");
4304 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4305 ecc->read_page = nand_read_page_raw;
4306 ecc->write_page = nand_write_page_raw;
4307 ecc->read_oob = nand_read_oob_std;
4308 ecc->read_page_raw = nand_read_page_raw;
4309 ecc->write_page_raw = nand_write_page_raw;
4310 ecc->write_oob = nand_write_oob_std;
4311 ecc->size = mtd->writesize;
4317 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4321 /* For many systems, the standard OOB write also works for raw */
4322 if (!ecc->read_oob_raw)
4323 ecc->read_oob_raw = ecc->read_oob;
4324 if (!ecc->write_oob_raw)
4325 ecc->write_oob_raw = ecc->write_oob;
4328 * The number of bytes available for a client to place data into
4329 * the out of band area.
4333 for (i = 0; ecc->layout->oobfree[i].length; i++)
4334 mtd->oobavail += ecc->layout->oobfree[i].length;
4337 /* ECC sanity check: warn if it's too weak */
4338 if (!nand_ecc_strength_good(mtd))
4339 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4343 * Set the number of read / write steps for one page depending on ECC
4346 ecc->steps = mtd->writesize / ecc->size;
4347 if (ecc->steps * ecc->size != mtd->writesize) {
4348 pr_warn("Invalid ECC parameters\n");
4351 ecc->total = ecc->steps * ecc->bytes;
4353 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4354 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4355 switch (ecc->steps) {
4357 mtd->subpage_sft = 1;
4362 mtd->subpage_sft = 2;
4366 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4368 /* Initialize state */
4369 chip->state = FL_READY;
4371 /* Invalidate the pagebuffer reference */
4374 /* Large page NAND with SOFT_ECC should support subpage reads */
4375 switch (ecc->mode) {
4377 case NAND_ECC_SOFT_BCH:
4378 if (chip->page_shift > 9)
4379 chip->options |= NAND_SUBPAGE_READ;
4386 /* Fill in remaining MTD driver data */
4387 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4388 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4390 mtd->_erase = nand_erase;
4391 mtd->_read = nand_read;
4392 mtd->_write = nand_write;
4393 mtd->_panic_write = panic_nand_write;
4394 mtd->_read_oob = nand_read_oob;
4395 mtd->_write_oob = nand_write_oob;
4396 mtd->_sync = nand_sync;
4398 mtd->_unlock = NULL;
4399 mtd->_block_isreserved = nand_block_isreserved;
4400 mtd->_block_isbad = nand_block_isbad;
4401 mtd->_block_markbad = nand_block_markbad;
4402 mtd->writebufsize = mtd->writesize;
4404 /* propagate ecc info to mtd_info */
4405 mtd->ecclayout = ecc->layout;
4406 mtd->ecc_strength = ecc->strength;
4407 mtd->ecc_step_size = ecc->size;
4409 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4410 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4413 if (!mtd->bitflip_threshold)
4414 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4418 EXPORT_SYMBOL(nand_scan_tail);
4421 * nand_scan - [NAND Interface] Scan for the NAND device
4422 * @mtd: MTD device structure
4423 * @maxchips: number of chips to scan for
4425 * This fills out all the uninitialized function pointers with the defaults.
4426 * The flash ID is read and the mtd/chip structures are filled with the
4427 * appropriate values.
4429 int nand_scan(struct mtd_info *mtd, int maxchips)
4433 ret = nand_scan_ident(mtd, maxchips, NULL);
4435 ret = nand_scan_tail(mtd);
4438 EXPORT_SYMBOL(nand_scan);
4440 MODULE_LICENSE("GPL");
4441 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4442 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4443 MODULE_DESCRIPTION("Generic NAND flash driver code");