5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/err.h>
57 #include <linux/compat.h>
58 #include <linux/mtd/mtd.h>
59 #include <linux/mtd/nand.h>
60 #include <linux/mtd/nand_ecc.h>
61 #include <linux/mtd/nand_bch.h>
62 #ifdef CONFIG_MTD_PARTITIONS
63 #include <linux/mtd/partitions.h>
66 #include <asm/errno.h>
69 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
70 * a flash. NAND flash is initialized prior to interrupts so standard timers
71 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
72 * which is greater than (max NAND reset time / NAND status read time).
73 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
75 #ifndef CONFIG_SYS_NAND_RESET_CNT
76 #define CONFIG_SYS_NAND_RESET_CNT 200000
79 static bool is_module_text_address(unsigned long addr) {return 0;}
82 /* Define default oob placement schemes for large and small page devices */
83 static struct nand_ecclayout nand_oob_8 = {
93 static struct nand_ecclayout nand_oob_16 = {
95 .eccpos = {0, 1, 2, 3, 6, 7},
101 static struct nand_ecclayout nand_oob_64 = {
104 40, 41, 42, 43, 44, 45, 46, 47,
105 48, 49, 50, 51, 52, 53, 54, 55,
106 56, 57, 58, 59, 60, 61, 62, 63},
112 static struct nand_ecclayout nand_oob_128 = {
115 80, 81, 82, 83, 84, 85, 86, 87,
116 88, 89, 90, 91, 92, 93, 94, 95,
117 96, 97, 98, 99, 100, 101, 102, 103,
118 104, 105, 106, 107, 108, 109, 110, 111,
119 112, 113, 114, 115, 116, 117, 118, 119,
120 120, 121, 122, 123, 124, 125, 126, 127},
126 static int nand_get_device(struct mtd_info *mtd, int new_state);
128 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
129 struct mtd_oob_ops *ops);
132 * For devices which display every fart in the system on a separate LED. Is
133 * compiled away when LED support is disabled.
135 DEFINE_LED_TRIGGER(nand_led_trigger);
137 static int check_offs_len(struct mtd_info *mtd,
138 loff_t ofs, uint64_t len)
140 struct nand_chip *chip = mtd->priv;
143 /* Start address must align on block boundary */
144 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
145 pr_debug("%s: unaligned address\n", __func__);
149 /* Length must align on block boundary */
150 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
151 pr_debug("%s: length not block aligned\n", __func__);
159 * nand_release_device - [GENERIC] release chip
160 * @mtd: MTD device structure
162 * Release chip lock and wake up anyone waiting on the device.
164 static void nand_release_device(struct mtd_info *mtd)
166 struct nand_chip *chip = mtd->priv;
169 /* Release the controller and the chip */
170 spin_lock(&chip->controller->lock);
171 chip->controller->active = NULL;
172 chip->state = FL_READY;
173 wake_up(&chip->controller->wq);
174 spin_unlock(&chip->controller->lock);
176 /* De-select the NAND device */
177 chip->select_chip(mtd, -1);
182 * nand_read_byte - [DEFAULT] read one byte from the chip
183 * @mtd: MTD device structure
185 * Default read function for 8bit buswidth
188 static uint8_t nand_read_byte(struct mtd_info *mtd)
190 uint8_t nand_read_byte(struct mtd_info *mtd)
193 struct nand_chip *chip = mtd->priv;
194 return readb(chip->IO_ADDR_R);
198 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
199 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
200 * @mtd: MTD device structure
202 * Default read function for 16bit buswidth with endianness conversion.
205 static uint8_t nand_read_byte16(struct mtd_info *mtd)
207 struct nand_chip *chip = mtd->priv;
208 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
212 * nand_read_word - [DEFAULT] read one word from the chip
213 * @mtd: MTD device structure
215 * Default read function for 16bit buswidth without endianness conversion.
217 static u16 nand_read_word(struct mtd_info *mtd)
219 struct nand_chip *chip = mtd->priv;
220 return readw(chip->IO_ADDR_R);
224 * nand_select_chip - [DEFAULT] control CE line
225 * @mtd: MTD device structure
226 * @chipnr: chipnumber to select, -1 for deselect
228 * Default select function for 1 chip devices.
230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
232 struct nand_chip *chip = mtd->priv;
236 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
247 * nand_write_byte - [DEFAULT] write single byte to chip
248 * @mtd: MTD device structure
249 * @byte: value to write
251 * Default function to write a byte to I/O[7:0]
253 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
255 struct nand_chip *chip = mtd->priv;
257 chip->write_buf(mtd, &byte, 1);
261 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
262 * @mtd: MTD device structure
263 * @byte: value to write
265 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
267 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
269 struct nand_chip *chip = mtd->priv;
270 uint16_t word = byte;
273 * It's not entirely clear what should happen to I/O[15:8] when writing
274 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
276 * When the host supports a 16-bit bus width, only data is
277 * transferred at the 16-bit width. All address and command line
278 * transfers shall use only the lower 8-bits of the data bus. During
279 * command transfers, the host may place any value on the upper
280 * 8-bits of the data bus. During address transfers, the host shall
281 * set the upper 8-bits of the data bus to 00h.
283 * One user of the write_byte callback is nand_onfi_set_features. The
284 * four parameters are specified to be written to I/O[7:0], but this is
285 * neither an address nor a command transfer. Let's assume a 0 on the
286 * upper I/O lines is OK.
288 chip->write_buf(mtd, (uint8_t *)&word, 2);
291 #if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN)
292 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
296 for (i = 0; i < len; i++)
297 writeb(buf[i], addr);
299 static void ioread8_rep(void *addr, uint8_t *buf, int len)
303 for (i = 0; i < len; i++)
304 buf[i] = readb(addr);
307 static void ioread16_rep(void *addr, void *buf, int len)
310 u16 *p = (u16 *) buf;
312 for (i = 0; i < len; i++)
316 static void iowrite16_rep(void *addr, void *buf, int len)
319 u16 *p = (u16 *) buf;
321 for (i = 0; i < len; i++)
327 * nand_write_buf - [DEFAULT] write buffer to chip
328 * @mtd: MTD device structure
330 * @len: number of bytes to write
332 * Default write function for 8bit buswidth.
335 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
337 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
340 struct nand_chip *chip = mtd->priv;
342 iowrite8_rep(chip->IO_ADDR_W, buf, len);
346 * nand_read_buf - [DEFAULT] read chip data into buffer
347 * @mtd: MTD device structure
348 * @buf: buffer to store date
349 * @len: number of bytes to read
351 * Default read function for 8bit buswidth.
354 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
356 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
359 struct nand_chip *chip = mtd->priv;
361 ioread8_rep(chip->IO_ADDR_R, buf, len);
365 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
367 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
368 * @mtd: MTD device structure
369 * @buf: buffer containing the data to compare
370 * @len: number of bytes to compare
372 * Default verify function for 8bit buswidth.
374 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
377 struct nand_chip *chip = mtd->priv;
379 for (i = 0; i < len; i++)
380 if (buf[i] != readb(chip->IO_ADDR_R))
386 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
387 * @mtd: MTD device structure
388 * @buf: buffer containing the data to compare
389 * @len: number of bytes to compare
391 * Default verify function for 16bit buswidth.
393 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
396 struct nand_chip *chip = mtd->priv;
397 u16 *p = (u16 *) buf;
400 for (i = 0; i < len; i++)
401 if (p[i] != readw(chip->IO_ADDR_R))
410 * nand_write_buf16 - [DEFAULT] write buffer to chip
411 * @mtd: MTD device structure
413 * @len: number of bytes to write
415 * Default write function for 16bit buswidth.
418 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
420 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
423 struct nand_chip *chip = mtd->priv;
424 u16 *p = (u16 *) buf;
426 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
430 * nand_read_buf16 - [DEFAULT] read chip data into buffer
431 * @mtd: MTD device structure
432 * @buf: buffer to store date
433 * @len: number of bytes to read
435 * Default read function for 16bit buswidth.
438 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
440 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
443 struct nand_chip *chip = mtd->priv;
444 u16 *p = (u16 *) buf;
446 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
450 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
451 * @mtd: MTD device structure
452 * @ofs: offset from device start
453 * @getchip: 0, if the chip is already selected
455 * Check, if the block is bad.
457 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
459 int page, chipnr, res = 0, i = 0;
460 struct nand_chip *chip = mtd->priv;
463 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
464 ofs += mtd->erasesize - mtd->writesize;
466 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
469 chipnr = (int)(ofs >> chip->chip_shift);
471 nand_get_device(mtd, FL_READING);
473 /* Select the NAND device */
474 chip->select_chip(mtd, chipnr);
478 if (chip->options & NAND_BUSWIDTH_16) {
479 chip->cmdfunc(mtd, NAND_CMD_READOOB,
480 chip->badblockpos & 0xFE, page);
481 bad = cpu_to_le16(chip->read_word(mtd));
482 if (chip->badblockpos & 0x1)
487 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
489 bad = chip->read_byte(mtd);
492 if (likely(chip->badblockbits == 8))
495 res = hweight8(bad) < chip->badblockbits;
496 ofs += mtd->writesize;
497 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
499 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
502 chip->select_chip(mtd, -1);
503 nand_release_device(mtd);
510 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
511 * @mtd: MTD device structure
512 * @ofs: offset from device start
514 * This is the default implementation, which can be overridden by a hardware
515 * specific driver. It provides the details for writing a bad block marker to a
518 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
520 struct nand_chip *chip = mtd->priv;
521 struct mtd_oob_ops ops;
522 uint8_t buf[2] = { 0, 0 };
523 int ret = 0, res, i = 0;
527 ops.ooboffs = chip->badblockpos;
528 if (chip->options & NAND_BUSWIDTH_16) {
529 ops.ooboffs &= ~0x01;
530 ops.len = ops.ooblen = 2;
532 ops.len = ops.ooblen = 1;
534 ops.mode = MTD_OPS_PLACE_OOB;
536 /* Write to first/last page(s) if necessary */
537 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
538 ofs += mtd->erasesize - mtd->writesize;
540 res = nand_do_write_oob(mtd, ofs, &ops);
545 ofs += mtd->writesize;
546 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
552 * nand_block_markbad_lowlevel - mark a block bad
553 * @mtd: MTD device structure
554 * @ofs: offset from device start
556 * This function performs the generic NAND bad block marking steps (i.e., bad
557 * block table(s) and/or marker(s)). We only allow the hardware driver to
558 * specify how to write bad block markers to OOB (chip->block_markbad).
560 * We try operations in the following order:
561 * (1) erase the affected block, to allow OOB marker to be written cleanly
562 * (2) write bad block marker to OOB area of affected block (unless flag
563 * NAND_BBT_NO_OOB_BBM is present)
565 * Note that we retain the first error encountered in (2) or (3), finish the
566 * procedures, and dump the error in the end.
568 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
570 struct nand_chip *chip = mtd->priv;
573 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
574 struct erase_info einfo;
576 /* Attempt erase before marking OOB */
577 memset(&einfo, 0, sizeof(einfo));
580 einfo.len = 1ULL << chip->phys_erase_shift;
581 nand_erase_nand(mtd, &einfo, 0);
583 /* Write bad block marker to OOB */
584 nand_get_device(mtd, FL_WRITING);
585 ret = chip->block_markbad(mtd, ofs);
586 nand_release_device(mtd);
589 /* Mark block bad in BBT */
591 res = nand_markbad_bbt(mtd, ofs);
597 mtd->ecc_stats.badblocks++;
603 * nand_check_wp - [GENERIC] check if the chip is write protected
604 * @mtd: MTD device structure
606 * Check, if the device is write protected. The function expects, that the
607 * device is already selected.
609 static int nand_check_wp(struct mtd_info *mtd)
611 struct nand_chip *chip = mtd->priv;
613 /* Broken xD cards report WP despite being writable */
614 if (chip->options & NAND_BROKEN_XD)
617 /* Check the WP bit */
618 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
619 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
623 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
624 * @mtd: MTD device structure
625 * @ofs: offset from device start
626 * @getchip: 0, if the chip is already selected
627 * @allowbbt: 1, if its allowed to access the bbt area
629 * Check, if the block is bad. Either by reading the bad block table or
630 * calling of the scan function.
632 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
635 struct nand_chip *chip = mtd->priv;
637 if (!(chip->options & NAND_BBT_SCANNED)) {
639 chip->options |= NAND_BBT_SCANNED;
643 return chip->block_bad(mtd, ofs, getchip);
645 /* Return info from the table */
646 return nand_isbad_bbt(mtd, ofs, allowbbt);
651 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
652 * @mtd: MTD device structure
655 * Helper function for nand_wait_ready used when needing to wait in interrupt
658 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
660 struct nand_chip *chip = mtd->priv;
663 /* Wait for the device to get ready */
664 for (i = 0; i < timeo; i++) {
665 if (chip->dev_ready(mtd))
667 touch_softlockup_watchdog();
673 /* Wait for the ready pin, after a command. The timeout is caught later. */
674 void nand_wait_ready(struct mtd_info *mtd)
676 struct nand_chip *chip = mtd->priv;
678 unsigned long timeo = jiffies + msecs_to_jiffies(20);
681 if (in_interrupt() || oops_in_progress)
682 return panic_nand_wait_ready(mtd, 400);
684 led_trigger_event(nand_led_trigger, LED_FULL);
685 /* Wait until command is processed or timeout occurs */
687 if (chip->dev_ready(mtd))
689 touch_softlockup_watchdog();
690 } while (time_before(jiffies, timeo));
691 led_trigger_event(nand_led_trigger, LED_OFF);
693 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
696 time_start = get_timer(0);
697 /* Wait until command is processed or timeout occurs */
698 while (get_timer(time_start) < timeo) {
700 if (chip->dev_ready(mtd))
705 EXPORT_SYMBOL_GPL(nand_wait_ready);
708 * nand_command - [DEFAULT] Send command to NAND device
709 * @mtd: MTD device structure
710 * @command: the command to be sent
711 * @column: the column address for this command, -1 if none
712 * @page_addr: the page address for this command, -1 if none
714 * Send command to NAND device. This function is used for small page devices
715 * (512 Bytes per page).
717 static void nand_command(struct mtd_info *mtd, unsigned int command,
718 int column, int page_addr)
720 register struct nand_chip *chip = mtd->priv;
721 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
722 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
724 /* Write out the command to the device */
725 if (command == NAND_CMD_SEQIN) {
728 if (column >= mtd->writesize) {
730 column -= mtd->writesize;
731 readcmd = NAND_CMD_READOOB;
732 } else if (column < 256) {
733 /* First 256 bytes --> READ0 */
734 readcmd = NAND_CMD_READ0;
737 readcmd = NAND_CMD_READ1;
739 chip->cmd_ctrl(mtd, readcmd, ctrl);
740 ctrl &= ~NAND_CTRL_CHANGE;
742 chip->cmd_ctrl(mtd, command, ctrl);
744 /* Address cycle, when necessary */
745 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
746 /* Serially input address */
748 /* Adjust columns for 16 bit buswidth */
749 if (chip->options & NAND_BUSWIDTH_16 &&
750 !nand_opcode_8bits(command))
752 chip->cmd_ctrl(mtd, column, ctrl);
753 ctrl &= ~NAND_CTRL_CHANGE;
755 if (page_addr != -1) {
756 chip->cmd_ctrl(mtd, page_addr, ctrl);
757 ctrl &= ~NAND_CTRL_CHANGE;
758 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
759 /* One more address cycle for devices > 32MiB */
760 if (chip->chipsize > (32 << 20))
761 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
763 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
766 * Program and erase have their own busy handlers status and sequential
771 case NAND_CMD_PAGEPROG:
772 case NAND_CMD_ERASE1:
773 case NAND_CMD_ERASE2:
775 case NAND_CMD_STATUS:
781 udelay(chip->chip_delay);
782 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
783 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
785 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
786 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
790 /* This applies to read commands */
793 * If we don't have access to the busy pin, we apply the given
796 if (!chip->dev_ready) {
797 udelay(chip->chip_delay);
802 * Apply this short delay always to ensure that we do wait tWB in
803 * any case on any machine.
807 nand_wait_ready(mtd);
811 * nand_command_lp - [DEFAULT] Send command to NAND large page device
812 * @mtd: MTD device structure
813 * @command: the command to be sent
814 * @column: the column address for this command, -1 if none
815 * @page_addr: the page address for this command, -1 if none
817 * Send command to NAND device. This is the version for the new large page
818 * devices. We don't have the separate regions as we have in the small page
819 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
821 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
822 int column, int page_addr)
824 register struct nand_chip *chip = mtd->priv;
825 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
827 /* Emulate NAND_CMD_READOOB */
828 if (command == NAND_CMD_READOOB) {
829 column += mtd->writesize;
830 command = NAND_CMD_READ0;
833 /* Command latch cycle */
834 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
836 if (column != -1 || page_addr != -1) {
837 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
839 /* Serially input address */
841 /* Adjust columns for 16 bit buswidth */
842 if (chip->options & NAND_BUSWIDTH_16 &&
843 !nand_opcode_8bits(command))
845 chip->cmd_ctrl(mtd, column, ctrl);
846 ctrl &= ~NAND_CTRL_CHANGE;
847 chip->cmd_ctrl(mtd, column >> 8, ctrl);
849 if (page_addr != -1) {
850 chip->cmd_ctrl(mtd, page_addr, ctrl);
851 chip->cmd_ctrl(mtd, page_addr >> 8,
852 NAND_NCE | NAND_ALE);
853 /* One more address cycle for devices > 128MiB */
854 if (chip->chipsize > (128 << 20))
855 chip->cmd_ctrl(mtd, page_addr >> 16,
856 NAND_NCE | NAND_ALE);
859 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
862 * Program and erase have their own busy handlers status, sequential
863 * in, and deplete1 need no delay.
867 case NAND_CMD_CACHEDPROG:
868 case NAND_CMD_PAGEPROG:
869 case NAND_CMD_ERASE1:
870 case NAND_CMD_ERASE2:
873 case NAND_CMD_STATUS:
879 udelay(chip->chip_delay);
880 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
881 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
882 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
883 NAND_NCE | NAND_CTRL_CHANGE);
884 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
888 case NAND_CMD_RNDOUT:
889 /* No ready / busy check necessary */
890 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
891 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
892 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
893 NAND_NCE | NAND_CTRL_CHANGE);
897 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
898 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
899 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
900 NAND_NCE | NAND_CTRL_CHANGE);
902 /* This applies to read commands */
905 * If we don't have access to the busy pin, we apply the given
908 if (!chip->dev_ready) {
909 udelay(chip->chip_delay);
915 * Apply this short delay always to ensure that we do wait tWB in
916 * any case on any machine.
920 nand_wait_ready(mtd);
924 * panic_nand_get_device - [GENERIC] Get chip for selected access
925 * @chip: the nand chip descriptor
926 * @mtd: MTD device structure
927 * @new_state: the state which is requested
929 * Used when in panic, no locks are taken.
931 static void panic_nand_get_device(struct nand_chip *chip,
932 struct mtd_info *mtd, int new_state)
934 /* Hardware controller shared among independent devices */
935 chip->controller->active = chip;
936 chip->state = new_state;
940 * nand_get_device - [GENERIC] Get chip for selected access
941 * @mtd: MTD device structure
942 * @new_state: the state which is requested
944 * Get the device and lock it for exclusive access
947 nand_get_device(struct mtd_info *mtd, int new_state)
949 struct nand_chip *chip = mtd->priv;
951 spinlock_t *lock = &chip->controller->lock;
952 wait_queue_head_t *wq = &chip->controller->wq;
953 DECLARE_WAITQUEUE(wait, current);
957 /* Hardware controller shared among independent devices */
958 if (!chip->controller->active)
959 chip->controller->active = chip;
961 if (chip->controller->active == chip && chip->state == FL_READY) {
962 chip->state = new_state;
966 if (new_state == FL_PM_SUSPENDED) {
967 if (chip->controller->active->state == FL_PM_SUSPENDED) {
968 chip->state = FL_PM_SUSPENDED;
973 set_current_state(TASK_UNINTERRUPTIBLE);
974 add_wait_queue(wq, &wait);
977 remove_wait_queue(wq, &wait);
980 chip->state = new_state;
986 * panic_nand_wait - [GENERIC] wait until the command is done
987 * @mtd: MTD device structure
988 * @chip: NAND chip structure
991 * Wait for command done. This is a helper function for nand_wait used when
992 * we are in interrupt context. May happen when in panic and trying to write
993 * an oops through mtdoops.
995 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
999 for (i = 0; i < timeo; i++) {
1000 if (chip->dev_ready) {
1001 if (chip->dev_ready(mtd))
1004 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1012 * nand_wait - [DEFAULT] wait until the command is done
1013 * @mtd: MTD device structure
1014 * @chip: NAND chip structure
1016 * Wait for command done. This applies to erase and program only. Erase can
1017 * take up to 400ms and program up to 20ms according to general NAND and
1020 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1023 int status, state = chip->state;
1024 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1026 led_trigger_event(nand_led_trigger, LED_FULL);
1029 * Apply this short delay always to ensure that we do wait tWB in any
1030 * case on any machine.
1034 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1037 if (in_interrupt() || oops_in_progress)
1038 panic_nand_wait(mtd, chip, timeo);
1040 timeo = jiffies + msecs_to_jiffies(timeo);
1041 while (time_before(jiffies, timeo)) {
1042 if (chip->dev_ready) {
1043 if (chip->dev_ready(mtd))
1046 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1053 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
1056 time_start = get_timer(0);
1057 while (get_timer(time_start) < timer) {
1058 if (chip->dev_ready) {
1059 if (chip->dev_ready(mtd))
1062 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1067 #ifdef PPCHAMELON_NAND_TIMER_HACK
1068 time_start = get_timer(0);
1069 while (get_timer(time_start) < 10)
1071 #endif /* PPCHAMELON_NAND_TIMER_HACK */
1072 led_trigger_event(nand_led_trigger, LED_OFF);
1074 status = (int)chip->read_byte(mtd);
1075 /* This can happen if in case of timeout or buggy dev_ready */
1076 WARN_ON(!(status & NAND_STATUS_READY));
1082 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1084 * @ofs: offset to start unlock from
1085 * @len: length to unlock
1086 * @invert: when = 0, unlock the range of blocks within the lower and
1087 * upper boundary address
1088 * when = 1, unlock the range of blocks outside the boundaries
1089 * of the lower and upper boundary address
1091 * Returs unlock status.
1093 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1094 uint64_t len, int invert)
1098 struct nand_chip *chip = mtd->priv;
1100 /* Submit address of first page to unlock */
1101 page = ofs >> chip->page_shift;
1102 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1104 /* Submit address of last page to unlock */
1105 page = (ofs + len) >> chip->page_shift;
1106 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1107 (page | invert) & chip->pagemask);
1109 /* Call wait ready function */
1110 status = chip->waitfunc(mtd, chip);
1111 /* See if device thinks it succeeded */
1112 if (status & NAND_STATUS_FAIL) {
1113 pr_debug("%s: error status = 0x%08x\n",
1122 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1124 * @ofs: offset to start unlock from
1125 * @len: length to unlock
1127 * Returns unlock status.
1129 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1133 struct nand_chip *chip = mtd->priv;
1135 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1136 __func__, (unsigned long long)ofs, len);
1138 if (check_offs_len(mtd, ofs, len))
1141 /* Align to last block address if size addresses end of the device */
1142 if (ofs + len == mtd->size)
1143 len -= mtd->erasesize;
1145 nand_get_device(mtd, FL_UNLOCKING);
1147 /* Shift to get chip number */
1148 chipnr = ofs >> chip->chip_shift;
1150 chip->select_chip(mtd, chipnr);
1152 /* Check, if it is write protected */
1153 if (nand_check_wp(mtd)) {
1154 pr_debug("%s: device is write protected!\n",
1160 ret = __nand_unlock(mtd, ofs, len, 0);
1163 chip->select_chip(mtd, -1);
1164 nand_release_device(mtd);
1168 EXPORT_SYMBOL(nand_unlock);
1171 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1173 * @ofs: offset to start unlock from
1174 * @len: length to unlock
1176 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1177 * have this feature, but it allows only to lock all blocks, not for specified
1178 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1181 * Returns lock status.
1183 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1186 int chipnr, status, page;
1187 struct nand_chip *chip = mtd->priv;
1189 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1190 __func__, (unsigned long long)ofs, len);
1192 if (check_offs_len(mtd, ofs, len))
1195 nand_get_device(mtd, FL_LOCKING);
1197 /* Shift to get chip number */
1198 chipnr = ofs >> chip->chip_shift;
1200 chip->select_chip(mtd, chipnr);
1202 /* Check, if it is write protected */
1203 if (nand_check_wp(mtd)) {
1204 pr_debug("%s: device is write protected!\n",
1206 status = MTD_ERASE_FAILED;
1211 /* Submit address of first page to lock */
1212 page = ofs >> chip->page_shift;
1213 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1215 /* Call wait ready function */
1216 status = chip->waitfunc(mtd, chip);
1217 /* See if device thinks it succeeded */
1218 if (status & NAND_STATUS_FAIL) {
1219 pr_debug("%s: error status = 0x%08x\n",
1225 ret = __nand_unlock(mtd, ofs, len, 0x1);
1228 chip->select_chip(mtd, -1);
1229 nand_release_device(mtd);
1233 EXPORT_SYMBOL(nand_lock);
1237 * nand_read_page_raw - [INTERN] read raw page data without ecc
1238 * @mtd: mtd info structure
1239 * @chip: nand chip info structure
1240 * @buf: buffer to store read data
1241 * @oob_required: caller requires OOB data read to chip->oob_poi
1242 * @page: page number to read
1244 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1246 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1247 uint8_t *buf, int oob_required, int page)
1249 chip->read_buf(mtd, buf, mtd->writesize);
1251 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1256 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1257 * @mtd: mtd info structure
1258 * @chip: nand chip info structure
1259 * @buf: buffer to store read data
1260 * @oob_required: caller requires OOB data read to chip->oob_poi
1261 * @page: page number to read
1263 * We need a special oob layout and handling even when OOB isn't used.
1265 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1266 struct nand_chip *chip, uint8_t *buf,
1267 int oob_required, int page)
1269 int eccsize = chip->ecc.size;
1270 int eccbytes = chip->ecc.bytes;
1271 uint8_t *oob = chip->oob_poi;
1274 for (steps = chip->ecc.steps; steps > 0; steps--) {
1275 chip->read_buf(mtd, buf, eccsize);
1278 if (chip->ecc.prepad) {
1279 chip->read_buf(mtd, oob, chip->ecc.prepad);
1280 oob += chip->ecc.prepad;
1283 chip->read_buf(mtd, oob, eccbytes);
1286 if (chip->ecc.postpad) {
1287 chip->read_buf(mtd, oob, chip->ecc.postpad);
1288 oob += chip->ecc.postpad;
1292 size = mtd->oobsize - (oob - chip->oob_poi);
1294 chip->read_buf(mtd, oob, size);
1300 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1301 * @mtd: mtd info structure
1302 * @chip: nand chip info structure
1303 * @buf: buffer to store read data
1304 * @oob_required: caller requires OOB data read to chip->oob_poi
1305 * @page: page number to read
1307 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1308 uint8_t *buf, int oob_required, int page)
1310 int i, eccsize = chip->ecc.size;
1311 int eccbytes = chip->ecc.bytes;
1312 int eccsteps = chip->ecc.steps;
1314 uint8_t *ecc_calc = chip->buffers->ecccalc;
1315 uint8_t *ecc_code = chip->buffers->ecccode;
1316 uint32_t *eccpos = chip->ecc.layout->eccpos;
1317 unsigned int max_bitflips = 0;
1319 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1321 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1322 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1324 for (i = 0; i < chip->ecc.total; i++)
1325 ecc_code[i] = chip->oob_poi[eccpos[i]];
1327 eccsteps = chip->ecc.steps;
1330 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1333 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1335 mtd->ecc_stats.failed++;
1337 mtd->ecc_stats.corrected += stat;
1338 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1341 return max_bitflips;
1345 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1346 * @mtd: mtd info structure
1347 * @chip: nand chip info structure
1348 * @data_offs: offset of requested data within the page
1349 * @readlen: data length
1350 * @bufpoi: buffer to store read data
1351 * @page: page number to read
1353 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1354 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1357 int start_step, end_step, num_steps;
1358 uint32_t *eccpos = chip->ecc.layout->eccpos;
1360 int data_col_addr, i, gaps = 0;
1361 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1362 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1364 unsigned int max_bitflips = 0;
1366 /* Column address within the page aligned to ECC size (256bytes) */
1367 start_step = data_offs / chip->ecc.size;
1368 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1369 num_steps = end_step - start_step + 1;
1370 index = start_step * chip->ecc.bytes;
1372 /* Data size aligned to ECC ecc.size */
1373 datafrag_len = num_steps * chip->ecc.size;
1374 eccfrag_len = num_steps * chip->ecc.bytes;
1376 data_col_addr = start_step * chip->ecc.size;
1377 /* If we read not a page aligned data */
1378 if (data_col_addr != 0)
1379 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1381 p = bufpoi + data_col_addr;
1382 chip->read_buf(mtd, p, datafrag_len);
1385 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1386 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1389 * The performance is faster if we position offsets according to
1390 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1392 for (i = 0; i < eccfrag_len - 1; i++) {
1393 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1394 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1400 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1401 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1404 * Send the command to read the particular ECC bytes take care
1405 * about buswidth alignment in read_buf.
1407 aligned_pos = eccpos[index] & ~(busw - 1);
1408 aligned_len = eccfrag_len;
1409 if (eccpos[index] & (busw - 1))
1411 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1414 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1415 mtd->writesize + aligned_pos, -1);
1416 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1419 for (i = 0; i < eccfrag_len; i++)
1420 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1422 p = bufpoi + data_col_addr;
1423 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1426 stat = chip->ecc.correct(mtd, p,
1427 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1429 mtd->ecc_stats.failed++;
1431 mtd->ecc_stats.corrected += stat;
1432 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1435 return max_bitflips;
1439 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1440 * @mtd: mtd info structure
1441 * @chip: nand chip info structure
1442 * @buf: buffer to store read data
1443 * @oob_required: caller requires OOB data read to chip->oob_poi
1444 * @page: page number to read
1446 * Not for syndrome calculating ECC controllers which need a special oob layout.
1448 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1449 uint8_t *buf, int oob_required, int page)
1451 int i, eccsize = chip->ecc.size;
1452 int eccbytes = chip->ecc.bytes;
1453 int eccsteps = chip->ecc.steps;
1455 uint8_t *ecc_calc = chip->buffers->ecccalc;
1456 uint8_t *ecc_code = chip->buffers->ecccode;
1457 uint32_t *eccpos = chip->ecc.layout->eccpos;
1458 unsigned int max_bitflips = 0;
1460 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1461 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1462 chip->read_buf(mtd, p, eccsize);
1463 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1465 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1467 for (i = 0; i < chip->ecc.total; i++)
1468 ecc_code[i] = chip->oob_poi[eccpos[i]];
1470 eccsteps = chip->ecc.steps;
1473 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1476 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1478 mtd->ecc_stats.failed++;
1480 mtd->ecc_stats.corrected += stat;
1481 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1484 return max_bitflips;
1488 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1489 * @mtd: mtd info structure
1490 * @chip: nand chip info structure
1491 * @buf: buffer to store read data
1492 * @oob_required: caller requires OOB data read to chip->oob_poi
1493 * @page: page number to read
1495 * Hardware ECC for large page chips, require OOB to be read first. For this
1496 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1497 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1498 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1499 * the data area, by overwriting the NAND manufacturer bad block markings.
1501 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1502 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1504 int i, eccsize = chip->ecc.size;
1505 int eccbytes = chip->ecc.bytes;
1506 int eccsteps = chip->ecc.steps;
1508 uint8_t *ecc_code = chip->buffers->ecccode;
1509 uint32_t *eccpos = chip->ecc.layout->eccpos;
1510 uint8_t *ecc_calc = chip->buffers->ecccalc;
1511 unsigned int max_bitflips = 0;
1513 /* Read the OOB area first */
1514 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1515 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1516 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1518 for (i = 0; i < chip->ecc.total; i++)
1519 ecc_code[i] = chip->oob_poi[eccpos[i]];
1521 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1524 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1525 chip->read_buf(mtd, p, eccsize);
1526 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1528 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1530 mtd->ecc_stats.failed++;
1532 mtd->ecc_stats.corrected += stat;
1533 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1536 return max_bitflips;
1540 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1541 * @mtd: mtd info structure
1542 * @chip: nand chip info structure
1543 * @buf: buffer to store read data
1544 * @oob_required: caller requires OOB data read to chip->oob_poi
1545 * @page: page number to read
1547 * The hw generator calculates the error syndrome automatically. Therefore we
1548 * need a special oob layout and handling.
1550 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1551 uint8_t *buf, int oob_required, int page)
1553 int i, eccsize = chip->ecc.size;
1554 int eccbytes = chip->ecc.bytes;
1555 int eccsteps = chip->ecc.steps;
1557 uint8_t *oob = chip->oob_poi;
1558 unsigned int max_bitflips = 0;
1560 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1563 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1564 chip->read_buf(mtd, p, eccsize);
1566 if (chip->ecc.prepad) {
1567 chip->read_buf(mtd, oob, chip->ecc.prepad);
1568 oob += chip->ecc.prepad;
1571 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1572 chip->read_buf(mtd, oob, eccbytes);
1573 stat = chip->ecc.correct(mtd, p, oob, NULL);
1576 mtd->ecc_stats.failed++;
1578 mtd->ecc_stats.corrected += stat;
1579 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1584 if (chip->ecc.postpad) {
1585 chip->read_buf(mtd, oob, chip->ecc.postpad);
1586 oob += chip->ecc.postpad;
1590 /* Calculate remaining oob bytes */
1591 i = mtd->oobsize - (oob - chip->oob_poi);
1593 chip->read_buf(mtd, oob, i);
1595 return max_bitflips;
1599 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1600 * @chip: nand chip structure
1601 * @oob: oob destination address
1602 * @ops: oob ops structure
1603 * @len: size of oob to transfer
1605 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1606 struct mtd_oob_ops *ops, size_t len)
1608 switch (ops->mode) {
1610 case MTD_OPS_PLACE_OOB:
1612 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1615 case MTD_OPS_AUTO_OOB: {
1616 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1617 uint32_t boffs = 0, roffs = ops->ooboffs;
1620 for (; free->length && len; free++, len -= bytes) {
1621 /* Read request not from offset 0? */
1622 if (unlikely(roffs)) {
1623 if (roffs >= free->length) {
1624 roffs -= free->length;
1627 boffs = free->offset + roffs;
1628 bytes = min_t(size_t, len,
1629 (free->length - roffs));
1632 bytes = min_t(size_t, len, free->length);
1633 boffs = free->offset;
1635 memcpy(oob, chip->oob_poi + boffs, bytes);
1647 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1648 * @mtd: MTD device structure
1649 * @retry_mode: the retry mode to use
1651 * Some vendors supply a special command to shift the Vt threshold, to be used
1652 * when there are too many bitflips in a page (i.e., ECC error). After setting
1653 * a new threshold, the host should retry reading the page.
1655 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1657 struct nand_chip *chip = mtd->priv;
1659 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1661 if (retry_mode >= chip->read_retries)
1664 if (!chip->setup_read_retry)
1667 return chip->setup_read_retry(mtd, retry_mode);
1671 * nand_do_read_ops - [INTERN] Read data with ECC
1672 * @mtd: MTD device structure
1673 * @from: offset to read from
1674 * @ops: oob ops structure
1676 * Internal function. Called with chip held.
1678 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1679 struct mtd_oob_ops *ops)
1681 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1682 struct nand_chip *chip = mtd->priv;
1684 uint32_t readlen = ops->len;
1685 uint32_t oobreadlen = ops->ooblen;
1686 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1687 mtd->oobavail : mtd->oobsize;
1689 uint8_t *bufpoi, *oob, *buf;
1690 unsigned int max_bitflips = 0;
1692 bool ecc_fail = false;
1694 chipnr = (int)(from >> chip->chip_shift);
1695 chip->select_chip(mtd, chipnr);
1697 realpage = (int)(from >> chip->page_shift);
1698 page = realpage & chip->pagemask;
1700 col = (int)(from & (mtd->writesize - 1));
1704 oob_required = oob ? 1 : 0;
1707 unsigned int ecc_failures = mtd->ecc_stats.failed;
1710 bytes = min(mtd->writesize - col, readlen);
1711 aligned = (bytes == mtd->writesize);
1713 /* Is the current page in the buffer? */
1714 if (realpage != chip->pagebuf || oob) {
1715 bufpoi = aligned ? buf : chip->buffers->databuf;
1718 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1721 * Now read the page into the buffer. Absent an error,
1722 * the read methods return max bitflips per ecc step.
1724 if (unlikely(ops->mode == MTD_OPS_RAW))
1725 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1728 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1730 ret = chip->ecc.read_subpage(mtd, chip,
1734 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1735 oob_required, page);
1738 /* Invalidate page cache */
1743 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1745 /* Transfer not aligned data */
1747 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1748 !(mtd->ecc_stats.failed - ecc_failures) &&
1749 (ops->mode != MTD_OPS_RAW)) {
1750 chip->pagebuf = realpage;
1751 chip->pagebuf_bitflips = ret;
1753 /* Invalidate page cache */
1756 memcpy(buf, chip->buffers->databuf + col, bytes);
1759 if (unlikely(oob)) {
1760 int toread = min(oobreadlen, max_oobsize);
1763 oob = nand_transfer_oob(chip,
1765 oobreadlen -= toread;
1769 if (chip->options & NAND_NEED_READRDY) {
1770 /* Apply delay or wait for ready/busy pin */
1771 if (!chip->dev_ready)
1772 udelay(chip->chip_delay);
1774 nand_wait_ready(mtd);
1777 if (mtd->ecc_stats.failed - ecc_failures) {
1778 if (retry_mode + 1 < chip->read_retries) {
1780 ret = nand_setup_read_retry(mtd,
1785 /* Reset failures; retry */
1786 mtd->ecc_stats.failed = ecc_failures;
1789 /* No more retry modes; real failure */
1796 memcpy(buf, chip->buffers->databuf + col, bytes);
1798 max_bitflips = max_t(unsigned int, max_bitflips,
1799 chip->pagebuf_bitflips);
1804 /* Reset to retry mode 0 */
1806 ret = nand_setup_read_retry(mtd, 0);
1815 /* For subsequent reads align to page boundary */
1817 /* Increment page address */
1820 page = realpage & chip->pagemask;
1821 /* Check, if we cross a chip boundary */
1824 chip->select_chip(mtd, -1);
1825 chip->select_chip(mtd, chipnr);
1828 chip->select_chip(mtd, -1);
1830 ops->retlen = ops->len - (size_t) readlen;
1832 ops->oobretlen = ops->ooblen - oobreadlen;
1840 return max_bitflips;
1844 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1845 * @mtd: MTD device structure
1846 * @from: offset to read from
1847 * @len: number of bytes to read
1848 * @retlen: pointer to variable to store the number of read bytes
1849 * @buf: the databuffer to put data
1851 * Get hold of the chip and call nand_do_read.
1853 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1854 size_t *retlen, uint8_t *buf)
1856 struct mtd_oob_ops ops;
1859 nand_get_device(mtd, FL_READING);
1863 ops.mode = MTD_OPS_PLACE_OOB;
1864 ret = nand_do_read_ops(mtd, from, &ops);
1865 *retlen = ops.retlen;
1866 nand_release_device(mtd);
1871 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1872 * @mtd: mtd info structure
1873 * @chip: nand chip info structure
1874 * @page: page number to read
1876 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1879 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1880 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1885 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1887 * @mtd: mtd info structure
1888 * @chip: nand chip info structure
1889 * @page: page number to read
1891 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1894 uint8_t *buf = chip->oob_poi;
1895 int length = mtd->oobsize;
1896 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1897 int eccsize = chip->ecc.size;
1898 uint8_t *bufpoi = buf;
1899 int i, toread, sndrnd = 0, pos;
1901 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1902 for (i = 0; i < chip->ecc.steps; i++) {
1904 pos = eccsize + i * (eccsize + chunk);
1905 if (mtd->writesize > 512)
1906 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1908 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1911 toread = min_t(int, length, chunk);
1912 chip->read_buf(mtd, bufpoi, toread);
1917 chip->read_buf(mtd, bufpoi, length);
1923 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1924 * @mtd: mtd info structure
1925 * @chip: nand chip info structure
1926 * @page: page number to write
1928 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1932 const uint8_t *buf = chip->oob_poi;
1933 int length = mtd->oobsize;
1935 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1936 chip->write_buf(mtd, buf, length);
1937 /* Send command to program the OOB data */
1938 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1940 status = chip->waitfunc(mtd, chip);
1942 return status & NAND_STATUS_FAIL ? -EIO : 0;
1946 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1947 * with syndrome - only for large page flash
1948 * @mtd: mtd info structure
1949 * @chip: nand chip info structure
1950 * @page: page number to write
1952 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1953 struct nand_chip *chip, int page)
1955 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1956 int eccsize = chip->ecc.size, length = mtd->oobsize;
1957 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1958 const uint8_t *bufpoi = chip->oob_poi;
1961 * data-ecc-data-ecc ... ecc-oob
1963 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1965 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1966 pos = steps * (eccsize + chunk);
1971 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1972 for (i = 0; i < steps; i++) {
1974 if (mtd->writesize <= 512) {
1975 uint32_t fill = 0xFFFFFFFF;
1979 int num = min_t(int, len, 4);
1980 chip->write_buf(mtd, (uint8_t *)&fill,
1985 pos = eccsize + i * (eccsize + chunk);
1986 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1990 len = min_t(int, length, chunk);
1991 chip->write_buf(mtd, bufpoi, len);
1996 chip->write_buf(mtd, bufpoi, length);
1998 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1999 status = chip->waitfunc(mtd, chip);
2001 return status & NAND_STATUS_FAIL ? -EIO : 0;
2005 * nand_do_read_oob - [INTERN] NAND read out-of-band
2006 * @mtd: MTD device structure
2007 * @from: offset to read from
2008 * @ops: oob operations description structure
2010 * NAND read out-of-band data from the spare area.
2012 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2013 struct mtd_oob_ops *ops)
2015 int page, realpage, chipnr;
2016 struct nand_chip *chip = mtd->priv;
2017 struct mtd_ecc_stats stats;
2018 int readlen = ops->ooblen;
2020 uint8_t *buf = ops->oobbuf;
2023 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2024 __func__, (unsigned long long)from, readlen);
2026 stats = mtd->ecc_stats;
2028 if (ops->mode == MTD_OPS_AUTO_OOB)
2029 len = chip->ecc.layout->oobavail;
2033 if (unlikely(ops->ooboffs >= len)) {
2034 pr_debug("%s: attempt to start read outside oob\n",
2039 /* Do not allow reads past end of device */
2040 if (unlikely(from >= mtd->size ||
2041 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2042 (from >> chip->page_shift)) * len)) {
2043 pr_debug("%s: attempt to read beyond end of device\n",
2048 chipnr = (int)(from >> chip->chip_shift);
2049 chip->select_chip(mtd, chipnr);
2051 /* Shift to get page */
2052 realpage = (int)(from >> chip->page_shift);
2053 page = realpage & chip->pagemask;
2058 if (ops->mode == MTD_OPS_RAW)
2059 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2061 ret = chip->ecc.read_oob(mtd, chip, page);
2066 len = min(len, readlen);
2067 buf = nand_transfer_oob(chip, buf, ops, len);
2069 if (chip->options & NAND_NEED_READRDY) {
2070 /* Apply delay or wait for ready/busy pin */
2071 if (!chip->dev_ready)
2072 udelay(chip->chip_delay);
2074 nand_wait_ready(mtd);
2081 /* Increment page address */
2084 page = realpage & chip->pagemask;
2085 /* Check, if we cross a chip boundary */
2088 chip->select_chip(mtd, -1);
2089 chip->select_chip(mtd, chipnr);
2092 chip->select_chip(mtd, -1);
2094 ops->oobretlen = ops->ooblen - readlen;
2099 if (mtd->ecc_stats.failed - stats.failed)
2102 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2106 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2107 * @mtd: MTD device structure
2108 * @from: offset to read from
2109 * @ops: oob operation description structure
2111 * NAND read data and/or out-of-band data.
2113 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2114 struct mtd_oob_ops *ops)
2116 int ret = -ENOTSUPP;
2120 /* Do not allow reads past end of device */
2121 if (ops->datbuf && (from + ops->len) > mtd->size) {
2122 pr_debug("%s: attempt to read beyond end of device\n",
2127 nand_get_device(mtd, FL_READING);
2129 switch (ops->mode) {
2130 case MTD_OPS_PLACE_OOB:
2131 case MTD_OPS_AUTO_OOB:
2140 ret = nand_do_read_oob(mtd, from, ops);
2142 ret = nand_do_read_ops(mtd, from, ops);
2145 nand_release_device(mtd);
2151 * nand_write_page_raw - [INTERN] raw page write function
2152 * @mtd: mtd info structure
2153 * @chip: nand chip info structure
2155 * @oob_required: must write chip->oob_poi to OOB
2157 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2159 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2160 const uint8_t *buf, int oob_required)
2162 chip->write_buf(mtd, buf, mtd->writesize);
2164 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2170 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2171 * @mtd: mtd info structure
2172 * @chip: nand chip info structure
2174 * @oob_required: must write chip->oob_poi to OOB
2176 * We need a special oob layout and handling even when ECC isn't checked.
2178 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2179 struct nand_chip *chip,
2180 const uint8_t *buf, int oob_required)
2182 int eccsize = chip->ecc.size;
2183 int eccbytes = chip->ecc.bytes;
2184 uint8_t *oob = chip->oob_poi;
2187 for (steps = chip->ecc.steps; steps > 0; steps--) {
2188 chip->write_buf(mtd, buf, eccsize);
2191 if (chip->ecc.prepad) {
2192 chip->write_buf(mtd, oob, chip->ecc.prepad);
2193 oob += chip->ecc.prepad;
2196 chip->write_buf(mtd, oob, eccbytes);
2199 if (chip->ecc.postpad) {
2200 chip->write_buf(mtd, oob, chip->ecc.postpad);
2201 oob += chip->ecc.postpad;
2205 size = mtd->oobsize - (oob - chip->oob_poi);
2207 chip->write_buf(mtd, oob, size);
2212 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2213 * @mtd: mtd info structure
2214 * @chip: nand chip info structure
2216 * @oob_required: must write chip->oob_poi to OOB
2218 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2219 const uint8_t *buf, int oob_required)
2221 int i, eccsize = chip->ecc.size;
2222 int eccbytes = chip->ecc.bytes;
2223 int eccsteps = chip->ecc.steps;
2224 uint8_t *ecc_calc = chip->buffers->ecccalc;
2225 const uint8_t *p = buf;
2226 uint32_t *eccpos = chip->ecc.layout->eccpos;
2228 /* Software ECC calculation */
2229 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2230 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2232 for (i = 0; i < chip->ecc.total; i++)
2233 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2235 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2239 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2240 * @mtd: mtd info structure
2241 * @chip: nand chip info structure
2243 * @oob_required: must write chip->oob_poi to OOB
2245 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2246 const uint8_t *buf, int oob_required)
2248 int i, eccsize = chip->ecc.size;
2249 int eccbytes = chip->ecc.bytes;
2250 int eccsteps = chip->ecc.steps;
2251 uint8_t *ecc_calc = chip->buffers->ecccalc;
2252 const uint8_t *p = buf;
2253 uint32_t *eccpos = chip->ecc.layout->eccpos;
2255 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2256 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2257 chip->write_buf(mtd, p, eccsize);
2258 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2261 for (i = 0; i < chip->ecc.total; i++)
2262 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2264 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2271 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2272 * @mtd: mtd info structure
2273 * @chip: nand chip info structure
2274 * @offset: column address of subpage within the page
2275 * @data_len: data length
2277 * @oob_required: must write chip->oob_poi to OOB
2279 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2280 struct nand_chip *chip, uint32_t offset,
2281 uint32_t data_len, const uint8_t *buf,
2284 uint8_t *oob_buf = chip->oob_poi;
2285 uint8_t *ecc_calc = chip->buffers->ecccalc;
2286 int ecc_size = chip->ecc.size;
2287 int ecc_bytes = chip->ecc.bytes;
2288 int ecc_steps = chip->ecc.steps;
2289 uint32_t *eccpos = chip->ecc.layout->eccpos;
2290 uint32_t start_step = offset / ecc_size;
2291 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2292 int oob_bytes = mtd->oobsize / ecc_steps;
2295 for (step = 0; step < ecc_steps; step++) {
2296 /* configure controller for WRITE access */
2297 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2299 /* write data (untouched subpages already masked by 0xFF) */
2300 chip->write_buf(mtd, buf, ecc_size);
2302 /* mask ECC of un-touched subpages by padding 0xFF */
2303 if ((step < start_step) || (step > end_step))
2304 memset(ecc_calc, 0xff, ecc_bytes);
2306 chip->ecc.calculate(mtd, buf, ecc_calc);
2308 /* mask OOB of un-touched subpages by padding 0xFF */
2309 /* if oob_required, preserve OOB metadata of written subpage */
2310 if (!oob_required || (step < start_step) || (step > end_step))
2311 memset(oob_buf, 0xff, oob_bytes);
2314 ecc_calc += ecc_bytes;
2315 oob_buf += oob_bytes;
2318 /* copy calculated ECC for whole page to chip->buffer->oob */
2319 /* this include masked-value(0xFF) for unwritten subpages */
2320 ecc_calc = chip->buffers->ecccalc;
2321 for (i = 0; i < chip->ecc.total; i++)
2322 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2324 /* write OOB buffer to NAND device */
2325 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2332 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2333 * @mtd: mtd info structure
2334 * @chip: nand chip info structure
2336 * @oob_required: must write chip->oob_poi to OOB
2338 * The hw generator calculates the error syndrome automatically. Therefore we
2339 * need a special oob layout and handling.
2341 static int nand_write_page_syndrome(struct mtd_info *mtd,
2342 struct nand_chip *chip,
2343 const uint8_t *buf, int oob_required)
2345 int i, eccsize = chip->ecc.size;
2346 int eccbytes = chip->ecc.bytes;
2347 int eccsteps = chip->ecc.steps;
2348 const uint8_t *p = buf;
2349 uint8_t *oob = chip->oob_poi;
2351 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2353 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2354 chip->write_buf(mtd, p, eccsize);
2356 if (chip->ecc.prepad) {
2357 chip->write_buf(mtd, oob, chip->ecc.prepad);
2358 oob += chip->ecc.prepad;
2361 chip->ecc.calculate(mtd, p, oob);
2362 chip->write_buf(mtd, oob, eccbytes);
2365 if (chip->ecc.postpad) {
2366 chip->write_buf(mtd, oob, chip->ecc.postpad);
2367 oob += chip->ecc.postpad;
2371 /* Calculate remaining oob bytes */
2372 i = mtd->oobsize - (oob - chip->oob_poi);
2374 chip->write_buf(mtd, oob, i);
2380 * nand_write_page - [REPLACEABLE] write one page
2381 * @mtd: MTD device structure
2382 * @chip: NAND chip descriptor
2383 * @offset: address offset within the page
2384 * @data_len: length of actual data to be written
2385 * @buf: the data to write
2386 * @oob_required: must write chip->oob_poi to OOB
2387 * @page: page number to write
2388 * @cached: cached programming
2389 * @raw: use _raw version of write_page
2391 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2392 uint32_t offset, int data_len, const uint8_t *buf,
2393 int oob_required, int page, int cached, int raw)
2395 int status, subpage;
2397 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2398 chip->ecc.write_subpage)
2399 subpage = offset || (data_len < mtd->writesize);
2403 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2406 status = chip->ecc.write_page_raw(mtd, chip, buf,
2409 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2412 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2418 * Cached progamming disabled for now. Not sure if it's worth the
2419 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2423 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2425 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2426 status = chip->waitfunc(mtd, chip);
2428 * See if operation failed and additional status checks are
2431 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2432 status = chip->errstat(mtd, chip, FL_WRITING, status,
2435 if (status & NAND_STATUS_FAIL)
2438 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2439 status = chip->waitfunc(mtd, chip);
2444 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
2445 /* Send command to read back the data */
2446 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2448 if (chip->verify_buf(mtd, buf, mtd->writesize))
2451 /* Make sure the next page prog is preceded by a status read */
2452 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2460 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2461 * @mtd: MTD device structure
2462 * @oob: oob data buffer
2463 * @len: oob data write length
2464 * @ops: oob ops structure
2466 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2467 struct mtd_oob_ops *ops)
2469 struct nand_chip *chip = mtd->priv;
2472 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2473 * data from a previous OOB read.
2475 memset(chip->oob_poi, 0xff, mtd->oobsize);
2477 switch (ops->mode) {
2479 case MTD_OPS_PLACE_OOB:
2481 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2484 case MTD_OPS_AUTO_OOB: {
2485 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2486 uint32_t boffs = 0, woffs = ops->ooboffs;
2489 for (; free->length && len; free++, len -= bytes) {
2490 /* Write request not from offset 0? */
2491 if (unlikely(woffs)) {
2492 if (woffs >= free->length) {
2493 woffs -= free->length;
2496 boffs = free->offset + woffs;
2497 bytes = min_t(size_t, len,
2498 (free->length - woffs));
2501 bytes = min_t(size_t, len, free->length);
2502 boffs = free->offset;
2504 memcpy(chip->oob_poi + boffs, oob, bytes);
2515 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2518 * nand_do_write_ops - [INTERN] NAND write with ECC
2519 * @mtd: MTD device structure
2520 * @to: offset to write to
2521 * @ops: oob operations description structure
2523 * NAND write with ECC.
2525 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2526 struct mtd_oob_ops *ops)
2528 int chipnr, realpage, page, blockmask, column;
2529 struct nand_chip *chip = mtd->priv;
2530 uint32_t writelen = ops->len;
2532 uint32_t oobwritelen = ops->ooblen;
2533 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2534 mtd->oobavail : mtd->oobsize;
2536 uint8_t *oob = ops->oobbuf;
2537 uint8_t *buf = ops->datbuf;
2539 int oob_required = oob ? 1 : 0;
2546 /* Reject writes, which are not page aligned */
2547 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2549 /* Reject writes, which are not page aligned */
2550 if (NOTALIGNED(to)) {
2552 pr_notice("%s: attempt to write non page aligned data\n",
2557 column = to & (mtd->writesize - 1);
2559 chipnr = (int)(to >> chip->chip_shift);
2560 chip->select_chip(mtd, chipnr);
2562 /* Check, if it is write protected */
2563 if (nand_check_wp(mtd)) {
2568 realpage = (int)(to >> chip->page_shift);
2569 page = realpage & chip->pagemask;
2570 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2572 /* Invalidate the page cache, when we write to the cached page */
2573 if (to <= (chip->pagebuf << chip->page_shift) &&
2574 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2577 /* Don't allow multipage oob writes with offset */
2578 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2584 int bytes = mtd->writesize;
2585 int cached = writelen > bytes && page != blockmask;
2586 uint8_t *wbuf = buf;
2589 /* Partial page write? */
2590 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2592 bytes = min_t(int, bytes - column, (int) writelen);
2594 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2595 memcpy(&chip->buffers->databuf[column], buf, bytes);
2596 wbuf = chip->buffers->databuf;
2599 if (unlikely(oob)) {
2600 size_t len = min(oobwritelen, oobmaxlen);
2601 oob = nand_fill_oob(mtd, oob, len, ops);
2604 /* We still need to erase leftover OOB data */
2605 memset(chip->oob_poi, 0xff, mtd->oobsize);
2607 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2608 oob_required, page, cached,
2609 (ops->mode == MTD_OPS_RAW));
2621 page = realpage & chip->pagemask;
2622 /* Check, if we cross a chip boundary */
2625 chip->select_chip(mtd, -1);
2626 chip->select_chip(mtd, chipnr);
2630 ops->retlen = ops->len - writelen;
2632 ops->oobretlen = ops->ooblen;
2635 chip->select_chip(mtd, -1);
2640 * panic_nand_write - [MTD Interface] NAND write with ECC
2641 * @mtd: MTD device structure
2642 * @to: offset to write to
2643 * @len: number of bytes to write
2644 * @retlen: pointer to variable to store the number of written bytes
2645 * @buf: the data to write
2647 * NAND write with ECC. Used when performing writes in interrupt context, this
2648 * may for example be called by mtdoops when writing an oops while in panic.
2650 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2651 size_t *retlen, const uint8_t *buf)
2653 struct nand_chip *chip = mtd->priv;
2654 struct mtd_oob_ops ops;
2657 /* Wait for the device to get ready */
2658 panic_nand_wait(mtd, chip, 400);
2660 /* Grab the device */
2661 panic_nand_get_device(chip, mtd, FL_WRITING);
2664 ops.datbuf = (uint8_t *)buf;
2666 ops.mode = MTD_OPS_PLACE_OOB;
2668 ret = nand_do_write_ops(mtd, to, &ops);
2670 *retlen = ops.retlen;
2675 * nand_write - [MTD Interface] NAND write with ECC
2676 * @mtd: MTD device structure
2677 * @to: offset to write to
2678 * @len: number of bytes to write
2679 * @retlen: pointer to variable to store the number of written bytes
2680 * @buf: the data to write
2682 * NAND write with ECC.
2684 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2685 size_t *retlen, const uint8_t *buf)
2687 struct mtd_oob_ops ops;
2690 nand_get_device(mtd, FL_WRITING);
2692 ops.datbuf = (uint8_t *)buf;
2694 ops.mode = MTD_OPS_PLACE_OOB;
2695 ret = nand_do_write_ops(mtd, to, &ops);
2696 *retlen = ops.retlen;
2697 nand_release_device(mtd);
2702 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2703 * @mtd: MTD device structure
2704 * @to: offset to write to
2705 * @ops: oob operation description structure
2707 * NAND write out-of-band.
2709 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2710 struct mtd_oob_ops *ops)
2712 int chipnr, page, status, len;
2713 struct nand_chip *chip = mtd->priv;
2715 pr_debug("%s: to = 0x%08x, len = %i\n",
2716 __func__, (unsigned int)to, (int)ops->ooblen);
2718 if (ops->mode == MTD_OPS_AUTO_OOB)
2719 len = chip->ecc.layout->oobavail;
2723 /* Do not allow write past end of page */
2724 if ((ops->ooboffs + ops->ooblen) > len) {
2725 pr_debug("%s: attempt to write past end of page\n",
2730 if (unlikely(ops->ooboffs >= len)) {
2731 pr_debug("%s: attempt to start write outside oob\n",
2736 /* Do not allow write past end of device */
2737 if (unlikely(to >= mtd->size ||
2738 ops->ooboffs + ops->ooblen >
2739 ((mtd->size >> chip->page_shift) -
2740 (to >> chip->page_shift)) * len)) {
2741 pr_debug("%s: attempt to write beyond end of device\n",
2746 chipnr = (int)(to >> chip->chip_shift);
2747 chip->select_chip(mtd, chipnr);
2749 /* Shift to get page */
2750 page = (int)(to >> chip->page_shift);
2753 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2754 * of my DiskOnChip 2000 test units) will clear the whole data page too
2755 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2756 * it in the doc2000 driver in August 1999. dwmw2.
2758 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2760 /* Check, if it is write protected */
2761 if (nand_check_wp(mtd)) {
2762 chip->select_chip(mtd, -1);
2766 /* Invalidate the page cache, if we write to the cached page */
2767 if (page == chip->pagebuf)
2770 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2772 if (ops->mode == MTD_OPS_RAW)
2773 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2775 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2777 chip->select_chip(mtd, -1);
2782 ops->oobretlen = ops->ooblen;
2788 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2789 * @mtd: MTD device structure
2790 * @to: offset to write to
2791 * @ops: oob operation description structure
2793 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2794 struct mtd_oob_ops *ops)
2796 int ret = -ENOTSUPP;
2800 /* Do not allow writes past end of device */
2801 if (ops->datbuf && (to + ops->len) > mtd->size) {
2802 pr_debug("%s: attempt to write beyond end of device\n",
2807 nand_get_device(mtd, FL_WRITING);
2809 switch (ops->mode) {
2810 case MTD_OPS_PLACE_OOB:
2811 case MTD_OPS_AUTO_OOB:
2820 ret = nand_do_write_oob(mtd, to, ops);
2822 ret = nand_do_write_ops(mtd, to, ops);
2825 nand_release_device(mtd);
2830 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2831 * @mtd: MTD device structure
2832 * @page: the page address of the block which will be erased
2834 * Standard erase command for NAND chips.
2836 static void single_erase_cmd(struct mtd_info *mtd, int page)
2838 struct nand_chip *chip = mtd->priv;
2839 /* Send commands to erase a block */
2840 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2841 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2845 * nand_erase - [MTD Interface] erase block(s)
2846 * @mtd: MTD device structure
2847 * @instr: erase instruction
2849 * Erase one ore more blocks.
2851 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2853 return nand_erase_nand(mtd, instr, 0);
2857 * nand_erase_nand - [INTERN] erase block(s)
2858 * @mtd: MTD device structure
2859 * @instr: erase instruction
2860 * @allowbbt: allow erasing the bbt area
2862 * Erase one ore more blocks.
2864 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2867 int page, status, pages_per_block, ret, chipnr;
2868 struct nand_chip *chip = mtd->priv;
2871 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2872 __func__, (unsigned long long)instr->addr,
2873 (unsigned long long)instr->len);
2875 if (check_offs_len(mtd, instr->addr, instr->len))
2878 /* Grab the lock and see if the device is available */
2879 nand_get_device(mtd, FL_ERASING);
2881 /* Shift to get first page */
2882 page = (int)(instr->addr >> chip->page_shift);
2883 chipnr = (int)(instr->addr >> chip->chip_shift);
2885 /* Calculate pages in each block */
2886 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2888 /* Select the NAND device */
2889 chip->select_chip(mtd, chipnr);
2891 /* Check, if it is write protected */
2892 if (nand_check_wp(mtd)) {
2893 pr_debug("%s: device is write protected!\n",
2895 instr->state = MTD_ERASE_FAILED;
2899 /* Loop through the pages */
2902 instr->state = MTD_ERASING;
2907 /* Check if we have a bad block, we do not erase bad blocks! */
2908 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2909 chip->page_shift, 0, allowbbt)) {
2910 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2912 instr->state = MTD_ERASE_FAILED;
2917 * Invalidate the page cache, if we erase the block which
2918 * contains the current cached page.
2920 if (page <= chip->pagebuf && chip->pagebuf <
2921 (page + pages_per_block))
2924 chip->erase_cmd(mtd, page & chip->pagemask);
2926 status = chip->waitfunc(mtd, chip);
2929 * See if operation failed and additional status checks are
2932 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2933 status = chip->errstat(mtd, chip, FL_ERASING,
2936 /* See if block erase succeeded */
2937 if (status & NAND_STATUS_FAIL) {
2938 pr_debug("%s: failed erase, page 0x%08x\n",
2940 instr->state = MTD_ERASE_FAILED;
2942 ((loff_t)page << chip->page_shift);
2946 /* Increment page address and decrement length */
2947 len -= (1ULL << chip->phys_erase_shift);
2948 page += pages_per_block;
2950 /* Check, if we cross a chip boundary */
2951 if (len && !(page & chip->pagemask)) {
2953 chip->select_chip(mtd, -1);
2954 chip->select_chip(mtd, chipnr);
2957 instr->state = MTD_ERASE_DONE;
2961 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2963 /* Deselect and wake up anyone waiting on the device */
2964 chip->select_chip(mtd, -1);
2965 nand_release_device(mtd);
2967 /* Do call back function */
2969 mtd_erase_callback(instr);
2971 /* Return more or less happy */
2976 * nand_sync - [MTD Interface] sync
2977 * @mtd: MTD device structure
2979 * Sync is actually a wait for chip ready function.
2981 static void nand_sync(struct mtd_info *mtd)
2983 pr_debug("%s: called\n", __func__);
2985 /* Grab the lock and see if the device is available */
2986 nand_get_device(mtd, FL_SYNCING);
2987 /* Release it and go back */
2988 nand_release_device(mtd);
2992 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2993 * @mtd: MTD device structure
2994 * @offs: offset relative to mtd start
2996 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2998 return nand_block_checkbad(mtd, offs, 1, 0);
3002 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3003 * @mtd: MTD device structure
3004 * @ofs: offset relative to mtd start
3006 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3010 ret = nand_block_isbad(mtd, ofs);
3012 /* If it was bad already, return success and do nothing */
3018 return nand_block_markbad_lowlevel(mtd, ofs);
3022 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3023 * @mtd: MTD device structure
3024 * @chip: nand chip info structure
3025 * @addr: feature address.
3026 * @subfeature_param: the subfeature parameters, a four bytes array.
3028 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3029 int addr, uint8_t *subfeature_param)
3034 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3035 if (!chip->onfi_version ||
3036 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3037 & ONFI_OPT_CMD_SET_GET_FEATURES))
3041 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3042 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3043 chip->write_byte(mtd, subfeature_param[i]);
3045 status = chip->waitfunc(mtd, chip);
3046 if (status & NAND_STATUS_FAIL)
3052 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3053 * @mtd: MTD device structure
3054 * @chip: nand chip info structure
3055 * @addr: feature address.
3056 * @subfeature_param: the subfeature parameters, a four bytes array.
3058 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3059 int addr, uint8_t *subfeature_param)
3063 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3064 if (!chip->onfi_version ||
3065 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3066 & ONFI_OPT_CMD_SET_GET_FEATURES))
3070 /* clear the sub feature parameters */
3071 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3073 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3074 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3075 *subfeature_param++ = chip->read_byte(mtd);
3081 * nand_suspend - [MTD Interface] Suspend the NAND flash
3082 * @mtd: MTD device structure
3084 static int nand_suspend(struct mtd_info *mtd)
3086 return nand_get_device(mtd, FL_PM_SUSPENDED);
3090 * nand_resume - [MTD Interface] Resume the NAND flash
3091 * @mtd: MTD device structure
3093 static void nand_resume(struct mtd_info *mtd)
3095 struct nand_chip *chip = mtd->priv;
3097 if (chip->state == FL_PM_SUSPENDED)
3098 nand_release_device(mtd);
3100 pr_err("%s called for a chip which is not in suspended state\n",
3105 /* Set default functions */
3106 static void nand_set_defaults(struct nand_chip *chip, int busw)
3108 /* check for proper chip_delay setup, set 20us if not */
3109 if (!chip->chip_delay)
3110 chip->chip_delay = 20;
3112 /* check, if a user supplied command function given */
3113 if (chip->cmdfunc == NULL)
3114 chip->cmdfunc = nand_command;
3116 /* check, if a user supplied wait function given */
3117 if (chip->waitfunc == NULL)
3118 chip->waitfunc = nand_wait;
3120 if (!chip->select_chip)
3121 chip->select_chip = nand_select_chip;
3123 /* set for ONFI nand */
3124 if (!chip->onfi_set_features)
3125 chip->onfi_set_features = nand_onfi_set_features;
3126 if (!chip->onfi_get_features)
3127 chip->onfi_get_features = nand_onfi_get_features;
3129 /* If called twice, pointers that depend on busw may need to be reset */
3130 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3131 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3132 if (!chip->read_word)
3133 chip->read_word = nand_read_word;
3134 if (!chip->block_bad)
3135 chip->block_bad = nand_block_bad;
3136 if (!chip->block_markbad)
3137 chip->block_markbad = nand_default_block_markbad;
3138 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3139 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3140 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3141 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3142 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3143 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3144 if (!chip->scan_bbt)
3145 chip->scan_bbt = nand_default_bbt;
3147 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
3148 if (!chip->verify_buf)
3149 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
3153 if (!chip->controller) {
3154 chip->controller = &chip->hwcontrol;
3155 spin_lock_init(&chip->controller->lock);
3156 init_waitqueue_head(&chip->controller->wq);
3161 /* Sanitize ONFI strings so we can safely print them */
3163 static void sanitize_string(uint8_t *s, size_t len)
3165 static void sanitize_string(char *s, size_t len)
3170 /* Null terminate */
3173 /* Remove non printable chars */
3174 for (i = 0; i < len - 1; i++) {
3175 if (s[i] < ' ' || s[i] > 127)
3179 /* Remove trailing spaces */
3183 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3188 for (i = 0; i < 8; i++)
3189 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3195 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3196 /* Parse the Extended Parameter Page. */
3197 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3198 struct nand_chip *chip, struct nand_onfi_params *p)
3200 struct onfi_ext_param_page *ep;
3201 struct onfi_ext_section *s;
3202 struct onfi_ext_ecc_info *ecc;
3208 len = le16_to_cpu(p->ext_param_page_length) * 16;
3209 ep = kmalloc(len, GFP_KERNEL);
3213 /* Send our own NAND_CMD_PARAM. */
3214 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3216 /* Use the Change Read Column command to skip the ONFI param pages. */
3217 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3218 sizeof(*p) * p->num_of_param_pages , -1);
3220 /* Read out the Extended Parameter Page. */
3221 chip->read_buf(mtd, (uint8_t *)ep, len);
3222 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3223 != le16_to_cpu(ep->crc))) {
3224 pr_debug("fail in the CRC.\n");
3229 * Check the signature.
3230 * Do not strictly follow the ONFI spec, maybe changed in future.
3233 if (strncmp(ep->sig, "EPPS", 4)) {
3235 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3237 pr_debug("The signature is invalid.\n");
3241 /* find the ECC section. */
3242 cursor = (uint8_t *)(ep + 1);
3243 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3244 s = ep->sections + i;
3245 if (s->type == ONFI_SECTION_TYPE_2)
3247 cursor += s->length * 16;
3249 if (i == ONFI_EXT_SECTION_MAX) {
3250 pr_debug("We can not find the ECC section.\n");
3254 /* get the info we want. */
3255 ecc = (struct onfi_ext_ecc_info *)cursor;
3257 if (!ecc->codeword_size) {
3258 pr_debug("Invalid codeword size\n");
3262 chip->ecc_strength_ds = ecc->ecc_bits;
3263 chip->ecc_step_ds = 1 << ecc->codeword_size;
3271 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3273 struct nand_chip *chip = mtd->priv;
3274 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3276 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3281 * Configure chip properties from Micron vendor-specific ONFI table
3283 static void nand_onfi_detect_micron(struct nand_chip *chip,
3284 struct nand_onfi_params *p)
3286 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3288 if (le16_to_cpu(p->vendor_revision) < 1)
3291 chip->read_retries = micron->read_retry_options;
3292 chip->setup_read_retry = nand_setup_read_retry_micron;
3296 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3298 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3301 struct nand_onfi_params *p = &chip->onfi_params;
3305 /* Try ONFI for unknown chip or LP */
3306 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3307 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3308 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3311 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3312 for (i = 0; i < 3; i++) {
3313 for (j = 0; j < sizeof(*p); j++)
3314 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3315 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3316 le16_to_cpu(p->crc)) {
3322 pr_err("Could not find valid ONFI parameter page; aborting\n");
3327 val = le16_to_cpu(p->revision);
3329 chip->onfi_version = 23;
3330 else if (val & (1 << 4))
3331 chip->onfi_version = 22;
3332 else if (val & (1 << 3))
3333 chip->onfi_version = 21;
3334 else if (val & (1 << 2))
3335 chip->onfi_version = 20;
3336 else if (val & (1 << 1))
3337 chip->onfi_version = 10;
3339 if (!chip->onfi_version) {
3340 pr_info("unsupported ONFI version: %d\n", val);
3344 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3345 sanitize_string(p->model, sizeof(p->model));
3347 mtd->name = p->model;
3349 mtd->writesize = le32_to_cpu(p->byte_per_page);
3352 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3353 * (don't ask me who thought of this...). MTD assumes that these
3354 * dimensions will be power-of-2, so just truncate the remaining area.
3356 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3357 mtd->erasesize *= mtd->writesize;
3359 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3361 /* See erasesize comment */
3362 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3363 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3364 chip->bits_per_cell = p->bits_per_cell;
3366 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3367 *busw = NAND_BUSWIDTH_16;
3371 if (p->ecc_bits != 0xff) {
3372 chip->ecc_strength_ds = p->ecc_bits;
3373 chip->ecc_step_ds = 512;
3374 } else if (chip->onfi_version >= 21 &&
3375 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3378 * The nand_flash_detect_ext_param_page() uses the
3379 * Change Read Column command which maybe not supported
3380 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3381 * now. We do not replace user supplied command function.
3383 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3384 chip->cmdfunc = nand_command_lp;
3386 /* The Extended Parameter Page is supported since ONFI 2.1. */
3387 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3388 pr_warn("Failed to detect ONFI extended param page\n");
3390 pr_warn("Could not retrieve ONFI ECC requirements\n");
3393 if (p->jedec_id == NAND_MFR_MICRON)
3394 nand_onfi_detect_micron(chip, p);
3399 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3407 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3409 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3412 struct nand_jedec_params *p = &chip->jedec_params;
3413 struct jedec_ecc_info *ecc;
3417 /* Try JEDEC for unknown chip or LP */
3418 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3419 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3420 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3421 chip->read_byte(mtd) != 'C')
3424 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3425 for (i = 0; i < 3; i++) {
3426 for (j = 0; j < sizeof(*p); j++)
3427 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3429 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3430 le16_to_cpu(p->crc))
3435 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3440 val = le16_to_cpu(p->revision);
3442 chip->jedec_version = 10;
3443 else if (val & (1 << 1))
3444 chip->jedec_version = 1; /* vendor specific version */
3446 if (!chip->jedec_version) {
3447 pr_info("unsupported JEDEC version: %d\n", val);
3451 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3452 sanitize_string(p->model, sizeof(p->model));
3454 mtd->name = p->model;
3456 mtd->writesize = le32_to_cpu(p->byte_per_page);
3458 /* Please reference to the comment for nand_flash_detect_onfi. */
3459 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3460 mtd->erasesize *= mtd->writesize;
3462 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3464 /* Please reference to the comment for nand_flash_detect_onfi. */
3465 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3466 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3467 chip->bits_per_cell = p->bits_per_cell;
3469 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3470 *busw = NAND_BUSWIDTH_16;
3475 ecc = &p->ecc_info[0];
3477 if (ecc->codeword_size >= 9) {
3478 chip->ecc_strength_ds = ecc->ecc_bits;
3479 chip->ecc_step_ds = 1 << ecc->codeword_size;
3481 pr_warn("Invalid codeword size\n");
3488 * nand_id_has_period - Check if an ID string has a given wraparound period
3489 * @id_data: the ID string
3490 * @arrlen: the length of the @id_data array
3491 * @period: the period of repitition
3493 * Check if an ID string is repeated within a given sequence of bytes at
3494 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3495 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3496 * if the repetition has a period of @period; otherwise, returns zero.
3498 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3501 for (i = 0; i < period; i++)
3502 for (j = i + period; j < arrlen; j += period)
3503 if (id_data[i] != id_data[j])
3509 * nand_id_len - Get the length of an ID string returned by CMD_READID
3510 * @id_data: the ID string
3511 * @arrlen: the length of the @id_data array
3513 * Returns the length of the ID string, according to known wraparound/trailing
3514 * zero patterns. If no pattern exists, returns the length of the array.
3516 static int nand_id_len(u8 *id_data, int arrlen)
3518 int last_nonzero, period;
3520 /* Find last non-zero byte */
3521 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3522 if (id_data[last_nonzero])
3526 if (last_nonzero < 0)
3529 /* Calculate wraparound period */
3530 for (period = 1; period < arrlen; period++)
3531 if (nand_id_has_period(id_data, arrlen, period))
3534 /* There's a repeated pattern */
3535 if (period < arrlen)
3538 /* There are trailing zeros */
3539 if (last_nonzero < arrlen - 1)
3540 return last_nonzero + 1;
3542 /* No pattern detected */
3546 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3547 static int nand_get_bits_per_cell(u8 cellinfo)
3551 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3552 bits >>= NAND_CI_CELLTYPE_SHIFT;
3557 * Many new NAND share similar device ID codes, which represent the size of the
3558 * chip. The rest of the parameters must be decoded according to generic or
3559 * manufacturer-specific "extended ID" decoding patterns.
3561 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3562 u8 id_data[8], int *busw)
3565 /* The 3rd id byte holds MLC / multichip data */
3566 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3567 /* The 4th id byte is the important one */
3570 id_len = nand_id_len(id_data, 8);
3573 * Field definitions are in the following datasheets:
3574 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3575 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3576 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3578 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3579 * ID to decide what to do.
3581 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3582 !nand_is_slc(chip) && id_data[5] != 0x00) {
3584 mtd->writesize = 2048 << (extid & 0x03);
3587 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3607 default: /* Other cases are "reserved" (unknown) */
3608 mtd->oobsize = 1024;
3612 /* Calc blocksize */
3613 mtd->erasesize = (128 * 1024) <<
3614 (((extid >> 1) & 0x04) | (extid & 0x03));
3616 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3617 !nand_is_slc(chip)) {
3621 mtd->writesize = 2048 << (extid & 0x03);
3624 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3648 /* Calc blocksize */
3649 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3651 mtd->erasesize = (128 * 1024) << tmp;
3652 else if (tmp == 0x03)
3653 mtd->erasesize = 768 * 1024;
3655 mtd->erasesize = (64 * 1024) << tmp;
3659 mtd->writesize = 1024 << (extid & 0x03);
3662 mtd->oobsize = (8 << (extid & 0x01)) *
3663 (mtd->writesize >> 9);
3665 /* Calc blocksize. Blocksize is multiples of 64KiB */
3666 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3668 /* Get buswidth information */
3669 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3672 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3673 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3675 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3677 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3679 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3680 nand_is_slc(chip) &&
3681 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3682 !(id_data[4] & 0x80) /* !BENAND */) {
3683 mtd->oobsize = 32 * mtd->writesize >> 9;
3690 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3691 * decodes a matching ID table entry and assigns the MTD size parameters for
3694 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3695 struct nand_flash_dev *type, u8 id_data[8],
3698 int maf_id = id_data[0];
3700 mtd->erasesize = type->erasesize;
3701 mtd->writesize = type->pagesize;
3702 mtd->oobsize = mtd->writesize / 32;
3703 *busw = type->options & NAND_BUSWIDTH_16;
3705 /* All legacy ID NAND are small-page, SLC */
3706 chip->bits_per_cell = 1;
3709 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3710 * some Spansion chips have erasesize that conflicts with size
3711 * listed in nand_ids table.
3712 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3714 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3715 && id_data[6] == 0x00 && id_data[7] == 0x00
3716 && mtd->writesize == 512) {
3717 mtd->erasesize = 128 * 1024;
3718 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3723 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3724 * heuristic patterns using various detected parameters (e.g., manufacturer,
3725 * page size, cell-type information).
3727 static void nand_decode_bbm_options(struct mtd_info *mtd,
3728 struct nand_chip *chip, u8 id_data[8])
3730 int maf_id = id_data[0];
3732 /* Set the bad block position */
3733 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3734 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3736 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3739 * Bad block marker is stored in the last page of each block on Samsung
3740 * and Hynix MLC devices; stored in first two pages of each block on
3741 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3742 * AMD/Spansion, and Macronix. All others scan only the first page.
3744 if (!nand_is_slc(chip) &&
3745 (maf_id == NAND_MFR_SAMSUNG ||
3746 maf_id == NAND_MFR_HYNIX))
3747 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3748 else if ((nand_is_slc(chip) &&
3749 (maf_id == NAND_MFR_SAMSUNG ||
3750 maf_id == NAND_MFR_HYNIX ||
3751 maf_id == NAND_MFR_TOSHIBA ||
3752 maf_id == NAND_MFR_AMD ||
3753 maf_id == NAND_MFR_MACRONIX)) ||
3754 (mtd->writesize == 2048 &&
3755 maf_id == NAND_MFR_MICRON))
3756 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3759 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3761 return type->id_len;
3764 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3765 struct nand_flash_dev *type, u8 *id_data, int *busw)
3768 if (!strncmp(type->id, id_data, type->id_len)) {
3770 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3772 mtd->writesize = type->pagesize;
3773 mtd->erasesize = type->erasesize;
3774 mtd->oobsize = type->oobsize;
3776 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3777 chip->chipsize = (uint64_t)type->chipsize << 20;
3778 chip->options |= type->options;
3779 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3780 chip->ecc_step_ds = NAND_ECC_STEP(type);
3782 *busw = type->options & NAND_BUSWIDTH_16;
3785 mtd->name = type->name;
3793 * Get the flash and manufacturer id and lookup if the type is supported.
3795 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3796 struct nand_chip *chip,
3797 int *maf_id, int *dev_id,
3798 struct nand_flash_dev *type)
3804 /* Select the device */
3805 chip->select_chip(mtd, 0);
3808 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3811 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3813 /* Send the command for reading device ID */
3814 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3816 /* Read manufacturer and device IDs */
3817 *maf_id = chip->read_byte(mtd);
3818 *dev_id = chip->read_byte(mtd);
3821 * Try again to make sure, as some systems the bus-hold or other
3822 * interface concerns can cause random data which looks like a
3823 * possibly credible NAND flash to appear. If the two results do
3824 * not match, ignore the device completely.
3827 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3829 /* Read entire ID string */
3830 for (i = 0; i < 8; i++)
3831 id_data[i] = chip->read_byte(mtd);
3833 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3834 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3835 *maf_id, *dev_id, id_data[0], id_data[1]);
3836 return ERR_PTR(-ENODEV);
3840 type = nand_flash_ids;
3842 for (; type->name != NULL; type++) {
3843 if (is_full_id_nand(type)) {
3844 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3846 } else if (*dev_id == type->dev_id) {
3851 chip->onfi_version = 0;
3852 if (!type->name || !type->pagesize) {
3853 /* Check is chip is ONFI compliant */
3854 if (nand_flash_detect_onfi(mtd, chip, &busw))
3857 /* Check if the chip is JEDEC compliant */
3858 if (nand_flash_detect_jedec(mtd, chip, &busw))
3863 return ERR_PTR(-ENODEV);
3866 mtd->name = type->name;
3868 chip->chipsize = (uint64_t)type->chipsize << 20;
3870 if (!type->pagesize && chip->init_size) {
3871 /* Set the pagesize, oobsize, erasesize by the driver */
3872 busw = chip->init_size(mtd, chip, id_data);
3873 } else if (!type->pagesize) {
3874 /* Decode parameters from extended ID */
3875 nand_decode_ext_id(mtd, chip, id_data, &busw);
3877 nand_decode_id(mtd, chip, type, id_data, &busw);
3879 /* Get chip options */
3880 chip->options |= type->options;
3883 * Check if chip is not a Samsung device. Do not clear the
3884 * options for chips which do not have an extended id.
3886 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3887 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3890 /* Try to identify manufacturer */
3891 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3892 if (nand_manuf_ids[maf_idx].id == *maf_id)
3896 if (chip->options & NAND_BUSWIDTH_AUTO) {
3897 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3898 chip->options |= busw;
3899 nand_set_defaults(chip, busw);
3900 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3902 * Check, if buswidth is correct. Hardware drivers should set
3905 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3907 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3908 pr_warn("bus width %d instead %d bit\n",
3909 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3911 return ERR_PTR(-EINVAL);
3914 nand_decode_bbm_options(mtd, chip, id_data);
3916 /* Calculate the address shift from the page size */
3917 chip->page_shift = ffs(mtd->writesize) - 1;
3918 /* Convert chipsize to number of pages per chip -1 */
3919 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3921 chip->bbt_erase_shift = chip->phys_erase_shift =
3922 ffs(mtd->erasesize) - 1;
3923 if (chip->chipsize & 0xffffffff)
3924 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3926 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3927 chip->chip_shift += 32 - 1;
3930 chip->badblockbits = 8;
3931 chip->erase_cmd = single_erase_cmd;
3933 /* Do not replace user supplied command function! */
3934 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3935 chip->cmdfunc = nand_command_lp;
3937 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3940 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3941 if (chip->onfi_version)
3942 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3943 chip->onfi_params.model);
3944 else if (chip->jedec_version)
3945 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3946 chip->jedec_params.model);
3948 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3951 if (chip->jedec_version)
3952 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3953 chip->jedec_params.model);
3955 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3958 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3962 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3963 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3964 mtd->writesize, mtd->oobsize);
3969 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3970 * @mtd: MTD device structure
3971 * @maxchips: number of chips to scan for
3972 * @table: alternative NAND ID table
3974 * This is the first phase of the normal nand_scan() function. It reads the
3975 * flash ID and sets up MTD fields accordingly.
3977 * The mtd->owner field must be set to the module of the caller.
3979 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3980 struct nand_flash_dev *table)
3982 int i, nand_maf_id, nand_dev_id;
3983 struct nand_chip *chip = mtd->priv;
3984 struct nand_flash_dev *type;
3986 /* Set the default functions */
3987 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3989 /* Read the flash type */
3990 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3991 &nand_dev_id, table);
3994 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3995 pr_warn("No NAND device found\n");
3996 chip->select_chip(mtd, -1);
3997 return PTR_ERR(type);
4000 chip->select_chip(mtd, -1);
4002 /* Check for a chip array */
4003 for (i = 1; i < maxchips; i++) {
4004 chip->select_chip(mtd, i);
4005 /* See comment in nand_get_flash_type for reset */
4006 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4007 /* Send the command for reading device ID */
4008 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4009 /* Read manufacturer and device IDs */
4010 if (nand_maf_id != chip->read_byte(mtd) ||
4011 nand_dev_id != chip->read_byte(mtd)) {
4012 chip->select_chip(mtd, -1);
4015 chip->select_chip(mtd, -1);
4020 pr_info("%d chips detected\n", i);
4023 /* Store the number of chips and calc total size for mtd */
4025 mtd->size = i * chip->chipsize;
4029 EXPORT_SYMBOL(nand_scan_ident);
4033 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4034 * @mtd: MTD device structure
4036 * This is the second phase of the normal nand_scan() function. It fills out
4037 * all the uninitialized function pointers with the defaults and scans for a
4038 * bad block table if appropriate.
4040 int nand_scan_tail(struct mtd_info *mtd)
4043 struct nand_chip *chip = mtd->priv;
4044 struct nand_ecc_ctrl *ecc = &chip->ecc;
4045 struct nand_buffers *nbuf;
4047 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4048 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4049 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4051 if (!(chip->options & NAND_OWN_BUFFERS)) {
4053 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4054 + mtd->oobsize * 3, GFP_KERNEL);
4057 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4058 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4059 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4061 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4064 chip->buffers = nbuf;
4070 /* Set the internal oob buffer location, just after the page data */
4071 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4074 * If no default placement scheme is given, select an appropriate one.
4076 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4077 switch (mtd->oobsize) {
4079 ecc->layout = &nand_oob_8;
4082 ecc->layout = &nand_oob_16;
4085 ecc->layout = &nand_oob_64;
4088 ecc->layout = &nand_oob_128;
4091 pr_warn("No oob scheme defined for oobsize %d\n",
4097 if (!chip->write_page)
4098 chip->write_page = nand_write_page;
4101 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4102 * selected and we have 256 byte pagesize fallback to software ECC
4105 switch (ecc->mode) {
4106 case NAND_ECC_HW_OOB_FIRST:
4107 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4108 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4109 pr_warn("No ECC functions supplied; "
4110 "hardware ECC not possible\n");
4113 if (!ecc->read_page)
4114 ecc->read_page = nand_read_page_hwecc_oob_first;
4117 /* Use standard hwecc read page function? */
4118 if (!ecc->read_page)
4119 ecc->read_page = nand_read_page_hwecc;
4120 if (!ecc->write_page)
4121 ecc->write_page = nand_write_page_hwecc;
4122 if (!ecc->read_page_raw)
4123 ecc->read_page_raw = nand_read_page_raw;
4124 if (!ecc->write_page_raw)
4125 ecc->write_page_raw = nand_write_page_raw;
4127 ecc->read_oob = nand_read_oob_std;
4128 if (!ecc->write_oob)
4129 ecc->write_oob = nand_write_oob_std;
4130 if (!ecc->read_subpage)
4131 ecc->read_subpage = nand_read_subpage;
4132 if (!ecc->write_subpage)
4133 ecc->write_subpage = nand_write_subpage_hwecc;
4135 case NAND_ECC_HW_SYNDROME:
4136 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4138 ecc->read_page == nand_read_page_hwecc ||
4140 ecc->write_page == nand_write_page_hwecc)) {
4141 pr_warn("No ECC functions supplied; "
4142 "hardware ECC not possible\n");
4145 /* Use standard syndrome read/write page function? */
4146 if (!ecc->read_page)
4147 ecc->read_page = nand_read_page_syndrome;
4148 if (!ecc->write_page)
4149 ecc->write_page = nand_write_page_syndrome;
4150 if (!ecc->read_page_raw)
4151 ecc->read_page_raw = nand_read_page_raw_syndrome;
4152 if (!ecc->write_page_raw)
4153 ecc->write_page_raw = nand_write_page_raw_syndrome;
4155 ecc->read_oob = nand_read_oob_syndrome;
4156 if (!ecc->write_oob)
4157 ecc->write_oob = nand_write_oob_syndrome;
4159 if (mtd->writesize >= ecc->size) {
4160 if (!ecc->strength) {
4161 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4166 pr_warn("%d byte HW ECC not possible on "
4167 "%d byte page size, fallback to SW ECC\n",
4168 ecc->size, mtd->writesize);
4169 ecc->mode = NAND_ECC_SOFT;
4172 ecc->calculate = nand_calculate_ecc;
4173 ecc->correct = nand_correct_data;
4174 ecc->read_page = nand_read_page_swecc;
4175 ecc->read_subpage = nand_read_subpage;
4176 ecc->write_page = nand_write_page_swecc;
4177 ecc->read_page_raw = nand_read_page_raw;
4178 ecc->write_page_raw = nand_write_page_raw;
4179 ecc->read_oob = nand_read_oob_std;
4180 ecc->write_oob = nand_write_oob_std;
4187 case NAND_ECC_SOFT_BCH:
4188 if (!mtd_nand_has_bch()) {
4189 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4192 ecc->calculate = nand_bch_calculate_ecc;
4193 ecc->correct = nand_bch_correct_data;
4194 ecc->read_page = nand_read_page_swecc;
4195 ecc->read_subpage = nand_read_subpage;
4196 ecc->write_page = nand_write_page_swecc;
4197 ecc->read_page_raw = nand_read_page_raw;
4198 ecc->write_page_raw = nand_write_page_raw;
4199 ecc->read_oob = nand_read_oob_std;
4200 ecc->write_oob = nand_write_oob_std;
4202 * Board driver should supply ecc.size and ecc.bytes values to
4203 * select how many bits are correctable; see nand_bch_init()
4204 * for details. Otherwise, default to 4 bits for large page
4207 if (!ecc->size && (mtd->oobsize >= 64)) {
4211 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4214 pr_warn("BCH ECC initialization failed!\n");
4217 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
4221 pr_warn("NAND_ECC_NONE selected by board driver. "
4222 "This is not recommended!\n");
4223 ecc->read_page = nand_read_page_raw;
4224 ecc->write_page = nand_write_page_raw;
4225 ecc->read_oob = nand_read_oob_std;
4226 ecc->read_page_raw = nand_read_page_raw;
4227 ecc->write_page_raw = nand_write_page_raw;
4228 ecc->write_oob = nand_write_oob_std;
4229 ecc->size = mtd->writesize;
4235 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4239 /* For many systems, the standard OOB write also works for raw */
4240 if (!ecc->read_oob_raw)
4241 ecc->read_oob_raw = ecc->read_oob;
4242 if (!ecc->write_oob_raw)
4243 ecc->write_oob_raw = ecc->write_oob;
4246 * The number of bytes available for a client to place data into
4247 * the out of band area.
4249 ecc->layout->oobavail = 0;
4250 for (i = 0; ecc->layout->oobfree[i].length
4251 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4252 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4253 mtd->oobavail = ecc->layout->oobavail;
4256 * Set the number of read / write steps for one page depending on ECC
4259 ecc->steps = mtd->writesize / ecc->size;
4260 if (ecc->steps * ecc->size != mtd->writesize) {
4261 pr_warn("Invalid ECC parameters\n");
4264 ecc->total = ecc->steps * ecc->bytes;
4266 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4267 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4268 switch (ecc->steps) {
4270 mtd->subpage_sft = 1;
4275 mtd->subpage_sft = 2;
4279 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4281 /* Initialize state */
4282 chip->state = FL_READY;
4284 /* Invalidate the pagebuffer reference */
4287 /* Large page NAND with SOFT_ECC should support subpage reads */
4288 if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4289 chip->options |= NAND_SUBPAGE_READ;
4291 /* Fill in remaining MTD driver data */
4292 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4293 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4295 mtd->_erase = nand_erase;
4298 mtd->_unpoint = NULL;
4300 mtd->_read = nand_read;
4301 mtd->_write = nand_write;
4302 mtd->_panic_write = panic_nand_write;
4303 mtd->_read_oob = nand_read_oob;
4304 mtd->_write_oob = nand_write_oob;
4305 mtd->_sync = nand_sync;
4307 mtd->_unlock = NULL;
4309 mtd->_suspend = nand_suspend;
4310 mtd->_resume = nand_resume;
4312 mtd->_block_isbad = nand_block_isbad;
4313 mtd->_block_markbad = nand_block_markbad;
4314 mtd->writebufsize = mtd->writesize;
4316 /* propagate ecc info to mtd_info */
4317 mtd->ecclayout = ecc->layout;
4318 mtd->ecc_strength = ecc->strength;
4319 mtd->ecc_step_size = ecc->size;
4321 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4322 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4325 if (!mtd->bitflip_threshold)
4326 mtd->bitflip_threshold = mtd->ecc_strength;
4328 /* Check, if we should skip the bad block table scan */
4329 if (chip->options & NAND_SKIP_BBTSCAN)
4330 chip->options |= NAND_BBT_SCANNED;
4334 EXPORT_SYMBOL(nand_scan_tail);
4337 * is_module_text_address() isn't exported, and it's mostly a pointless
4338 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4339 * to call us from in-kernel code if the core NAND support is modular.
4342 #define caller_is_module() (1)
4344 #define caller_is_module() \
4345 is_module_text_address((unsigned long)__builtin_return_address(0))
4349 * nand_scan - [NAND Interface] Scan for the NAND device
4350 * @mtd: MTD device structure
4351 * @maxchips: number of chips to scan for
4353 * This fills out all the uninitialized function pointers with the defaults.
4354 * The flash ID is read and the mtd/chip structures are filled with the
4355 * appropriate values. The mtd->owner field must be set to the module of the
4358 int nand_scan(struct mtd_info *mtd, int maxchips)
4362 /* Many callers got this wrong, so check for it for a while... */
4363 if (!mtd->owner && caller_is_module()) {
4364 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4368 ret = nand_scan_ident(mtd, maxchips, NULL);
4370 ret = nand_scan_tail(mtd);
4373 EXPORT_SYMBOL(nand_scan);
4377 * nand_release - [NAND Interface] Free resources held by the NAND device
4378 * @mtd: MTD device structure
4380 void nand_release(struct mtd_info *mtd)
4382 struct nand_chip *chip = mtd->priv;
4384 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4385 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4387 mtd_device_unregister(mtd);
4389 /* Free bad block table memory */
4391 if (!(chip->options & NAND_OWN_BUFFERS))
4392 kfree(chip->buffers);
4394 /* Free bad block descriptor memory */
4395 if (chip->badblock_pattern && chip->badblock_pattern->options
4396 & NAND_BBT_DYNAMICSTRUCT)
4397 kfree(chip->badblock_pattern);
4399 EXPORT_SYMBOL_GPL(nand_release);
4401 static int __init nand_base_init(void)
4403 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4407 static void __exit nand_base_exit(void)
4409 led_trigger_unregister_simple(nand_led_trigger);
4413 module_init(nand_base_init);
4414 module_exit(nand_base_exit);
4416 MODULE_LICENSE("GPL");
4417 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4418 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4419 MODULE_DESCRIPTION("Generic NAND flash driver code");