5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/tech/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License version 2 as
30 * published by the Free Software Foundation.
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/errno.h>
39 #include <linux/err.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/types.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/compatmac.h>
47 #include <linux/interrupt.h>
48 #include <linux/bitops.h>
49 #include <linux/leds.h>
52 #ifdef CONFIG_MTD_PARTITIONS
53 #include <linux/mtd/partitions.h>
60 #define ENOTSUPP 524 /* Operation is not supported */
62 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
66 #include <linux/err.h>
67 #include <linux/mtd/compat.h>
68 #include <linux/mtd/mtd.h>
69 #include <linux/mtd/nand.h>
70 #include <linux/mtd/nand_ecc.h>
73 #include <asm/errno.h>
75 #ifdef CONFIG_JFFS2_NAND
76 #include <jffs2/jffs2.h>
79 /* Define default oob placement schemes for large and small page devices */
80 static struct nand_ecclayout nand_oob_8 = {
90 static struct nand_ecclayout nand_oob_16 = {
92 .eccpos = {0, 1, 2, 3, 6, 7},
98 static struct nand_ecclayout nand_oob_64 = {
101 40, 41, 42, 43, 44, 45, 46, 47,
102 48, 49, 50, 51, 52, 53, 54, 55,
103 56, 57, 58, 59, 60, 61, 62, 63},
109 static struct nand_ecclayout nand_oob_128 = {
112 80, 81, 82, 83, 84, 85, 86, 87,
113 88, 89, 90, 91, 92, 93, 94, 95,
114 96, 97, 98, 99, 100, 101, 102, 103,
115 104, 105, 106, 107, 108, 109, 110, 111,
116 112, 113, 114, 115, 116, 117, 118, 119,
117 120, 121, 122, 123, 124, 125, 126, 127},
124 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
127 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
128 struct mtd_oob_ops *ops);
130 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
133 * For devices which display every fart in the system on a seperate LED. Is
134 * compiled away when LED support is disabled.
138 DEFINE_LED_TRIGGER(nand_led_trigger);
142 * nand_release_device - [GENERIC] release chip
143 * @mtd: MTD device structure
145 * Deselect, release chip lock and wake up anyone waiting on the device
149 static void nand_release_device(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
153 /* De-select the NAND device */
154 chip->select_chip(mtd, -1);
156 /* Release the controller and the chip */
157 spin_lock(&chip->controller->lock);
158 chip->controller->active = NULL;
159 chip->state = FL_READY;
160 wake_up(&chip->controller->wq);
161 spin_unlock(&chip->controller->lock);
164 static void nand_release_device (struct mtd_info *mtd)
166 struct nand_chip *this = mtd->priv;
167 this->select_chip(mtd, -1); /* De-select the NAND device */
172 * nand_read_byte - [DEFAULT] read one byte from the chip
173 * @mtd: MTD device structure
175 * Default read function for 8bit buswith
177 static uint8_t nand_read_byte(struct mtd_info *mtd)
179 struct nand_chip *chip = mtd->priv;
180 return readb(chip->IO_ADDR_R);
184 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
185 * @mtd: MTD device structure
187 * Default read function for 16bit buswith with
188 * endianess conversion
190 static uint8_t nand_read_byte16(struct mtd_info *mtd)
192 struct nand_chip *chip = mtd->priv;
193 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
197 * nand_read_word - [DEFAULT] read one word from the chip
198 * @mtd: MTD device structure
200 * Default read function for 16bit buswith without
201 * endianess conversion
203 static u16 nand_read_word(struct mtd_info *mtd)
205 struct nand_chip *chip = mtd->priv;
206 return readw(chip->IO_ADDR_R);
210 * nand_select_chip - [DEFAULT] control CE line
211 * @mtd: MTD device structure
212 * @chipnr: chipnumber to select, -1 for deselect
214 * Default select function for 1 chip devices.
216 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
218 struct nand_chip *chip = mtd->priv;
222 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
233 * nand_write_buf - [DEFAULT] write buffer to chip
234 * @mtd: MTD device structure
236 * @len: number of bytes to write
238 * Default write function for 8bit buswith
240 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
243 struct nand_chip *chip = mtd->priv;
245 for (i = 0; i < len; i++)
246 writeb(buf[i], chip->IO_ADDR_W);
250 * nand_read_buf - [DEFAULT] read chip data into buffer
251 * @mtd: MTD device structure
252 * @buf: buffer to store date
253 * @len: number of bytes to read
255 * Default read function for 8bit buswith
257 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
260 struct nand_chip *chip = mtd->priv;
262 for (i = 0; i < len; i++)
263 buf[i] = readb(chip->IO_ADDR_R);
267 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
268 * @mtd: MTD device structure
269 * @buf: buffer containing the data to compare
270 * @len: number of bytes to compare
272 * Default verify function for 8bit buswith
274 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
277 struct nand_chip *chip = mtd->priv;
279 for (i = 0; i < len; i++)
280 if (buf[i] != readb(chip->IO_ADDR_R))
286 * nand_write_buf16 - [DEFAULT] write buffer to chip
287 * @mtd: MTD device structure
289 * @len: number of bytes to write
291 * Default write function for 16bit buswith
293 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
296 struct nand_chip *chip = mtd->priv;
297 u16 *p = (u16 *) buf;
300 for (i = 0; i < len; i++)
301 writew(p[i], chip->IO_ADDR_W);
306 * nand_read_buf16 - [DEFAULT] read chip data into buffer
307 * @mtd: MTD device structure
308 * @buf: buffer to store date
309 * @len: number of bytes to read
311 * Default read function for 16bit buswith
313 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
316 struct nand_chip *chip = mtd->priv;
317 u16 *p = (u16 *) buf;
320 for (i = 0; i < len; i++)
321 p[i] = readw(chip->IO_ADDR_R);
325 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
326 * @mtd: MTD device structure
327 * @buf: buffer containing the data to compare
328 * @len: number of bytes to compare
330 * Default verify function for 16bit buswith
332 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
335 struct nand_chip *chip = mtd->priv;
336 u16 *p = (u16 *) buf;
339 for (i = 0; i < len; i++)
340 if (p[i] != readw(chip->IO_ADDR_R))
347 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
348 * @mtd: MTD device structure
349 * @ofs: offset from device start
350 * @getchip: 0, if the chip is already selected
352 * Check, if the block is bad.
354 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
356 int page, chipnr, res = 0;
357 struct nand_chip *chip = mtd->priv;
360 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
363 chipnr = (int)(ofs >> chip->chip_shift);
365 nand_get_device(chip, mtd, FL_READING);
367 /* Select the NAND device */
368 chip->select_chip(mtd, chipnr);
371 if (chip->options & NAND_BUSWIDTH_16) {
372 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
374 bad = cpu_to_le16(chip->read_word(mtd));
375 if (chip->badblockpos & 0x1)
377 if ((bad & 0xFF) != 0xff)
380 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
381 if (chip->read_byte(mtd) != 0xff)
386 nand_release_device(mtd);
392 * nand_default_block_markbad - [DEFAULT] mark a block bad
393 * @mtd: MTD device structure
394 * @ofs: offset from device start
396 * This is the default implementation, which can be overridden by
397 * a hardware specific driver.
399 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
401 struct nand_chip *chip = mtd->priv;
402 uint8_t buf[2] = { 0, 0 };
405 /* Get block number */
406 block = (int)(ofs >> chip->bbt_erase_shift);
408 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
410 /* Do we have a flash based bad block table ? */
411 if (chip->options & NAND_USE_FLASH_BBT)
412 ret = nand_update_bbt(mtd, ofs);
414 /* We write two bytes, so we dont have to mess with 16 bit
418 chip->ops.len = chip->ops.ooblen = 2;
419 chip->ops.datbuf = NULL;
420 chip->ops.oobbuf = buf;
421 chip->ops.ooboffs = chip->badblockpos & ~0x01;
423 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
426 mtd->ecc_stats.badblocks++;
431 * nand_check_wp - [GENERIC] check if the chip is write protected
432 * @mtd: MTD device structure
433 * Check, if the device is write protected
435 * The function expects, that the device is already selected
437 static int nand_check_wp(struct mtd_info *mtd)
439 struct nand_chip *chip = mtd->priv;
440 /* Check the WP bit */
441 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
442 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
446 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
447 * @mtd: MTD device structure
448 * @ofs: offset from device start
449 * @getchip: 0, if the chip is already selected
450 * @allowbbt: 1, if its allowed to access the bbt area
452 * Check, if the block is bad. Either by reading the bad block table or
453 * calling of the scan function.
455 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
458 struct nand_chip *chip = mtd->priv;
461 return chip->block_bad(mtd, ofs, getchip);
463 /* Return info from the table */
464 return nand_isbad_bbt(mtd, ofs, allowbbt);
468 * Wait for the ready pin, after a command
469 * The timeout is catched later.
473 void nand_wait_ready(struct mtd_info *mtd)
475 struct nand_chip *chip = mtd->priv;
476 unsigned long timeo = jiffies + 2;
478 led_trigger_event(nand_led_trigger, LED_FULL);
479 /* wait until command is processed or timeout occures */
481 if (chip->dev_ready(mtd))
483 touch_softlockup_watchdog();
484 } while (time_before(jiffies, timeo));
485 led_trigger_event(nand_led_trigger, LED_OFF);
487 EXPORT_SYMBOL_GPL(nand_wait_ready);
489 void nand_wait_ready(struct mtd_info *mtd)
491 struct nand_chip *chip = mtd->priv;
492 u32 timeo = (CFG_HZ * 20) / 1000;
496 /* wait until command is processed or timeout occures */
497 while (get_timer(0) < timeo) {
499 if (chip->dev_ready(mtd))
506 * nand_command - [DEFAULT] Send command to NAND device
507 * @mtd: MTD device structure
508 * @command: the command to be sent
509 * @column: the column address for this command, -1 if none
510 * @page_addr: the page address for this command, -1 if none
512 * Send command to NAND device. This function is used for small page
513 * devices (256/512 Bytes per page)
515 static void nand_command(struct mtd_info *mtd, unsigned int command,
516 int column, int page_addr)
518 register struct nand_chip *chip = mtd->priv;
519 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
522 * Write out the command to the device.
524 if (command == NAND_CMD_SEQIN) {
527 if (column >= mtd->writesize) {
529 column -= mtd->writesize;
530 readcmd = NAND_CMD_READOOB;
531 } else if (column < 256) {
532 /* First 256 bytes --> READ0 */
533 readcmd = NAND_CMD_READ0;
536 readcmd = NAND_CMD_READ1;
538 chip->cmd_ctrl(mtd, readcmd, ctrl);
539 ctrl &= ~NAND_CTRL_CHANGE;
541 chip->cmd_ctrl(mtd, command, ctrl);
544 * Address cycle, when necessary
546 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
547 /* Serially input address */
549 /* Adjust columns for 16 bit buswidth */
550 if (chip->options & NAND_BUSWIDTH_16)
552 chip->cmd_ctrl(mtd, column, ctrl);
553 ctrl &= ~NAND_CTRL_CHANGE;
555 if (page_addr != -1) {
556 chip->cmd_ctrl(mtd, page_addr, ctrl);
557 ctrl &= ~NAND_CTRL_CHANGE;
558 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
559 /* One more address cycle for devices > 32MiB */
560 if (chip->chipsize > (32 << 20))
561 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
563 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
566 * program and erase have their own busy handlers
567 * status and sequential in needs no delay
571 case NAND_CMD_PAGEPROG:
572 case NAND_CMD_ERASE1:
573 case NAND_CMD_ERASE2:
575 case NAND_CMD_STATUS:
581 udelay(chip->chip_delay);
582 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
583 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
585 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
586 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
589 /* This applies to read commands */
592 * If we don't have access to the busy pin, we apply the given
595 if (!chip->dev_ready) {
596 udelay(chip->chip_delay);
600 /* Apply this short delay always to ensure that we do wait tWB in
601 * any case on any machine. */
604 nand_wait_ready(mtd);
608 * nand_command_lp - [DEFAULT] Send command to NAND large page device
609 * @mtd: MTD device structure
610 * @command: the command to be sent
611 * @column: the column address for this command, -1 if none
612 * @page_addr: the page address for this command, -1 if none
614 * Send command to NAND device. This is the version for the new large page
615 * devices We dont have the separate regions as we have in the small page
616 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
618 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
619 int column, int page_addr)
621 register struct nand_chip *chip = mtd->priv;
623 /* Emulate NAND_CMD_READOOB */
624 if (command == NAND_CMD_READOOB) {
625 column += mtd->writesize;
626 command = NAND_CMD_READ0;
629 /* Command latch cycle */
630 chip->cmd_ctrl(mtd, command & 0xff,
631 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
633 if (column != -1 || page_addr != -1) {
634 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
636 /* Serially input address */
638 /* Adjust columns for 16 bit buswidth */
639 if (chip->options & NAND_BUSWIDTH_16)
641 chip->cmd_ctrl(mtd, column, ctrl);
642 ctrl &= ~NAND_CTRL_CHANGE;
643 chip->cmd_ctrl(mtd, column >> 8, ctrl);
645 if (page_addr != -1) {
646 chip->cmd_ctrl(mtd, page_addr, ctrl);
647 chip->cmd_ctrl(mtd, page_addr >> 8,
648 NAND_NCE | NAND_ALE);
649 /* One more address cycle for devices > 128MiB */
650 if (chip->chipsize > (128 << 20))
651 chip->cmd_ctrl(mtd, page_addr >> 16,
652 NAND_NCE | NAND_ALE);
655 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
658 * program and erase have their own busy handlers
659 * status, sequential in, and deplete1 need no delay
663 case NAND_CMD_CACHEDPROG:
664 case NAND_CMD_PAGEPROG:
665 case NAND_CMD_ERASE1:
666 case NAND_CMD_ERASE2:
669 case NAND_CMD_STATUS:
670 case NAND_CMD_DEPLETE1:
674 * read error status commands require only a short delay
676 case NAND_CMD_STATUS_ERROR:
677 case NAND_CMD_STATUS_ERROR0:
678 case NAND_CMD_STATUS_ERROR1:
679 case NAND_CMD_STATUS_ERROR2:
680 case NAND_CMD_STATUS_ERROR3:
681 udelay(chip->chip_delay);
687 udelay(chip->chip_delay);
688 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
689 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
690 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
691 NAND_NCE | NAND_CTRL_CHANGE);
692 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
695 case NAND_CMD_RNDOUT:
696 /* No ready / busy check necessary */
697 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
698 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
699 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
700 NAND_NCE | NAND_CTRL_CHANGE);
704 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
705 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
706 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
707 NAND_NCE | NAND_CTRL_CHANGE);
709 /* This applies to read commands */
712 * If we don't have access to the busy pin, we apply the given
715 if (!chip->dev_ready) {
716 udelay(chip->chip_delay);
721 /* Apply this short delay always to ensure that we do wait tWB in
722 * any case on any machine. */
725 nand_wait_ready(mtd);
729 * nand_get_device - [GENERIC] Get chip for selected access
730 * @chip: the nand chip descriptor
731 * @mtd: MTD device structure
732 * @new_state: the state which is requested
734 * Get the device and lock it for exclusive access
739 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
741 spinlock_t *lock = &chip->controller->lock;
742 wait_queue_head_t *wq = &chip->controller->wq;
743 DECLARE_WAITQUEUE(wait, current);
747 /* Hardware controller shared among independend devices */
748 /* Hardware controller shared among independend devices */
749 if (!chip->controller->active)
750 chip->controller->active = chip;
752 if (chip->controller->active == chip && chip->state == FL_READY) {
753 chip->state = new_state;
757 if (new_state == FL_PM_SUSPENDED) {
759 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
761 set_current_state(TASK_UNINTERRUPTIBLE);
762 add_wait_queue(wq, &wait);
765 remove_wait_queue(wq, &wait);
769 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
776 * nand_wait - [DEFAULT] wait until the command is done
777 * @mtd: MTD device structure
778 * @chip: NAND chip structure
780 * Wait for command done. This applies to erase and program only
781 * Erase can take up to 400ms and program up to 20ms according to
782 * general NAND and SmartMedia specs
786 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
789 unsigned long timeo = jiffies;
790 int status, state = chip->state;
792 if (state == FL_ERASING)
793 timeo += (HZ * 400) / 1000;
795 timeo += (HZ * 20) / 1000;
797 led_trigger_event(nand_led_trigger, LED_FULL);
799 /* Apply this short delay always to ensure that we do wait tWB in
800 * any case on any machine. */
803 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
804 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
806 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
808 while (time_before(jiffies, timeo)) {
809 if (chip->dev_ready) {
810 if (chip->dev_ready(mtd))
813 if (chip->read_byte(mtd) & NAND_STATUS_READY)
818 led_trigger_event(nand_led_trigger, LED_OFF);
820 status = (int)chip->read_byte(mtd);
824 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
827 int state = this->state;
829 if (state == FL_ERASING)
830 timeo = (CFG_HZ * 400) / 1000;
832 timeo = (CFG_HZ * 20) / 1000;
834 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
835 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
837 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
842 if (get_timer(0) > timeo) {
847 if (this->dev_ready) {
848 if (this->dev_ready(mtd))
851 if (this->read_byte(mtd) & NAND_STATUS_READY)
855 #ifdef PPCHAMELON_NAND_TIMER_HACK
857 while (get_timer(0) < 10);
858 #endif /* PPCHAMELON_NAND_TIMER_HACK */
860 return this->read_byte(mtd);
865 * nand_read_page_raw - [Intern] read raw page data without ecc
866 * @mtd: mtd info structure
867 * @chip: nand chip info structure
868 * @buf: buffer to store read data
870 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
873 chip->read_buf(mtd, buf, mtd->writesize);
874 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
879 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
880 * @mtd: mtd info structure
881 * @chip: nand chip info structure
882 * @buf: buffer to store read data
884 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
887 int i, eccsize = chip->ecc.size;
888 int eccbytes = chip->ecc.bytes;
889 int eccsteps = chip->ecc.steps;
891 uint8_t *ecc_calc = chip->buffers->ecccalc;
892 uint8_t *ecc_code = chip->buffers->ecccode;
893 uint32_t *eccpos = chip->ecc.layout->eccpos;
895 chip->ecc.read_page_raw(mtd, chip, buf);
897 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
898 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
900 for (i = 0; i < chip->ecc.total; i++)
901 ecc_code[i] = chip->oob_poi[eccpos[i]];
903 eccsteps = chip->ecc.steps;
906 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
909 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
911 mtd->ecc_stats.failed++;
913 mtd->ecc_stats.corrected += stat;
919 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
920 * @mtd: mtd info structure
921 * @chip: nand chip info structure
922 * @buf: buffer to store read data
924 * Not for syndrome calculating ecc controllers which need a special oob layout
926 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
929 int i, eccsize = chip->ecc.size;
930 int eccbytes = chip->ecc.bytes;
931 int eccsteps = chip->ecc.steps;
933 uint8_t *ecc_calc = chip->buffers->ecccalc;
934 uint8_t *ecc_code = chip->buffers->ecccode;
935 uint32_t *eccpos = chip->ecc.layout->eccpos;
937 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
938 chip->ecc.hwctl(mtd, NAND_ECC_READ);
939 chip->read_buf(mtd, p, eccsize);
940 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
942 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
944 for (i = 0; i < chip->ecc.total; i++)
945 ecc_code[i] = chip->oob_poi[eccpos[i]];
947 eccsteps = chip->ecc.steps;
950 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
953 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
955 mtd->ecc_stats.failed++;
957 mtd->ecc_stats.corrected += stat;
963 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
964 * @mtd: mtd info structure
965 * @chip: nand chip info structure
966 * @buf: buffer to store read data
968 * The hw generator calculates the error syndrome automatically. Therefor
969 * we need a special oob layout and handling.
971 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
974 int i, eccsize = chip->ecc.size;
975 int eccbytes = chip->ecc.bytes;
976 int eccsteps = chip->ecc.steps;
978 uint8_t *oob = chip->oob_poi;
980 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
983 chip->ecc.hwctl(mtd, NAND_ECC_READ);
984 chip->read_buf(mtd, p, eccsize);
986 if (chip->ecc.prepad) {
987 chip->read_buf(mtd, oob, chip->ecc.prepad);
988 oob += chip->ecc.prepad;
991 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
992 chip->read_buf(mtd, oob, eccbytes);
993 stat = chip->ecc.correct(mtd, p, oob, NULL);
996 mtd->ecc_stats.failed++;
998 mtd->ecc_stats.corrected += stat;
1002 if (chip->ecc.postpad) {
1003 chip->read_buf(mtd, oob, chip->ecc.postpad);
1004 oob += chip->ecc.postpad;
1008 /* Calculate remaining oob bytes */
1009 i = mtd->oobsize - (oob - chip->oob_poi);
1011 chip->read_buf(mtd, oob, i);
1017 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1018 * @chip: nand chip structure
1019 * @oob: oob destination address
1020 * @ops: oob ops structure
1021 * @len: size of oob to transfer
1023 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1024 struct mtd_oob_ops *ops, size_t len)
1030 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1033 case MTD_OOB_AUTO: {
1034 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1035 uint32_t boffs = 0, roffs = ops->ooboffs;
1038 for(; free->length && len; free++, len -= bytes) {
1039 /* Read request not from offset 0 ? */
1040 if (unlikely(roffs)) {
1041 if (roffs >= free->length) {
1042 roffs -= free->length;
1045 boffs = free->offset + roffs;
1046 bytes = min_t(size_t, len,
1047 (free->length - roffs));
1050 bytes = min_t(size_t, len, free->length);
1051 boffs = free->offset;
1053 memcpy(oob, chip->oob_poi + boffs, bytes);
1065 * nand_do_read_ops - [Internal] Read data with ECC
1067 * @mtd: MTD device structure
1068 * @from: offset to read from
1069 * @ops: oob ops structure
1071 * Internal function. Called with chip held.
1073 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1074 struct mtd_oob_ops *ops)
1076 int chipnr, page, realpage, col, bytes, aligned;
1077 struct nand_chip *chip = mtd->priv;
1078 struct mtd_ecc_stats stats;
1079 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1082 uint32_t readlen = ops->len;
1083 uint32_t oobreadlen = ops->ooblen;
1084 uint8_t *bufpoi, *oob, *buf;
1086 stats = mtd->ecc_stats;
1088 chipnr = (int)(from >> chip->chip_shift);
1089 chip->select_chip(mtd, chipnr);
1091 realpage = (int)(from >> chip->page_shift);
1092 page = realpage & chip->pagemask;
1094 col = (int)(from & (mtd->writesize - 1));
1100 bytes = min(mtd->writesize - col, readlen);
1101 aligned = (bytes == mtd->writesize);
1103 /* Is the current page in the buffer ? */
1104 if (realpage != chip->pagebuf || oob) {
1105 bufpoi = aligned ? buf : chip->buffers->databuf;
1107 if (likely(sndcmd)) {
1108 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1112 /* Now read the page into the buffer */
1113 if (unlikely(ops->mode == MTD_OOB_RAW))
1114 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1116 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1120 /* Transfer not aligned data */
1122 chip->pagebuf = realpage;
1123 memcpy(buf, chip->buffers->databuf + col, bytes);
1128 if (unlikely(oob)) {
1129 /* Raw mode does data:oob:data:oob */
1130 if (ops->mode != MTD_OOB_RAW) {
1131 int toread = min(oobreadlen,
1132 chip->ecc.layout->oobavail);
1134 oob = nand_transfer_oob(chip,
1136 oobreadlen -= toread;
1139 buf = nand_transfer_oob(chip,
1140 buf, ops, mtd->oobsize);
1143 if (!(chip->options & NAND_NO_READRDY)) {
1145 * Apply delay or wait for ready/busy pin. Do
1146 * this before the AUTOINCR check, so no
1147 * problems arise if a chip which does auto
1148 * increment is marked as NOAUTOINCR by the
1151 if (!chip->dev_ready)
1152 udelay(chip->chip_delay);
1154 nand_wait_ready(mtd);
1157 memcpy(buf, chip->buffers->databuf + col, bytes);
1166 /* For subsequent reads align to page boundary. */
1168 /* Increment page address */
1171 page = realpage & chip->pagemask;
1172 /* Check, if we cross a chip boundary */
1175 chip->select_chip(mtd, -1);
1176 chip->select_chip(mtd, chipnr);
1179 /* Check, if the chip supports auto page increment
1180 * or if we have hit a block boundary.
1182 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1186 ops->retlen = ops->len - (size_t) readlen;
1188 ops->oobretlen = ops->ooblen - oobreadlen;
1193 if (mtd->ecc_stats.failed - stats.failed)
1196 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1200 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1201 * @mtd: MTD device structure
1202 * @from: offset to read from
1203 * @len: number of bytes to read
1204 * @retlen: pointer to variable to store the number of read bytes
1205 * @buf: the databuffer to put data
1207 * Get hold of the chip and call nand_do_read
1209 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1210 size_t *retlen, uint8_t *buf)
1212 struct nand_chip *chip = mtd->priv;
1215 /* Do not allow reads past end of device */
1216 if ((from + len) > mtd->size)
1221 nand_get_device(chip, mtd, FL_READING);
1223 chip->ops.len = len;
1224 chip->ops.datbuf = buf;
1225 chip->ops.oobbuf = NULL;
1227 ret = nand_do_read_ops(mtd, from, &chip->ops);
1229 *retlen = chip->ops.retlen;
1231 nand_release_device(mtd);
1237 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1238 * @mtd: mtd info structure
1239 * @chip: nand chip info structure
1240 * @page: page number to read
1241 * @sndcmd: flag whether to issue read command or not
1243 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1244 int page, int sndcmd)
1247 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1250 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1255 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1257 * @mtd: mtd info structure
1258 * @chip: nand chip info structure
1259 * @page: page number to read
1260 * @sndcmd: flag whether to issue read command or not
1262 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1263 int page, int sndcmd)
1265 uint8_t *buf = chip->oob_poi;
1266 int length = mtd->oobsize;
1267 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1268 int eccsize = chip->ecc.size;
1269 uint8_t *bufpoi = buf;
1270 int i, toread, sndrnd = 0, pos;
1272 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1273 for (i = 0; i < chip->ecc.steps; i++) {
1275 pos = eccsize + i * (eccsize + chunk);
1276 if (mtd->writesize > 512)
1277 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1279 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1282 toread = min_t(int, length, chunk);
1283 chip->read_buf(mtd, bufpoi, toread);
1288 chip->read_buf(mtd, bufpoi, length);
1294 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1295 * @mtd: mtd info structure
1296 * @chip: nand chip info structure
1297 * @page: page number to write
1299 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1303 const uint8_t *buf = chip->oob_poi;
1304 int length = mtd->oobsize;
1306 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1307 chip->write_buf(mtd, buf, length);
1308 /* Send command to program the OOB data */
1309 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1311 status = chip->waitfunc(mtd, chip);
1313 return status & NAND_STATUS_FAIL ? -EIO : 0;
1317 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1318 * with syndrome - only for large page flash !
1319 * @mtd: mtd info structure
1320 * @chip: nand chip info structure
1321 * @page: page number to write
1323 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1324 struct nand_chip *chip, int page)
1326 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1327 int eccsize = chip->ecc.size, length = mtd->oobsize;
1328 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1329 const uint8_t *bufpoi = chip->oob_poi;
1332 * data-ecc-data-ecc ... ecc-oob
1334 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1336 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1337 pos = steps * (eccsize + chunk);
1342 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1343 for (i = 0; i < steps; i++) {
1345 if (mtd->writesize <= 512) {
1346 uint32_t fill = 0xFFFFFFFF;
1350 int num = min_t(int, len, 4);
1351 chip->write_buf(mtd, (uint8_t *)&fill,
1356 pos = eccsize + i * (eccsize + chunk);
1357 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1361 len = min_t(int, length, chunk);
1362 chip->write_buf(mtd, bufpoi, len);
1367 chip->write_buf(mtd, bufpoi, length);
1369 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1370 status = chip->waitfunc(mtd, chip);
1372 return status & NAND_STATUS_FAIL ? -EIO : 0;
1376 * nand_do_read_oob - [Intern] NAND read out-of-band
1377 * @mtd: MTD device structure
1378 * @from: offset to read from
1379 * @ops: oob operations description structure
1381 * NAND read out-of-band data from the spare area
1383 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1384 struct mtd_oob_ops *ops)
1386 int page, realpage, chipnr, sndcmd = 1;
1387 struct nand_chip *chip = mtd->priv;
1388 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1389 int readlen = ops->ooblen;
1391 uint8_t *buf = ops->oobbuf;
1393 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1394 (unsigned long long)from, readlen);
1396 if (ops->mode == MTD_OOB_AUTO)
1397 len = chip->ecc.layout->oobavail;
1401 if (unlikely(ops->ooboffs >= len)) {
1402 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1403 "Attempt to start read outside oob\n");
1407 /* Do not allow reads past end of device */
1408 if (unlikely(from >= mtd->size ||
1409 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1410 (from >> chip->page_shift)) * len)) {
1411 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1412 "Attempt read beyond end of device\n");
1416 chipnr = (int)(from >> chip->chip_shift);
1417 chip->select_chip(mtd, chipnr);
1419 /* Shift to get page */
1420 realpage = (int)(from >> chip->page_shift);
1421 page = realpage & chip->pagemask;
1424 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1426 len = min(len, readlen);
1427 buf = nand_transfer_oob(chip, buf, ops, len);
1429 if (!(chip->options & NAND_NO_READRDY)) {
1431 * Apply delay or wait for ready/busy pin. Do this
1432 * before the AUTOINCR check, so no problems arise if a
1433 * chip which does auto increment is marked as
1434 * NOAUTOINCR by the board driver.
1436 if (!chip->dev_ready)
1437 udelay(chip->chip_delay);
1439 nand_wait_ready(mtd);
1446 /* Increment page address */
1449 page = realpage & chip->pagemask;
1450 /* Check, if we cross a chip boundary */
1453 chip->select_chip(mtd, -1);
1454 chip->select_chip(mtd, chipnr);
1457 /* Check, if the chip supports auto page increment
1458 * or if we have hit a block boundary.
1460 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1464 ops->oobretlen = ops->ooblen;
1469 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1470 * @mtd: MTD device structure
1471 * @from: offset to read from
1472 * @ops: oob operation description structure
1474 * NAND read data and/or out-of-band data
1476 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1477 struct mtd_oob_ops *ops)
1479 struct nand_chip *chip = mtd->priv;
1480 int ret = -ENOTSUPP;
1484 /* Do not allow reads past end of device */
1485 if (ops->datbuf && (from + ops->len) > mtd->size) {
1486 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1487 "Attempt read beyond end of device\n");
1491 nand_get_device(chip, mtd, FL_READING);
1504 ret = nand_do_read_oob(mtd, from, ops);
1506 ret = nand_do_read_ops(mtd, from, ops);
1509 nand_release_device(mtd);
1515 * nand_write_page_raw - [Intern] raw page write function
1516 * @mtd: mtd info structure
1517 * @chip: nand chip info structure
1520 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1523 chip->write_buf(mtd, buf, mtd->writesize);
1524 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1528 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1529 * @mtd: mtd info structure
1530 * @chip: nand chip info structure
1533 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1536 int i, eccsize = chip->ecc.size;
1537 int eccbytes = chip->ecc.bytes;
1538 int eccsteps = chip->ecc.steps;
1539 uint8_t *ecc_calc = chip->buffers->ecccalc;
1540 const uint8_t *p = buf;
1541 uint32_t *eccpos = chip->ecc.layout->eccpos;
1543 /* Software ecc calculation */
1544 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1545 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1547 for (i = 0; i < chip->ecc.total; i++)
1548 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1550 chip->ecc.write_page_raw(mtd, chip, buf);
1554 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1555 * @mtd: mtd info structure
1556 * @chip: nand chip info structure
1559 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1562 int i, eccsize = chip->ecc.size;
1563 int eccbytes = chip->ecc.bytes;
1564 int eccsteps = chip->ecc.steps;
1565 uint8_t *ecc_calc = chip->buffers->ecccalc;
1566 const uint8_t *p = buf;
1567 uint32_t *eccpos = chip->ecc.layout->eccpos;
1569 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1570 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1571 chip->write_buf(mtd, p, eccsize);
1572 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1575 for (i = 0; i < chip->ecc.total; i++)
1576 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1578 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1582 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1583 * @mtd: mtd info structure
1584 * @chip: nand chip info structure
1587 * The hw generator calculates the error syndrome automatically. Therefor
1588 * we need a special oob layout and handling.
1590 static void nand_write_page_syndrome(struct mtd_info *mtd,
1591 struct nand_chip *chip, const uint8_t *buf)
1593 int i, eccsize = chip->ecc.size;
1594 int eccbytes = chip->ecc.bytes;
1595 int eccsteps = chip->ecc.steps;
1596 const uint8_t *p = buf;
1597 uint8_t *oob = chip->oob_poi;
1599 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1601 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1602 chip->write_buf(mtd, p, eccsize);
1604 if (chip->ecc.prepad) {
1605 chip->write_buf(mtd, oob, chip->ecc.prepad);
1606 oob += chip->ecc.prepad;
1609 chip->ecc.calculate(mtd, p, oob);
1610 chip->write_buf(mtd, oob, eccbytes);
1613 if (chip->ecc.postpad) {
1614 chip->write_buf(mtd, oob, chip->ecc.postpad);
1615 oob += chip->ecc.postpad;
1619 /* Calculate remaining oob bytes */
1620 i = mtd->oobsize - (oob - chip->oob_poi);
1622 chip->write_buf(mtd, oob, i);
1626 * nand_write_page - [REPLACEABLE] write one page
1627 * @mtd: MTD device structure
1628 * @chip: NAND chip descriptor
1629 * @buf: the data to write
1630 * @page: page number to write
1631 * @cached: cached programming
1632 * @raw: use _raw version of write_page
1634 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1635 const uint8_t *buf, int page, int cached, int raw)
1639 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1642 chip->ecc.write_page_raw(mtd, chip, buf);
1644 chip->ecc.write_page(mtd, chip, buf);
1647 * Cached progamming disabled for now, Not sure if its worth the
1648 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1652 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1654 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1655 status = chip->waitfunc(mtd, chip);
1657 * See if operation failed and additional status checks are
1660 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1661 status = chip->errstat(mtd, chip, FL_WRITING, status,
1664 if (status & NAND_STATUS_FAIL)
1667 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1668 status = chip->waitfunc(mtd, chip);
1671 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1672 /* Send command to read back the data */
1673 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1675 if (chip->verify_buf(mtd, buf, mtd->writesize))
1682 * nand_fill_oob - [Internal] Transfer client buffer to oob
1683 * @chip: nand chip structure
1684 * @oob: oob data buffer
1685 * @ops: oob ops structure
1687 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1688 struct mtd_oob_ops *ops)
1690 size_t len = ops->ooblen;
1696 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1699 case MTD_OOB_AUTO: {
1700 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1701 uint32_t boffs = 0, woffs = ops->ooboffs;
1704 for(; free->length && len; free++, len -= bytes) {
1705 /* Write request not from offset 0 ? */
1706 if (unlikely(woffs)) {
1707 if (woffs >= free->length) {
1708 woffs -= free->length;
1711 boffs = free->offset + woffs;
1712 bytes = min_t(size_t, len,
1713 (free->length - woffs));
1716 bytes = min_t(size_t, len, free->length);
1717 boffs = free->offset;
1719 memcpy(chip->oob_poi + boffs, oob, bytes);
1730 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1733 * nand_do_write_ops - [Internal] NAND write with ECC
1734 * @mtd: MTD device structure
1735 * @to: offset to write to
1736 * @ops: oob operations description structure
1738 * NAND write with ECC
1740 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1741 struct mtd_oob_ops *ops)
1743 int chipnr, realpage, page, blockmask, column;
1744 struct nand_chip *chip = mtd->priv;
1745 uint32_t writelen = ops->len;
1746 uint8_t *oob = ops->oobbuf;
1747 uint8_t *buf = ops->datbuf;
1754 /* reject writes, which are not page aligned */
1755 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1756 printk(KERN_NOTICE "nand_write: "
1757 "Attempt to write not page aligned data\n");
1761 column = to & (mtd->writesize - 1);
1762 subpage = column || (writelen & (mtd->writesize - 1));
1767 chipnr = (int)(to >> chip->chip_shift);
1768 chip->select_chip(mtd, chipnr);
1770 /* Check, if it is write protected */
1771 if (nand_check_wp(mtd)) {
1772 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1776 realpage = (int)(to >> chip->page_shift);
1777 page = realpage & chip->pagemask;
1778 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1780 /* Invalidate the page cache, when we write to the cached page */
1781 if (to <= (chip->pagebuf << chip->page_shift) &&
1782 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1785 /* If we're not given explicit OOB data, let it be 0xFF */
1787 memset(chip->oob_poi, 0xff, mtd->oobsize);
1790 int bytes = mtd->writesize;
1791 int cached = writelen > bytes && page != blockmask;
1792 uint8_t *wbuf = buf;
1794 /* Partial page write ? */
1795 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1797 bytes = min_t(int, bytes - column, (int) writelen);
1799 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1800 memcpy(&chip->buffers->databuf[column], buf, bytes);
1801 wbuf = chip->buffers->databuf;
1805 oob = nand_fill_oob(chip, oob, ops);
1807 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1808 (ops->mode == MTD_OOB_RAW));
1820 page = realpage & chip->pagemask;
1821 /* Check, if we cross a chip boundary */
1824 chip->select_chip(mtd, -1);
1825 chip->select_chip(mtd, chipnr);
1829 ops->retlen = ops->len - writelen;
1831 ops->oobretlen = ops->ooblen;
1836 * nand_write - [MTD Interface] NAND write with ECC
1837 * @mtd: MTD device structure
1838 * @to: offset to write to
1839 * @len: number of bytes to write
1840 * @retlen: pointer to variable to store the number of written bytes
1841 * @buf: the data to write
1843 * NAND write with ECC
1845 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1846 size_t *retlen, const uint8_t *buf)
1848 struct nand_chip *chip = mtd->priv;
1851 /* Do not allow reads past end of device */
1852 if ((to + len) > mtd->size)
1857 nand_get_device(chip, mtd, FL_WRITING);
1859 chip->ops.len = len;
1860 chip->ops.datbuf = (uint8_t *)buf;
1861 chip->ops.oobbuf = NULL;
1863 ret = nand_do_write_ops(mtd, to, &chip->ops);
1865 *retlen = chip->ops.retlen;
1867 nand_release_device(mtd);
1873 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1874 * @mtd: MTD device structure
1875 * @to: offset to write to
1876 * @ops: oob operation description structure
1878 * NAND write out-of-band
1880 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1881 struct mtd_oob_ops *ops)
1883 int chipnr, page, status, len;
1884 struct nand_chip *chip = mtd->priv;
1886 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1887 (unsigned int)to, (int)ops->ooblen);
1889 if (ops->mode == MTD_OOB_AUTO)
1890 len = chip->ecc.layout->oobavail;
1894 /* Do not allow write past end of page */
1895 if ((ops->ooboffs + ops->ooblen) > len) {
1896 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1897 "Attempt to write past end of page\n");
1901 if (unlikely(ops->ooboffs >= len)) {
1902 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1903 "Attempt to start write outside oob\n");
1907 /* Do not allow reads past end of device */
1908 if (unlikely(to >= mtd->size ||
1909 ops->ooboffs + ops->ooblen >
1910 ((mtd->size >> chip->page_shift) -
1911 (to >> chip->page_shift)) * len)) {
1912 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1913 "Attempt write beyond end of device\n");
1917 chipnr = (int)(to >> chip->chip_shift);
1918 chip->select_chip(mtd, chipnr);
1920 /* Shift to get page */
1921 page = (int)(to >> chip->page_shift);
1924 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1925 * of my DiskOnChip 2000 test units) will clear the whole data page too
1926 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1927 * it in the doc2000 driver in August 1999. dwmw2.
1929 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1931 /* Check, if it is write protected */
1932 if (nand_check_wp(mtd))
1935 /* Invalidate the page cache, if we write to the cached page */
1936 if (page == chip->pagebuf)
1939 memset(chip->oob_poi, 0xff, mtd->oobsize);
1940 nand_fill_oob(chip, ops->oobbuf, ops);
1941 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1942 memset(chip->oob_poi, 0xff, mtd->oobsize);
1947 ops->oobretlen = ops->ooblen;
1953 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1954 * @mtd: MTD device structure
1955 * @to: offset to write to
1956 * @ops: oob operation description structure
1958 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1959 struct mtd_oob_ops *ops)
1961 struct nand_chip *chip = mtd->priv;
1962 int ret = -ENOTSUPP;
1966 /* Do not allow writes past end of device */
1967 if (ops->datbuf && (to + ops->len) > mtd->size) {
1968 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1969 "Attempt read beyond end of device\n");
1973 nand_get_device(chip, mtd, FL_WRITING);
1986 ret = nand_do_write_oob(mtd, to, ops);
1988 ret = nand_do_write_ops(mtd, to, ops);
1991 nand_release_device(mtd);
1996 * single_erease_cmd - [GENERIC] NAND standard block erase command function
1997 * @mtd: MTD device structure
1998 * @page: the page address of the block which will be erased
2000 * Standard erase command for NAND chips
2002 static void single_erase_cmd(struct mtd_info *mtd, int page)
2004 struct nand_chip *chip = mtd->priv;
2005 /* Send commands to erase a block */
2006 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2007 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2011 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2012 * @mtd: MTD device structure
2013 * @page: the page address of the block which will be erased
2015 * AND multi block erase command function
2016 * Erase 4 consecutive blocks
2018 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2020 struct nand_chip *chip = mtd->priv;
2021 /* Send commands to erase a block */
2022 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2023 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2024 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2025 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2026 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2030 * nand_erase - [MTD Interface] erase block(s)
2031 * @mtd: MTD device structure
2032 * @instr: erase instruction
2034 * Erase one ore more blocks
2036 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2038 return nand_erase_nand(mtd, instr, 0);
2041 #define BBT_PAGE_MASK 0xffffff3f
2043 * nand_erase_nand - [Internal] erase block(s)
2044 * @mtd: MTD device structure
2045 * @instr: erase instruction
2046 * @allowbbt: allow erasing the bbt area
2048 * Erase one ore more blocks
2050 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2053 int page, len, status, pages_per_block, ret, chipnr;
2054 struct nand_chip *chip = mtd->priv;
2055 int rewrite_bbt[NAND_MAX_CHIPS]={0};
2056 unsigned int bbt_masked_page = 0xffffffff;
2058 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2059 (unsigned int) instr->addr, (unsigned int) instr->len);
2061 /* Start address must align on block boundary */
2062 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2063 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2067 /* Length must align on block boundary */
2068 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2069 MTDDEBUG (MTD_DEBUG_LEVEL0,
2070 "nand_erase: Length not block aligned\n");
2074 /* Do not allow erase past end of device */
2075 if ((instr->len + instr->addr) > mtd->size) {
2076 MTDDEBUG (MTD_DEBUG_LEVEL0,
2077 "nand_erase: Erase past end of device\n");
2081 instr->fail_addr = 0xffffffff;
2083 /* Grab the lock and see if the device is available */
2084 nand_get_device(chip, mtd, FL_ERASING);
2086 /* Shift to get first page */
2087 page = (int)(instr->addr >> chip->page_shift);
2088 chipnr = (int)(instr->addr >> chip->chip_shift);
2090 /* Calculate pages in each block */
2091 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2093 /* Select the NAND device */
2094 chip->select_chip(mtd, chipnr);
2096 /* Check, if it is write protected */
2097 if (nand_check_wp(mtd)) {
2098 MTDDEBUG (MTD_DEBUG_LEVEL0,
2099 "nand_erase: Device is write protected!!!\n");
2100 instr->state = MTD_ERASE_FAILED;
2105 * If BBT requires refresh, set the BBT page mask to see if the BBT
2106 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2107 * can not be matched. This is also done when the bbt is actually
2108 * erased to avoid recusrsive updates
2110 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2111 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2113 /* Loop through the pages */
2116 instr->state = MTD_ERASING;
2120 * heck if we have a bad block, we do not erase bad blocks !
2122 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2123 chip->page_shift, 0, allowbbt)) {
2124 printk(KERN_WARNING "nand_erase: attempt to erase a "
2125 "bad block at page 0x%08x\n", page);
2126 instr->state = MTD_ERASE_FAILED;
2131 * Invalidate the page cache, if we erase the block which
2132 * contains the current cached page
2134 if (page <= chip->pagebuf && chip->pagebuf <
2135 (page + pages_per_block))
2138 chip->erase_cmd(mtd, page & chip->pagemask);
2140 status = chip->waitfunc(mtd, chip);
2143 * See if operation failed and additional status checks are
2146 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2147 status = chip->errstat(mtd, chip, FL_ERASING,
2150 /* See if block erase succeeded */
2151 if (status & NAND_STATUS_FAIL) {
2152 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2153 "Failed erase, page 0x%08x\n", page);
2154 instr->state = MTD_ERASE_FAILED;
2155 instr->fail_addr = (page << chip->page_shift);
2160 * If BBT requires refresh, set the BBT rewrite flag to the
2163 if (bbt_masked_page != 0xffffffff &&
2164 (page & BBT_PAGE_MASK) == bbt_masked_page)
2165 rewrite_bbt[chipnr] = (page << chip->page_shift);
2167 /* Increment page address and decrement length */
2168 len -= (1 << chip->phys_erase_shift);
2169 page += pages_per_block;
2171 /* Check, if we cross a chip boundary */
2172 if (len && !(page & chip->pagemask)) {
2174 chip->select_chip(mtd, -1);
2175 chip->select_chip(mtd, chipnr);
2178 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2179 * page mask to see if this BBT should be rewritten
2181 if (bbt_masked_page != 0xffffffff &&
2182 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2183 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2187 instr->state = MTD_ERASE_DONE;
2191 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2192 /* Do call back function */
2194 mtd_erase_callback(instr);
2196 /* Deselect and wake up anyone waiting on the device */
2197 nand_release_device(mtd);
2200 * If BBT requires refresh and erase was successful, rewrite any
2201 * selected bad block tables
2203 if (bbt_masked_page == 0xffffffff || ret)
2206 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2207 if (!rewrite_bbt[chipnr])
2209 /* update the BBT for chip */
2210 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2211 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2212 chip->bbt_td->pages[chipnr]);
2213 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2216 /* Return more or less happy */
2221 * nand_sync - [MTD Interface] sync
2222 * @mtd: MTD device structure
2224 * Sync is actually a wait for chip ready function
2226 static void nand_sync(struct mtd_info *mtd)
2228 struct nand_chip *chip = mtd->priv;
2230 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2232 /* Grab the lock and see if the device is available */
2233 nand_get_device(chip, mtd, FL_SYNCING);
2234 /* Release it and go back */
2235 nand_release_device(mtd);
2239 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2240 * @mtd: MTD device structure
2241 * @offs: offset relative to mtd start
2243 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2245 /* Check for invalid offset */
2246 if (offs > mtd->size)
2249 return nand_block_checkbad(mtd, offs, 1, 0);
2253 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2254 * @mtd: MTD device structure
2255 * @ofs: offset relative to mtd start
2257 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2259 struct nand_chip *chip = mtd->priv;
2262 if ((ret = nand_block_isbad(mtd, ofs))) {
2263 /* If it was bad already, return success and do nothing. */
2269 return chip->block_markbad(mtd, ofs);
2273 * nand_suspend - [MTD Interface] Suspend the NAND flash
2274 * @mtd: MTD device structure
2276 static int nand_suspend(struct mtd_info *mtd)
2278 struct nand_chip *chip = mtd->priv;
2280 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2284 * nand_resume - [MTD Interface] Resume the NAND flash
2285 * @mtd: MTD device structure
2287 static void nand_resume(struct mtd_info *mtd)
2289 struct nand_chip *chip = mtd->priv;
2291 if (chip->state == FL_PM_SUSPENDED)
2292 nand_release_device(mtd);
2294 printk(KERN_ERR "nand_resume() called for a chip which is not "
2295 "in suspended state\n");
2299 * Set default functions
2301 static void nand_set_defaults(struct nand_chip *chip, int busw)
2303 /* check for proper chip_delay setup, set 20us if not */
2304 if (!chip->chip_delay)
2305 chip->chip_delay = 20;
2307 /* check, if a user supplied command function given */
2308 if (chip->cmdfunc == NULL)
2309 chip->cmdfunc = nand_command;
2311 /* check, if a user supplied wait function given */
2312 if (chip->waitfunc == NULL)
2313 chip->waitfunc = nand_wait;
2315 if (!chip->select_chip)
2316 chip->select_chip = nand_select_chip;
2317 if (!chip->read_byte)
2318 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2319 if (!chip->read_word)
2320 chip->read_word = nand_read_word;
2321 if (!chip->block_bad)
2322 chip->block_bad = nand_block_bad;
2323 if (!chip->block_markbad)
2324 chip->block_markbad = nand_default_block_markbad;
2325 if (!chip->write_buf)
2326 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2327 if (!chip->read_buf)
2328 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2329 if (!chip->verify_buf)
2330 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2331 if (!chip->scan_bbt)
2332 chip->scan_bbt = nand_default_bbt;
2334 if (!chip->controller) {
2335 chip->controller = &chip->hwcontrol;
2337 /* XXX U-BOOT XXX */
2339 spin_lock_init(&chip->controller->lock);
2340 init_waitqueue_head(&chip->controller->wq);
2347 * Get the flash and manufacturer id and lookup if the type is supported
2349 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2350 struct nand_chip *chip,
2351 int busw, int *maf_id)
2353 struct nand_flash_dev *type = NULL;
2354 int i, dev_id, maf_idx;
2356 /* Select the device */
2357 chip->select_chip(mtd, 0);
2359 /* Send the command for reading device ID */
2360 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2362 /* Read manufacturer and device IDs */
2363 *maf_id = chip->read_byte(mtd);
2364 dev_id = chip->read_byte(mtd);
2366 /* Lookup the flash id */
2367 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2368 if (dev_id == nand_flash_ids[i].id) {
2369 type = &nand_flash_ids[i];
2375 return ERR_PTR(-ENODEV);
2378 mtd->name = type->name;
2380 chip->chipsize = type->chipsize << 20;
2382 /* Newer devices have all the information in additional id bytes */
2383 if (!type->pagesize) {
2385 /* The 3rd id byte holds MLC / multichip data */
2386 chip->cellinfo = chip->read_byte(mtd);
2387 /* The 4th id byte is the important one */
2388 extid = chip->read_byte(mtd);
2390 mtd->writesize = 1024 << (extid & 0x3);
2393 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2395 /* Calc blocksize. Blocksize is multiples of 64KiB */
2396 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2398 /* Get buswidth information */
2399 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2403 * Old devices have chip data hardcoded in the device id table
2405 mtd->erasesize = type->erasesize;
2406 mtd->writesize = type->pagesize;
2407 mtd->oobsize = mtd->writesize / 32;
2408 busw = type->options & NAND_BUSWIDTH_16;
2411 /* Try to identify manufacturer */
2412 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2413 if (nand_manuf_ids[maf_idx].id == *maf_id)
2418 * Check, if buswidth is correct. Hardware drivers should set
2421 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2422 printk(KERN_INFO "NAND device: Manufacturer ID:"
2423 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2424 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2425 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2426 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2428 return ERR_PTR(-EINVAL);
2431 /* Calculate the address shift from the page size */
2432 chip->page_shift = ffs(mtd->writesize) - 1;
2433 /* Convert chipsize to number of pages per chip -1. */
2434 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2436 chip->bbt_erase_shift = chip->phys_erase_shift =
2437 ffs(mtd->erasesize) - 1;
2438 chip->chip_shift = ffs(chip->chipsize) - 1;
2440 /* Set the bad block position */
2441 chip->badblockpos = mtd->writesize > 512 ?
2442 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2444 /* Get chip options, preserve non chip based options */
2445 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2446 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2449 * Set chip as a default. Board drivers can override it, if necessary
2451 chip->options |= NAND_NO_AUTOINCR;
2453 /* Check if chip is a not a samsung device. Do not clear the
2454 * options for chips which are not having an extended id.
2456 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2457 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2459 /* Check for AND chips with 4 page planes */
2460 if (chip->options & NAND_4PAGE_ARRAY)
2461 chip->erase_cmd = multi_erase_cmd;
2463 chip->erase_cmd = single_erase_cmd;
2465 /* Do not replace user supplied command function ! */
2466 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2467 chip->cmdfunc = nand_command_lp;
2469 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2470 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2471 nand_manuf_ids[maf_idx].name, type->name);
2477 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2478 * @mtd: MTD device structure
2479 * @maxchips: Number of chips to scan for
2481 * This is the first phase of the normal nand_scan() function. It
2482 * reads the flash ID and sets up MTD fields accordingly.
2484 * The mtd->owner field must be set to the module of the caller.
2486 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2488 int i, busw, nand_maf_id;
2489 struct nand_chip *chip = mtd->priv;
2490 struct nand_flash_dev *type;
2492 /* Get buswidth to select the correct functions */
2493 busw = chip->options & NAND_BUSWIDTH_16;
2494 /* Set the default functions */
2495 nand_set_defaults(chip, busw);
2497 /* Read the flash type */
2498 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2501 printk(KERN_WARNING "No NAND device found!!!\n");
2502 chip->select_chip(mtd, -1);
2503 return PTR_ERR(type);
2506 /* Check for a chip array */
2507 for (i = 1; i < maxchips; i++) {
2508 chip->select_chip(mtd, i);
2509 /* Send the command for reading device ID */
2510 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2511 /* Read manufacturer and device IDs */
2512 if (nand_maf_id != chip->read_byte(mtd) ||
2513 type->id != chip->read_byte(mtd))
2517 printk(KERN_INFO "%d NAND chips detected\n", i);
2519 /* Store the number of chips and calc total size for mtd */
2521 mtd->size = i * chip->chipsize;
2528 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2529 * @mtd: MTD device structure
2530 * @maxchips: Number of chips to scan for
2532 * This is the second phase of the normal nand_scan() function. It
2533 * fills out all the uninitialized function pointers with the defaults
2534 * and scans for a bad block table if appropriate.
2536 int nand_scan_tail(struct mtd_info *mtd)
2539 struct nand_chip *chip = mtd->priv;
2541 if (!(chip->options & NAND_OWN_BUFFERS))
2542 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2546 /* Set the internal oob buffer location, just after the page data */
2547 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2550 * If no default placement scheme is given, select an appropriate one
2552 if (!chip->ecc.layout) {
2553 switch (mtd->oobsize) {
2555 chip->ecc.layout = &nand_oob_8;
2558 chip->ecc.layout = &nand_oob_16;
2561 chip->ecc.layout = &nand_oob_64;
2564 chip->ecc.layout = &nand_oob_128;
2567 printk(KERN_WARNING "No oob scheme defined for "
2568 "oobsize %d\n", mtd->oobsize);
2573 if (!chip->write_page)
2574 chip->write_page = nand_write_page;
2577 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2578 * selected and we have 256 byte pagesize fallback to software ECC
2580 if (!chip->ecc.read_page_raw)
2581 chip->ecc.read_page_raw = nand_read_page_raw;
2582 if (!chip->ecc.write_page_raw)
2583 chip->ecc.write_page_raw = nand_write_page_raw;
2585 switch (chip->ecc.mode) {
2587 /* Use standard hwecc read page function ? */
2588 if (!chip->ecc.read_page)
2589 chip->ecc.read_page = nand_read_page_hwecc;
2590 if (!chip->ecc.write_page)
2591 chip->ecc.write_page = nand_write_page_hwecc;
2592 if (!chip->ecc.read_oob)
2593 chip->ecc.read_oob = nand_read_oob_std;
2594 if (!chip->ecc.write_oob)
2595 chip->ecc.write_oob = nand_write_oob_std;
2597 case NAND_ECC_HW_SYNDROME:
2598 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2599 !chip->ecc.hwctl) &&
2600 (!chip->ecc.read_page ||
2601 chip->ecc.read_page == nand_read_page_hwecc ||
2602 !chip->ecc.write_page ||
2603 chip->ecc.write_page == nand_write_page_hwecc)) {
2604 printk(KERN_WARNING "No ECC functions supplied, "
2605 "Hardware ECC not possible\n");
2608 /* Use standard syndrome read/write page function ? */
2609 if (!chip->ecc.read_page)
2610 chip->ecc.read_page = nand_read_page_syndrome;
2611 if (!chip->ecc.write_page)
2612 chip->ecc.write_page = nand_write_page_syndrome;
2613 if (!chip->ecc.read_oob)
2614 chip->ecc.read_oob = nand_read_oob_syndrome;
2615 if (!chip->ecc.write_oob)
2616 chip->ecc.write_oob = nand_write_oob_syndrome;
2618 if (mtd->writesize >= chip->ecc.size)
2620 printk(KERN_WARNING "%d byte HW ECC not possible on "
2621 "%d byte page size, fallback to SW ECC\n",
2622 chip->ecc.size, mtd->writesize);
2623 chip->ecc.mode = NAND_ECC_SOFT;
2626 chip->ecc.calculate = nand_calculate_ecc;
2627 chip->ecc.correct = nand_correct_data;
2628 chip->ecc.read_page = nand_read_page_swecc;
2629 chip->ecc.write_page = nand_write_page_swecc;
2630 chip->ecc.read_oob = nand_read_oob_std;
2631 chip->ecc.write_oob = nand_write_oob_std;
2632 chip->ecc.size = 256;
2633 chip->ecc.bytes = 3;
2637 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2638 "This is not recommended !!\n");
2639 chip->ecc.read_page = nand_read_page_raw;
2640 chip->ecc.write_page = nand_write_page_raw;
2641 chip->ecc.read_oob = nand_read_oob_std;
2642 chip->ecc.write_oob = nand_write_oob_std;
2643 chip->ecc.size = mtd->writesize;
2644 chip->ecc.bytes = 0;
2648 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2654 * The number of bytes available for a client to place data into
2655 * the out of band area
2657 chip->ecc.layout->oobavail = 0;
2658 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2659 chip->ecc.layout->oobavail +=
2660 chip->ecc.layout->oobfree[i].length;
2661 mtd->oobavail = chip->ecc.layout->oobavail;
2664 * Set the number of read / write steps for one page depending on ECC
2667 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2668 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2669 printk(KERN_WARNING "Invalid ecc parameters\n");
2672 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2675 * Allow subpage writes up to ecc.steps. Not possible for MLC
2678 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2679 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2680 switch(chip->ecc.steps) {
2682 mtd->subpage_sft = 1;
2686 mtd->subpage_sft = 2;
2690 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2692 /* Initialize state */
2693 chip->state = FL_READY;
2695 /* De-select the device */
2696 chip->select_chip(mtd, -1);
2698 /* Invalidate the pagebuffer reference */
2701 /* Fill in remaining MTD driver data */
2702 mtd->type = MTD_NANDFLASH;
2703 mtd->flags = MTD_CAP_NANDFLASH;
2704 mtd->erase = nand_erase;
2706 mtd->unpoint = NULL;
2707 mtd->read = nand_read;
2708 mtd->write = nand_write;
2709 mtd->read_oob = nand_read_oob;
2710 mtd->write_oob = nand_write_oob;
2711 mtd->sync = nand_sync;
2714 mtd->suspend = nand_suspend;
2715 mtd->resume = nand_resume;
2716 mtd->block_isbad = nand_block_isbad;
2717 mtd->block_markbad = nand_block_markbad;
2719 /* propagate ecc.layout to mtd_info */
2720 mtd->ecclayout = chip->ecc.layout;
2722 /* Check, if we should skip the bad block table scan */
2723 if (chip->options & NAND_SKIP_BBTSCAN)
2726 /* Build bad block table */
2727 return chip->scan_bbt(mtd);
2730 /* module_text_address() isn't exported, and it's mostly a pointless
2731 test if this is a module _anyway_ -- they'd have to try _really_ hard
2732 to call us from in-kernel code if the core NAND support is modular. */
2734 #define caller_is_module() (1)
2736 #define caller_is_module() \
2737 module_text_address((unsigned long)__builtin_return_address(0))
2741 * nand_scan - [NAND Interface] Scan for the NAND device
2742 * @mtd: MTD device structure
2743 * @maxchips: Number of chips to scan for
2745 * This fills out all the uninitialized function pointers
2746 * with the defaults.
2747 * The flash ID is read and the mtd/chip structures are
2748 * filled with the appropriate values.
2749 * The mtd->owner field must be set to the module of the caller
2752 int nand_scan(struct mtd_info *mtd, int maxchips)
2756 /* Many callers got this wrong, so check for it for a while... */
2757 /* XXX U-BOOT XXX */
2759 if (!mtd->owner && caller_is_module()) {
2760 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2765 ret = nand_scan_ident(mtd, maxchips);
2767 ret = nand_scan_tail(mtd);
2772 * nand_release - [NAND Interface] Free resources held by the NAND device
2773 * @mtd: MTD device structure
2775 void nand_release(struct mtd_info *mtd)
2777 struct nand_chip *chip = mtd->priv;
2779 #ifdef CONFIG_MTD_PARTITIONS
2780 /* Deregister partitions */
2781 del_mtd_partitions(mtd);
2783 /* Deregister the device */
2784 /* XXX U-BOOT XXX */
2786 del_mtd_device(mtd);
2789 /* Free bad block table memory */
2791 if (!(chip->options & NAND_OWN_BUFFERS))
2792 kfree(chip->buffers);
2795 /* XXX U-BOOT XXX */
2797 EXPORT_SYMBOL_GPL(nand_scan);
2798 EXPORT_SYMBOL_GPL(nand_scan_ident);
2799 EXPORT_SYMBOL_GPL(nand_scan_tail);
2800 EXPORT_SYMBOL_GPL(nand_release);
2802 static int __init nand_base_init(void)
2804 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2808 static void __exit nand_base_exit(void)
2810 led_trigger_unregister_simple(nand_led_trigger);
2813 module_init(nand_base_init);
2814 module_exit(nand_base_exit);
2816 MODULE_LICENSE("GPL");
2817 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2818 MODULE_DESCRIPTION("Generic NAND flash driver code");