5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36 #include <linux/err.h>
37 #include <linux/compat.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/nand.h>
40 #include <linux/mtd/nand_ecc.h>
41 #include <linux/mtd/nand_bch.h>
42 #ifdef CONFIG_MTD_PARTITIONS
43 #include <linux/mtd/partitions.h>
46 #include <asm/errno.h>
48 static bool is_module_text_address(unsigned long addr) {return 0;}
50 /* Define default oob placement schemes for large and small page devices */
51 static struct nand_ecclayout nand_oob_8 = {
61 static struct nand_ecclayout nand_oob_16 = {
63 .eccpos = {0, 1, 2, 3, 6, 7},
69 static struct nand_ecclayout nand_oob_64 = {
72 40, 41, 42, 43, 44, 45, 46, 47,
73 48, 49, 50, 51, 52, 53, 54, 55,
74 56, 57, 58, 59, 60, 61, 62, 63},
80 static struct nand_ecclayout nand_oob_128 = {
83 80, 81, 82, 83, 84, 85, 86, 87,
84 88, 89, 90, 91, 92, 93, 94, 95,
85 96, 97, 98, 99, 100, 101, 102, 103,
86 104, 105, 106, 107, 108, 109, 110, 111,
87 112, 113, 114, 115, 116, 117, 118, 119,
88 120, 121, 122, 123, 124, 125, 126, 127},
94 static int nand_get_device(struct mtd_info *mtd, int new_state);
96 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
97 struct mtd_oob_ops *ops);
100 * For devices which display every fart in the system on a separate LED. Is
101 * compiled away when LED support is disabled.
103 DEFINE_LED_TRIGGER(nand_led_trigger);
105 static int check_offs_len(struct mtd_info *mtd,
106 loff_t ofs, uint64_t len)
108 struct nand_chip *chip = mtd->priv;
111 /* Start address must align on block boundary */
112 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
113 pr_debug("%s: unaligned address\n", __func__);
117 /* Length must align on block boundary */
118 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
119 pr_debug("%s: length not block aligned\n", __func__);
127 * nand_release_device - [GENERIC] release chip
128 * @mtd: MTD device structure
130 * Release chip lock and wake up anyone waiting on the device.
132 static void nand_release_device(struct mtd_info *mtd)
134 struct nand_chip *chip = mtd->priv;
136 /* De-select the NAND device */
137 chip->select_chip(mtd, -1);
141 * nand_read_byte - [DEFAULT] read one byte from the chip
142 * @mtd: MTD device structure
144 * Default read function for 8bit buswidth
146 uint8_t nand_read_byte(struct mtd_info *mtd)
148 struct nand_chip *chip = mtd->priv;
149 return readb(chip->IO_ADDR_R);
153 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
154 * @mtd: MTD device structure
156 * Default read function for 16bit buswidth with endianness conversion.
159 static uint8_t nand_read_byte16(struct mtd_info *mtd)
161 struct nand_chip *chip = mtd->priv;
162 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
166 * nand_read_word - [DEFAULT] read one word from the chip
167 * @mtd: MTD device structure
169 * Default read function for 16bit buswidth without endianness conversion.
171 static u16 nand_read_word(struct mtd_info *mtd)
173 struct nand_chip *chip = mtd->priv;
174 return readw(chip->IO_ADDR_R);
178 * nand_select_chip - [DEFAULT] control CE line
179 * @mtd: MTD device structure
180 * @chipnr: chipnumber to select, -1 for deselect
182 * Default select function for 1 chip devices.
184 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
186 struct nand_chip *chip = mtd->priv;
190 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
201 * nand_write_byte - [DEFAULT] write single byte to chip
202 * @mtd: MTD device structure
203 * @byte: value to write
205 * Default function to write a byte to I/O[7:0]
207 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
209 struct nand_chip *chip = mtd->priv;
211 chip->write_buf(mtd, &byte, 1);
215 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
216 * @mtd: MTD device structure
217 * @byte: value to write
219 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
221 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
223 struct nand_chip *chip = mtd->priv;
224 uint16_t word = byte;
227 * It's not entirely clear what should happen to I/O[15:8] when writing
228 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
230 * When the host supports a 16-bit bus width, only data is
231 * transferred at the 16-bit width. All address and command line
232 * transfers shall use only the lower 8-bits of the data bus. During
233 * command transfers, the host may place any value on the upper
234 * 8-bits of the data bus. During address transfers, the host shall
235 * set the upper 8-bits of the data bus to 00h.
237 * One user of the write_byte callback is nand_onfi_set_features. The
238 * four parameters are specified to be written to I/O[7:0], but this is
239 * neither an address nor a command transfer. Let's assume a 0 on the
240 * upper I/O lines is OK.
242 chip->write_buf(mtd, (uint8_t *)&word, 2);
245 #if !defined(CONFIG_BLACKFIN)
246 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
250 for (i = 0; i < len; i++)
251 writeb(buf[i], addr);
253 static void ioread8_rep(void *addr, uint8_t *buf, int len)
257 for (i = 0; i < len; i++)
258 buf[i] = readb(addr);
261 static void ioread16_rep(void *addr, void *buf, int len)
264 u16 *p = (u16 *) buf;
266 for (i = 0; i < len; i++)
270 static void iowrite16_rep(void *addr, void *buf, int len)
273 u16 *p = (u16 *) buf;
275 for (i = 0; i < len; i++)
281 * nand_write_buf - [DEFAULT] write buffer to chip
282 * @mtd: MTD device structure
284 * @len: number of bytes to write
286 * Default write function for 8bit buswidth.
288 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
290 struct nand_chip *chip = mtd->priv;
292 iowrite8_rep(chip->IO_ADDR_W, buf, len);
296 * nand_read_buf - [DEFAULT] read chip data into buffer
297 * @mtd: MTD device structure
298 * @buf: buffer to store date
299 * @len: number of bytes to read
301 * Default read function for 8bit buswidth.
303 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
305 struct nand_chip *chip = mtd->priv;
307 ioread8_rep(chip->IO_ADDR_R, buf, len);
311 * nand_write_buf16 - [DEFAULT] write buffer to chip
312 * @mtd: MTD device structure
314 * @len: number of bytes to write
316 * Default write function for 16bit buswidth.
318 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
320 struct nand_chip *chip = mtd->priv;
321 u16 *p = (u16 *) buf;
323 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
327 * nand_read_buf16 - [DEFAULT] read chip data into buffer
328 * @mtd: MTD device structure
329 * @buf: buffer to store date
330 * @len: number of bytes to read
332 * Default read function for 16bit buswidth.
334 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
336 struct nand_chip *chip = mtd->priv;
337 u16 *p = (u16 *) buf;
339 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
343 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
344 * @mtd: MTD device structure
345 * @ofs: offset from device start
346 * @getchip: 0, if the chip is already selected
348 * Check, if the block is bad.
350 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
352 int page, chipnr, res = 0, i = 0;
353 struct nand_chip *chip = mtd->priv;
356 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
357 ofs += mtd->erasesize - mtd->writesize;
359 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
362 chipnr = (int)(ofs >> chip->chip_shift);
364 nand_get_device(mtd, FL_READING);
366 /* Select the NAND device */
367 chip->select_chip(mtd, chipnr);
371 if (chip->options & NAND_BUSWIDTH_16) {
372 chip->cmdfunc(mtd, NAND_CMD_READOOB,
373 chip->badblockpos & 0xFE, page);
374 bad = cpu_to_le16(chip->read_word(mtd));
375 if (chip->badblockpos & 0x1)
380 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
382 bad = chip->read_byte(mtd);
385 if (likely(chip->badblockbits == 8))
388 res = hweight8(bad) < chip->badblockbits;
389 ofs += mtd->writesize;
390 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
392 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
395 chip->select_chip(mtd, -1);
396 nand_release_device(mtd);
403 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
404 * @mtd: MTD device structure
405 * @ofs: offset from device start
407 * This is the default implementation, which can be overridden by a hardware
408 * specific driver. It provides the details for writing a bad block marker to a
411 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
413 struct nand_chip *chip = mtd->priv;
414 struct mtd_oob_ops ops;
415 uint8_t buf[2] = { 0, 0 };
416 int ret = 0, res, i = 0;
418 memset(&ops, 0, sizeof(ops));
420 ops.ooboffs = chip->badblockpos;
421 if (chip->options & NAND_BUSWIDTH_16) {
422 ops.ooboffs &= ~0x01;
423 ops.len = ops.ooblen = 2;
425 ops.len = ops.ooblen = 1;
427 ops.mode = MTD_OPS_PLACE_OOB;
429 /* Write to first/last page(s) if necessary */
430 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
431 ofs += mtd->erasesize - mtd->writesize;
433 res = nand_do_write_oob(mtd, ofs, &ops);
438 ofs += mtd->writesize;
439 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
445 * nand_block_markbad_lowlevel - mark a block bad
446 * @mtd: MTD device structure
447 * @ofs: offset from device start
449 * This function performs the generic NAND bad block marking steps (i.e., bad
450 * block table(s) and/or marker(s)). We only allow the hardware driver to
451 * specify how to write bad block markers to OOB (chip->block_markbad).
453 * We try operations in the following order:
454 * (1) erase the affected block, to allow OOB marker to be written cleanly
455 * (2) write bad block marker to OOB area of affected block (unless flag
456 * NAND_BBT_NO_OOB_BBM is present)
458 * Note that we retain the first error encountered in (2) or (3), finish the
459 * procedures, and dump the error in the end.
461 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
463 struct nand_chip *chip = mtd->priv;
466 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
467 struct erase_info einfo;
469 /* Attempt erase before marking OOB */
470 memset(&einfo, 0, sizeof(einfo));
473 einfo.len = 1ULL << chip->phys_erase_shift;
474 nand_erase_nand(mtd, &einfo, 0);
476 /* Write bad block marker to OOB */
477 nand_get_device(mtd, FL_WRITING);
478 ret = chip->block_markbad(mtd, ofs);
479 nand_release_device(mtd);
482 /* Mark block bad in BBT */
484 res = nand_markbad_bbt(mtd, ofs);
490 mtd->ecc_stats.badblocks++;
496 * nand_check_wp - [GENERIC] check if the chip is write protected
497 * @mtd: MTD device structure
499 * Check, if the device is write protected. The function expects, that the
500 * device is already selected.
502 static int nand_check_wp(struct mtd_info *mtd)
504 struct nand_chip *chip = mtd->priv;
506 /* Broken xD cards report WP despite being writable */
507 if (chip->options & NAND_BROKEN_XD)
510 /* Check the WP bit */
511 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
512 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
516 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
517 * @mtd: MTD device structure
518 * @ofs: offset from device start
520 * Check if the block is marked as reserved.
522 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
524 struct nand_chip *chip = mtd->priv;
528 /* Return info from the table */
529 return nand_isreserved_bbt(mtd, ofs);
533 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
534 * @mtd: MTD device structure
535 * @ofs: offset from device start
536 * @getchip: 0, if the chip is already selected
537 * @allowbbt: 1, if its allowed to access the bbt area
539 * Check, if the block is bad. Either by reading the bad block table or
540 * calling of the scan function.
542 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
545 struct nand_chip *chip = mtd->priv;
547 if (!(chip->options & NAND_SKIP_BBTSCAN) &&
548 !(chip->options & NAND_BBT_SCANNED)) {
549 chip->options |= NAND_BBT_SCANNED;
554 return chip->block_bad(mtd, ofs, getchip);
556 /* Return info from the table */
557 return nand_isbad_bbt(mtd, ofs, allowbbt);
560 /* Wait for the ready pin, after a command. The timeout is caught later. */
561 void nand_wait_ready(struct mtd_info *mtd)
563 struct nand_chip *chip = mtd->priv;
564 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
567 time_start = get_timer(0);
568 /* Wait until command is processed or timeout occurs */
569 while (get_timer(time_start) < timeo) {
571 if (chip->dev_ready(mtd))
575 EXPORT_SYMBOL_GPL(nand_wait_ready);
578 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
579 * @mtd: MTD device structure
580 * @timeo: Timeout in ms
582 * Wait for status ready (i.e. command done) or timeout.
584 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
586 register struct nand_chip *chip = mtd->priv;
589 timeo = (CONFIG_SYS_HZ * timeo) / 1000;
590 time_start = get_timer(0);
591 while (get_timer(time_start) < timeo) {
592 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
599 * nand_command - [DEFAULT] Send command to NAND device
600 * @mtd: MTD device structure
601 * @command: the command to be sent
602 * @column: the column address for this command, -1 if none
603 * @page_addr: the page address for this command, -1 if none
605 * Send command to NAND device. This function is used for small page devices
606 * (512 Bytes per page).
608 static void nand_command(struct mtd_info *mtd, unsigned int command,
609 int column, int page_addr)
611 register struct nand_chip *chip = mtd->priv;
612 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
614 /* Write out the command to the device */
615 if (command == NAND_CMD_SEQIN) {
618 if (column >= mtd->writesize) {
620 column -= mtd->writesize;
621 readcmd = NAND_CMD_READOOB;
622 } else if (column < 256) {
623 /* First 256 bytes --> READ0 */
624 readcmd = NAND_CMD_READ0;
627 readcmd = NAND_CMD_READ1;
629 chip->cmd_ctrl(mtd, readcmd, ctrl);
630 ctrl &= ~NAND_CTRL_CHANGE;
632 chip->cmd_ctrl(mtd, command, ctrl);
634 /* Address cycle, when necessary */
635 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
636 /* Serially input address */
638 /* Adjust columns for 16 bit buswidth */
639 if (chip->options & NAND_BUSWIDTH_16 &&
640 !nand_opcode_8bits(command))
642 chip->cmd_ctrl(mtd, column, ctrl);
643 ctrl &= ~NAND_CTRL_CHANGE;
645 if (page_addr != -1) {
646 chip->cmd_ctrl(mtd, page_addr, ctrl);
647 ctrl &= ~NAND_CTRL_CHANGE;
648 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
649 /* One more address cycle for devices > 32MiB */
650 if (chip->chipsize > (32 << 20))
651 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
653 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
656 * Program and erase have their own busy handlers status and sequential
661 case NAND_CMD_PAGEPROG:
662 case NAND_CMD_ERASE1:
663 case NAND_CMD_ERASE2:
665 case NAND_CMD_STATUS:
671 udelay(chip->chip_delay);
672 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
673 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
675 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
676 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
677 nand_wait_status_ready(mtd, 250);
680 /* This applies to read commands */
683 * If we don't have access to the busy pin, we apply the given
686 if (!chip->dev_ready) {
687 udelay(chip->chip_delay);
692 * Apply this short delay always to ensure that we do wait tWB in
693 * any case on any machine.
697 nand_wait_ready(mtd);
701 * nand_command_lp - [DEFAULT] Send command to NAND large page device
702 * @mtd: MTD device structure
703 * @command: the command to be sent
704 * @column: the column address for this command, -1 if none
705 * @page_addr: the page address for this command, -1 if none
707 * Send command to NAND device. This is the version for the new large page
708 * devices. We don't have the separate regions as we have in the small page
709 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
711 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
712 int column, int page_addr)
714 register struct nand_chip *chip = mtd->priv;
716 /* Emulate NAND_CMD_READOOB */
717 if (command == NAND_CMD_READOOB) {
718 column += mtd->writesize;
719 command = NAND_CMD_READ0;
722 /* Command latch cycle */
723 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
725 if (column != -1 || page_addr != -1) {
726 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
728 /* Serially input address */
730 /* Adjust columns for 16 bit buswidth */
731 if (chip->options & NAND_BUSWIDTH_16 &&
732 !nand_opcode_8bits(command))
734 chip->cmd_ctrl(mtd, column, ctrl);
735 ctrl &= ~NAND_CTRL_CHANGE;
736 chip->cmd_ctrl(mtd, column >> 8, ctrl);
738 if (page_addr != -1) {
739 chip->cmd_ctrl(mtd, page_addr, ctrl);
740 chip->cmd_ctrl(mtd, page_addr >> 8,
741 NAND_NCE | NAND_ALE);
742 /* One more address cycle for devices > 128MiB */
743 if (chip->chipsize > (128 << 20))
744 chip->cmd_ctrl(mtd, page_addr >> 16,
745 NAND_NCE | NAND_ALE);
748 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
751 * Program and erase have their own busy handlers status, sequential
752 * in and status need no delay.
756 case NAND_CMD_CACHEDPROG:
757 case NAND_CMD_PAGEPROG:
758 case NAND_CMD_ERASE1:
759 case NAND_CMD_ERASE2:
762 case NAND_CMD_STATUS:
768 udelay(chip->chip_delay);
769 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
770 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
771 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
772 NAND_NCE | NAND_CTRL_CHANGE);
773 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
774 nand_wait_status_ready(mtd, 250);
777 case NAND_CMD_RNDOUT:
778 /* No ready / busy check necessary */
779 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
780 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
781 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
782 NAND_NCE | NAND_CTRL_CHANGE);
786 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
787 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
788 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
789 NAND_NCE | NAND_CTRL_CHANGE);
791 /* This applies to read commands */
794 * If we don't have access to the busy pin, we apply the given
797 if (!chip->dev_ready) {
798 udelay(chip->chip_delay);
804 * Apply this short delay always to ensure that we do wait tWB in
805 * any case on any machine.
809 nand_wait_ready(mtd);
813 * panic_nand_get_device - [GENERIC] Get chip for selected access
814 * @chip: the nand chip descriptor
815 * @mtd: MTD device structure
816 * @new_state: the state which is requested
818 * Used when in panic, no locks are taken.
820 static void panic_nand_get_device(struct nand_chip *chip,
821 struct mtd_info *mtd, int new_state)
823 /* Hardware controller shared among independent devices */
824 chip->controller->active = chip;
825 chip->state = new_state;
829 * nand_get_device - [GENERIC] Get chip for selected access
830 * @mtd: MTD device structure
831 * @new_state: the state which is requested
833 * Get the device and lock it for exclusive access
836 nand_get_device(struct mtd_info *mtd, int new_state)
838 struct nand_chip *chip = mtd->priv;
839 chip->state = new_state;
844 * panic_nand_wait - [GENERIC] wait until the command is done
845 * @mtd: MTD device structure
846 * @chip: NAND chip structure
849 * Wait for command done. This is a helper function for nand_wait used when
850 * we are in interrupt context. May happen when in panic and trying to write
851 * an oops through mtdoops.
853 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
857 for (i = 0; i < timeo; i++) {
858 if (chip->dev_ready) {
859 if (chip->dev_ready(mtd))
862 if (chip->read_byte(mtd) & NAND_STATUS_READY)
870 * nand_wait - [DEFAULT] wait until the command is done
871 * @mtd: MTD device structure
872 * @chip: NAND chip structure
874 * Wait for command done. This applies to erase and program only. Erase can
875 * take up to 400ms and program up to 20ms according to general NAND and
878 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
881 int status, state = chip->state;
882 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
884 led_trigger_event(nand_led_trigger, LED_FULL);
887 * Apply this short delay always to ensure that we do wait tWB in any
888 * case on any machine.
892 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
894 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
897 time_start = get_timer(0);
898 while (get_timer(time_start) < timer) {
899 if (chip->dev_ready) {
900 if (chip->dev_ready(mtd))
903 if (chip->read_byte(mtd) & NAND_STATUS_READY)
907 led_trigger_event(nand_led_trigger, LED_OFF);
909 status = (int)chip->read_byte(mtd);
910 /* This can happen if in case of timeout or buggy dev_ready */
911 WARN_ON(!(status & NAND_STATUS_READY));
916 * nand_read_page_raw - [INTERN] read raw page data without ecc
917 * @mtd: mtd info structure
918 * @chip: nand chip info structure
919 * @buf: buffer to store read data
920 * @oob_required: caller requires OOB data read to chip->oob_poi
921 * @page: page number to read
923 * Not for syndrome calculating ECC controllers, which use a special oob layout.
925 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
926 uint8_t *buf, int oob_required, int page)
928 chip->read_buf(mtd, buf, mtd->writesize);
930 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
935 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
936 * @mtd: mtd info structure
937 * @chip: nand chip info structure
938 * @buf: buffer to store read data
939 * @oob_required: caller requires OOB data read to chip->oob_poi
940 * @page: page number to read
942 * We need a special oob layout and handling even when OOB isn't used.
944 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
945 struct nand_chip *chip, uint8_t *buf,
946 int oob_required, int page)
948 int eccsize = chip->ecc.size;
949 int eccbytes = chip->ecc.bytes;
950 uint8_t *oob = chip->oob_poi;
953 for (steps = chip->ecc.steps; steps > 0; steps--) {
954 chip->read_buf(mtd, buf, eccsize);
957 if (chip->ecc.prepad) {
958 chip->read_buf(mtd, oob, chip->ecc.prepad);
959 oob += chip->ecc.prepad;
962 chip->read_buf(mtd, oob, eccbytes);
965 if (chip->ecc.postpad) {
966 chip->read_buf(mtd, oob, chip->ecc.postpad);
967 oob += chip->ecc.postpad;
971 size = mtd->oobsize - (oob - chip->oob_poi);
973 chip->read_buf(mtd, oob, size);
979 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
980 * @mtd: mtd info structure
981 * @chip: nand chip info structure
982 * @buf: buffer to store read data
983 * @oob_required: caller requires OOB data read to chip->oob_poi
984 * @page: page number to read
986 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
987 uint8_t *buf, int oob_required, int page)
989 int i, eccsize = chip->ecc.size;
990 int eccbytes = chip->ecc.bytes;
991 int eccsteps = chip->ecc.steps;
993 uint8_t *ecc_calc = chip->buffers->ecccalc;
994 uint8_t *ecc_code = chip->buffers->ecccode;
995 uint32_t *eccpos = chip->ecc.layout->eccpos;
996 unsigned int max_bitflips = 0;
998 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1000 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1001 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1003 for (i = 0; i < chip->ecc.total; i++)
1004 ecc_code[i] = chip->oob_poi[eccpos[i]];
1006 eccsteps = chip->ecc.steps;
1009 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1012 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1014 mtd->ecc_stats.failed++;
1016 mtd->ecc_stats.corrected += stat;
1017 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1020 return max_bitflips;
1024 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1025 * @mtd: mtd info structure
1026 * @chip: nand chip info structure
1027 * @data_offs: offset of requested data within the page
1028 * @readlen: data length
1029 * @bufpoi: buffer to store read data
1030 * @page: page number to read
1032 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1033 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1036 int start_step, end_step, num_steps;
1037 uint32_t *eccpos = chip->ecc.layout->eccpos;
1039 int data_col_addr, i, gaps = 0;
1040 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1041 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1043 unsigned int max_bitflips = 0;
1045 /* Column address within the page aligned to ECC size (256bytes) */
1046 start_step = data_offs / chip->ecc.size;
1047 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1048 num_steps = end_step - start_step + 1;
1049 index = start_step * chip->ecc.bytes;
1051 /* Data size aligned to ECC ecc.size */
1052 datafrag_len = num_steps * chip->ecc.size;
1053 eccfrag_len = num_steps * chip->ecc.bytes;
1055 data_col_addr = start_step * chip->ecc.size;
1056 /* If we read not a page aligned data */
1057 if (data_col_addr != 0)
1058 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1060 p = bufpoi + data_col_addr;
1061 chip->read_buf(mtd, p, datafrag_len);
1064 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1065 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1068 * The performance is faster if we position offsets according to
1069 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1071 for (i = 0; i < eccfrag_len - 1; i++) {
1072 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1078 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1079 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1082 * Send the command to read the particular ECC bytes take care
1083 * about buswidth alignment in read_buf.
1085 aligned_pos = eccpos[index] & ~(busw - 1);
1086 aligned_len = eccfrag_len;
1087 if (eccpos[index] & (busw - 1))
1089 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1092 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1093 mtd->writesize + aligned_pos, -1);
1094 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1097 for (i = 0; i < eccfrag_len; i++)
1098 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1100 p = bufpoi + data_col_addr;
1101 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1104 stat = chip->ecc.correct(mtd, p,
1105 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1107 mtd->ecc_stats.failed++;
1109 mtd->ecc_stats.corrected += stat;
1110 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1113 return max_bitflips;
1117 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1118 * @mtd: mtd info structure
1119 * @chip: nand chip info structure
1120 * @buf: buffer to store read data
1121 * @oob_required: caller requires OOB data read to chip->oob_poi
1122 * @page: page number to read
1124 * Not for syndrome calculating ECC controllers which need a special oob layout.
1126 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1127 uint8_t *buf, int oob_required, int page)
1129 int i, eccsize = chip->ecc.size;
1130 int eccbytes = chip->ecc.bytes;
1131 int eccsteps = chip->ecc.steps;
1133 uint8_t *ecc_calc = chip->buffers->ecccalc;
1134 uint8_t *ecc_code = chip->buffers->ecccode;
1135 uint32_t *eccpos = chip->ecc.layout->eccpos;
1136 unsigned int max_bitflips = 0;
1138 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1139 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1140 chip->read_buf(mtd, p, eccsize);
1141 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1143 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1145 for (i = 0; i < chip->ecc.total; i++)
1146 ecc_code[i] = chip->oob_poi[eccpos[i]];
1148 eccsteps = chip->ecc.steps;
1151 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1154 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1156 mtd->ecc_stats.failed++;
1158 mtd->ecc_stats.corrected += stat;
1159 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1162 return max_bitflips;
1166 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1167 * @mtd: mtd info structure
1168 * @chip: nand chip info structure
1169 * @buf: buffer to store read data
1170 * @oob_required: caller requires OOB data read to chip->oob_poi
1171 * @page: page number to read
1173 * Hardware ECC for large page chips, require OOB to be read first. For this
1174 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1175 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1176 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1177 * the data area, by overwriting the NAND manufacturer bad block markings.
1179 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1180 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1182 int i, eccsize = chip->ecc.size;
1183 int eccbytes = chip->ecc.bytes;
1184 int eccsteps = chip->ecc.steps;
1186 uint8_t *ecc_code = chip->buffers->ecccode;
1187 uint32_t *eccpos = chip->ecc.layout->eccpos;
1188 uint8_t *ecc_calc = chip->buffers->ecccalc;
1189 unsigned int max_bitflips = 0;
1191 /* Read the OOB area first */
1192 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1193 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1194 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1196 for (i = 0; i < chip->ecc.total; i++)
1197 ecc_code[i] = chip->oob_poi[eccpos[i]];
1199 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1202 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1203 chip->read_buf(mtd, p, eccsize);
1204 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1206 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1208 mtd->ecc_stats.failed++;
1210 mtd->ecc_stats.corrected += stat;
1211 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1214 return max_bitflips;
1218 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1219 * @mtd: mtd info structure
1220 * @chip: nand chip info structure
1221 * @buf: buffer to store read data
1222 * @oob_required: caller requires OOB data read to chip->oob_poi
1223 * @page: page number to read
1225 * The hw generator calculates the error syndrome automatically. Therefore we
1226 * need a special oob layout and handling.
1228 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1229 uint8_t *buf, int oob_required, int page)
1231 int i, eccsize = chip->ecc.size;
1232 int eccbytes = chip->ecc.bytes;
1233 int eccsteps = chip->ecc.steps;
1235 uint8_t *oob = chip->oob_poi;
1236 unsigned int max_bitflips = 0;
1238 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1241 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1242 chip->read_buf(mtd, p, eccsize);
1244 if (chip->ecc.prepad) {
1245 chip->read_buf(mtd, oob, chip->ecc.prepad);
1246 oob += chip->ecc.prepad;
1249 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1250 chip->read_buf(mtd, oob, eccbytes);
1251 stat = chip->ecc.correct(mtd, p, oob, NULL);
1254 mtd->ecc_stats.failed++;
1256 mtd->ecc_stats.corrected += stat;
1257 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1262 if (chip->ecc.postpad) {
1263 chip->read_buf(mtd, oob, chip->ecc.postpad);
1264 oob += chip->ecc.postpad;
1268 /* Calculate remaining oob bytes */
1269 i = mtd->oobsize - (oob - chip->oob_poi);
1271 chip->read_buf(mtd, oob, i);
1273 return max_bitflips;
1277 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1278 * @chip: nand chip structure
1279 * @oob: oob destination address
1280 * @ops: oob ops structure
1281 * @len: size of oob to transfer
1283 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1284 struct mtd_oob_ops *ops, size_t len)
1286 switch (ops->mode) {
1288 case MTD_OPS_PLACE_OOB:
1290 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1293 case MTD_OPS_AUTO_OOB: {
1294 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1295 uint32_t boffs = 0, roffs = ops->ooboffs;
1298 for (; free->length && len; free++, len -= bytes) {
1299 /* Read request not from offset 0? */
1300 if (unlikely(roffs)) {
1301 if (roffs >= free->length) {
1302 roffs -= free->length;
1305 boffs = free->offset + roffs;
1306 bytes = min_t(size_t, len,
1307 (free->length - roffs));
1310 bytes = min_t(size_t, len, free->length);
1311 boffs = free->offset;
1313 memcpy(oob, chip->oob_poi + boffs, bytes);
1325 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1326 * @mtd: MTD device structure
1327 * @retry_mode: the retry mode to use
1329 * Some vendors supply a special command to shift the Vt threshold, to be used
1330 * when there are too many bitflips in a page (i.e., ECC error). After setting
1331 * a new threshold, the host should retry reading the page.
1333 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1335 struct nand_chip *chip = mtd->priv;
1337 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1339 if (retry_mode >= chip->read_retries)
1342 if (!chip->setup_read_retry)
1345 return chip->setup_read_retry(mtd, retry_mode);
1349 * nand_do_read_ops - [INTERN] Read data with ECC
1350 * @mtd: MTD device structure
1351 * @from: offset to read from
1352 * @ops: oob ops structure
1354 * Internal function. Called with chip held.
1356 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1357 struct mtd_oob_ops *ops)
1359 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1360 struct nand_chip *chip = mtd->priv;
1362 uint32_t readlen = ops->len;
1363 uint32_t oobreadlen = ops->ooblen;
1364 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1365 mtd->oobavail : mtd->oobsize;
1367 uint8_t *bufpoi, *oob, *buf;
1369 unsigned int max_bitflips = 0;
1371 bool ecc_fail = false;
1373 chipnr = (int)(from >> chip->chip_shift);
1374 chip->select_chip(mtd, chipnr);
1376 realpage = (int)(from >> chip->page_shift);
1377 page = realpage & chip->pagemask;
1379 col = (int)(from & (mtd->writesize - 1));
1383 oob_required = oob ? 1 : 0;
1386 unsigned int ecc_failures = mtd->ecc_stats.failed;
1389 bytes = min(mtd->writesize - col, readlen);
1390 aligned = (bytes == mtd->writesize);
1397 /* Is the current page in the buffer? */
1398 if (realpage != chip->pagebuf || oob) {
1399 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1401 if (use_bufpoi && aligned)
1402 pr_debug("%s: using read bounce buffer for buf@%p\n",
1406 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1409 * Now read the page into the buffer. Absent an error,
1410 * the read methods return max bitflips per ecc step.
1412 if (unlikely(ops->mode == MTD_OPS_RAW))
1413 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1416 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1418 ret = chip->ecc.read_subpage(mtd, chip,
1422 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1423 oob_required, page);
1426 /* Invalidate page cache */
1431 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1433 /* Transfer not aligned data */
1435 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1436 !(mtd->ecc_stats.failed - ecc_failures) &&
1437 (ops->mode != MTD_OPS_RAW)) {
1438 chip->pagebuf = realpage;
1439 chip->pagebuf_bitflips = ret;
1441 /* Invalidate page cache */
1444 memcpy(buf, chip->buffers->databuf + col, bytes);
1447 if (unlikely(oob)) {
1448 int toread = min(oobreadlen, max_oobsize);
1451 oob = nand_transfer_oob(chip,
1453 oobreadlen -= toread;
1457 if (chip->options & NAND_NEED_READRDY) {
1458 /* Apply delay or wait for ready/busy pin */
1459 if (!chip->dev_ready)
1460 udelay(chip->chip_delay);
1462 nand_wait_ready(mtd);
1465 if (mtd->ecc_stats.failed - ecc_failures) {
1466 if (retry_mode + 1 < chip->read_retries) {
1468 ret = nand_setup_read_retry(mtd,
1473 /* Reset failures; retry */
1474 mtd->ecc_stats.failed = ecc_failures;
1477 /* No more retry modes; real failure */
1484 memcpy(buf, chip->buffers->databuf + col, bytes);
1486 max_bitflips = max_t(unsigned int, max_bitflips,
1487 chip->pagebuf_bitflips);
1492 /* Reset to retry mode 0 */
1494 ret = nand_setup_read_retry(mtd, 0);
1503 /* For subsequent reads align to page boundary */
1505 /* Increment page address */
1508 page = realpage & chip->pagemask;
1509 /* Check, if we cross a chip boundary */
1512 chip->select_chip(mtd, -1);
1513 chip->select_chip(mtd, chipnr);
1516 chip->select_chip(mtd, -1);
1518 ops->retlen = ops->len - (size_t) readlen;
1520 ops->oobretlen = ops->ooblen - oobreadlen;
1528 return max_bitflips;
1532 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1533 * @mtd: MTD device structure
1534 * @from: offset to read from
1535 * @len: number of bytes to read
1536 * @retlen: pointer to variable to store the number of read bytes
1537 * @buf: the databuffer to put data
1539 * Get hold of the chip and call nand_do_read.
1541 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1542 size_t *retlen, uint8_t *buf)
1544 struct mtd_oob_ops ops;
1547 nand_get_device(mtd, FL_READING);
1548 memset(&ops, 0, sizeof(ops));
1551 ops.mode = MTD_OPS_PLACE_OOB;
1552 ret = nand_do_read_ops(mtd, from, &ops);
1553 *retlen = ops.retlen;
1554 nand_release_device(mtd);
1559 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1560 * @mtd: mtd info structure
1561 * @chip: nand chip info structure
1562 * @page: page number to read
1564 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1567 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1568 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1573 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1575 * @mtd: mtd info structure
1576 * @chip: nand chip info structure
1577 * @page: page number to read
1579 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1582 int length = mtd->oobsize;
1583 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1584 int eccsize = chip->ecc.size;
1585 uint8_t *bufpoi = chip->oob_poi;
1586 int i, toread, sndrnd = 0, pos;
1588 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1589 for (i = 0; i < chip->ecc.steps; i++) {
1591 pos = eccsize + i * (eccsize + chunk);
1592 if (mtd->writesize > 512)
1593 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1595 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1598 toread = min_t(int, length, chunk);
1599 chip->read_buf(mtd, bufpoi, toread);
1604 chip->read_buf(mtd, bufpoi, length);
1610 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1611 * @mtd: mtd info structure
1612 * @chip: nand chip info structure
1613 * @page: page number to write
1615 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1619 const uint8_t *buf = chip->oob_poi;
1620 int length = mtd->oobsize;
1622 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1623 chip->write_buf(mtd, buf, length);
1624 /* Send command to program the OOB data */
1625 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1627 status = chip->waitfunc(mtd, chip);
1629 return status & NAND_STATUS_FAIL ? -EIO : 0;
1633 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1634 * with syndrome - only for large page flash
1635 * @mtd: mtd info structure
1636 * @chip: nand chip info structure
1637 * @page: page number to write
1639 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1640 struct nand_chip *chip, int page)
1642 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1643 int eccsize = chip->ecc.size, length = mtd->oobsize;
1644 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1645 const uint8_t *bufpoi = chip->oob_poi;
1648 * data-ecc-data-ecc ... ecc-oob
1650 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1652 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1653 pos = steps * (eccsize + chunk);
1658 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1659 for (i = 0; i < steps; i++) {
1661 if (mtd->writesize <= 512) {
1662 uint32_t fill = 0xFFFFFFFF;
1666 int num = min_t(int, len, 4);
1667 chip->write_buf(mtd, (uint8_t *)&fill,
1672 pos = eccsize + i * (eccsize + chunk);
1673 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1677 len = min_t(int, length, chunk);
1678 chip->write_buf(mtd, bufpoi, len);
1683 chip->write_buf(mtd, bufpoi, length);
1685 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1686 status = chip->waitfunc(mtd, chip);
1688 return status & NAND_STATUS_FAIL ? -EIO : 0;
1692 * nand_do_read_oob - [INTERN] NAND read out-of-band
1693 * @mtd: MTD device structure
1694 * @from: offset to read from
1695 * @ops: oob operations description structure
1697 * NAND read out-of-band data from the spare area.
1699 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1700 struct mtd_oob_ops *ops)
1702 int page, realpage, chipnr;
1703 struct nand_chip *chip = mtd->priv;
1704 struct mtd_ecc_stats stats;
1705 int readlen = ops->ooblen;
1707 uint8_t *buf = ops->oobbuf;
1710 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1711 __func__, (unsigned long long)from, readlen);
1713 stats = mtd->ecc_stats;
1715 if (ops->mode == MTD_OPS_AUTO_OOB)
1716 len = chip->ecc.layout->oobavail;
1720 if (unlikely(ops->ooboffs >= len)) {
1721 pr_debug("%s: attempt to start read outside oob\n",
1726 /* Do not allow reads past end of device */
1727 if (unlikely(from >= mtd->size ||
1728 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1729 (from >> chip->page_shift)) * len)) {
1730 pr_debug("%s: attempt to read beyond end of device\n",
1735 chipnr = (int)(from >> chip->chip_shift);
1736 chip->select_chip(mtd, chipnr);
1738 /* Shift to get page */
1739 realpage = (int)(from >> chip->page_shift);
1740 page = realpage & chip->pagemask;
1745 if (ops->mode == MTD_OPS_RAW)
1746 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1748 ret = chip->ecc.read_oob(mtd, chip, page);
1753 len = min(len, readlen);
1754 buf = nand_transfer_oob(chip, buf, ops, len);
1756 if (chip->options & NAND_NEED_READRDY) {
1757 /* Apply delay or wait for ready/busy pin */
1758 if (!chip->dev_ready)
1759 udelay(chip->chip_delay);
1761 nand_wait_ready(mtd);
1768 /* Increment page address */
1771 page = realpage & chip->pagemask;
1772 /* Check, if we cross a chip boundary */
1775 chip->select_chip(mtd, -1);
1776 chip->select_chip(mtd, chipnr);
1779 chip->select_chip(mtd, -1);
1781 ops->oobretlen = ops->ooblen - readlen;
1786 if (mtd->ecc_stats.failed - stats.failed)
1789 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1793 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1794 * @mtd: MTD device structure
1795 * @from: offset to read from
1796 * @ops: oob operation description structure
1798 * NAND read data and/or out-of-band data.
1800 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1801 struct mtd_oob_ops *ops)
1803 int ret = -ENOTSUPP;
1807 /* Do not allow reads past end of device */
1808 if (ops->datbuf && (from + ops->len) > mtd->size) {
1809 pr_debug("%s: attempt to read beyond end of device\n",
1814 nand_get_device(mtd, FL_READING);
1816 switch (ops->mode) {
1817 case MTD_OPS_PLACE_OOB:
1818 case MTD_OPS_AUTO_OOB:
1827 ret = nand_do_read_oob(mtd, from, ops);
1829 ret = nand_do_read_ops(mtd, from, ops);
1832 nand_release_device(mtd);
1838 * nand_write_page_raw - [INTERN] raw page write function
1839 * @mtd: mtd info structure
1840 * @chip: nand chip info structure
1842 * @oob_required: must write chip->oob_poi to OOB
1844 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1846 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1847 const uint8_t *buf, int oob_required)
1849 chip->write_buf(mtd, buf, mtd->writesize);
1851 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1857 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1858 * @mtd: mtd info structure
1859 * @chip: nand chip info structure
1861 * @oob_required: must write chip->oob_poi to OOB
1863 * We need a special oob layout and handling even when ECC isn't checked.
1865 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1866 struct nand_chip *chip,
1867 const uint8_t *buf, int oob_required)
1869 int eccsize = chip->ecc.size;
1870 int eccbytes = chip->ecc.bytes;
1871 uint8_t *oob = chip->oob_poi;
1874 for (steps = chip->ecc.steps; steps > 0; steps--) {
1875 chip->write_buf(mtd, buf, eccsize);
1878 if (chip->ecc.prepad) {
1879 chip->write_buf(mtd, oob, chip->ecc.prepad);
1880 oob += chip->ecc.prepad;
1883 chip->write_buf(mtd, oob, eccbytes);
1886 if (chip->ecc.postpad) {
1887 chip->write_buf(mtd, oob, chip->ecc.postpad);
1888 oob += chip->ecc.postpad;
1892 size = mtd->oobsize - (oob - chip->oob_poi);
1894 chip->write_buf(mtd, oob, size);
1899 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1900 * @mtd: mtd info structure
1901 * @chip: nand chip info structure
1903 * @oob_required: must write chip->oob_poi to OOB
1905 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1906 const uint8_t *buf, int oob_required)
1908 int i, eccsize = chip->ecc.size;
1909 int eccbytes = chip->ecc.bytes;
1910 int eccsteps = chip->ecc.steps;
1911 uint8_t *ecc_calc = chip->buffers->ecccalc;
1912 const uint8_t *p = buf;
1913 uint32_t *eccpos = chip->ecc.layout->eccpos;
1915 /* Software ECC calculation */
1916 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1917 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1919 for (i = 0; i < chip->ecc.total; i++)
1920 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1922 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1926 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1927 * @mtd: mtd info structure
1928 * @chip: nand chip info structure
1930 * @oob_required: must write chip->oob_poi to OOB
1932 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1933 const uint8_t *buf, int oob_required)
1935 int i, eccsize = chip->ecc.size;
1936 int eccbytes = chip->ecc.bytes;
1937 int eccsteps = chip->ecc.steps;
1938 uint8_t *ecc_calc = chip->buffers->ecccalc;
1939 const uint8_t *p = buf;
1940 uint32_t *eccpos = chip->ecc.layout->eccpos;
1942 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1943 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1944 chip->write_buf(mtd, p, eccsize);
1945 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1948 for (i = 0; i < chip->ecc.total; i++)
1949 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1951 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1958 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
1959 * @mtd: mtd info structure
1960 * @chip: nand chip info structure
1961 * @offset: column address of subpage within the page
1962 * @data_len: data length
1964 * @oob_required: must write chip->oob_poi to OOB
1966 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
1967 struct nand_chip *chip, uint32_t offset,
1968 uint32_t data_len, const uint8_t *buf,
1971 uint8_t *oob_buf = chip->oob_poi;
1972 uint8_t *ecc_calc = chip->buffers->ecccalc;
1973 int ecc_size = chip->ecc.size;
1974 int ecc_bytes = chip->ecc.bytes;
1975 int ecc_steps = chip->ecc.steps;
1976 uint32_t *eccpos = chip->ecc.layout->eccpos;
1977 uint32_t start_step = offset / ecc_size;
1978 uint32_t end_step = (offset + data_len - 1) / ecc_size;
1979 int oob_bytes = mtd->oobsize / ecc_steps;
1982 for (step = 0; step < ecc_steps; step++) {
1983 /* configure controller for WRITE access */
1984 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1986 /* write data (untouched subpages already masked by 0xFF) */
1987 chip->write_buf(mtd, buf, ecc_size);
1989 /* mask ECC of un-touched subpages by padding 0xFF */
1990 if ((step < start_step) || (step > end_step))
1991 memset(ecc_calc, 0xff, ecc_bytes);
1993 chip->ecc.calculate(mtd, buf, ecc_calc);
1995 /* mask OOB of un-touched subpages by padding 0xFF */
1996 /* if oob_required, preserve OOB metadata of written subpage */
1997 if (!oob_required || (step < start_step) || (step > end_step))
1998 memset(oob_buf, 0xff, oob_bytes);
2001 ecc_calc += ecc_bytes;
2002 oob_buf += oob_bytes;
2005 /* copy calculated ECC for whole page to chip->buffer->oob */
2006 /* this include masked-value(0xFF) for unwritten subpages */
2007 ecc_calc = chip->buffers->ecccalc;
2008 for (i = 0; i < chip->ecc.total; i++)
2009 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2011 /* write OOB buffer to NAND device */
2012 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2019 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2020 * @mtd: mtd info structure
2021 * @chip: nand chip info structure
2023 * @oob_required: must write chip->oob_poi to OOB
2025 * The hw generator calculates the error syndrome automatically. Therefore we
2026 * need a special oob layout and handling.
2028 static int nand_write_page_syndrome(struct mtd_info *mtd,
2029 struct nand_chip *chip,
2030 const uint8_t *buf, int oob_required)
2032 int i, eccsize = chip->ecc.size;
2033 int eccbytes = chip->ecc.bytes;
2034 int eccsteps = chip->ecc.steps;
2035 const uint8_t *p = buf;
2036 uint8_t *oob = chip->oob_poi;
2038 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2040 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2041 chip->write_buf(mtd, p, eccsize);
2043 if (chip->ecc.prepad) {
2044 chip->write_buf(mtd, oob, chip->ecc.prepad);
2045 oob += chip->ecc.prepad;
2048 chip->ecc.calculate(mtd, p, oob);
2049 chip->write_buf(mtd, oob, eccbytes);
2052 if (chip->ecc.postpad) {
2053 chip->write_buf(mtd, oob, chip->ecc.postpad);
2054 oob += chip->ecc.postpad;
2058 /* Calculate remaining oob bytes */
2059 i = mtd->oobsize - (oob - chip->oob_poi);
2061 chip->write_buf(mtd, oob, i);
2067 * nand_write_page - [REPLACEABLE] write one page
2068 * @mtd: MTD device structure
2069 * @chip: NAND chip descriptor
2070 * @offset: address offset within the page
2071 * @data_len: length of actual data to be written
2072 * @buf: the data to write
2073 * @oob_required: must write chip->oob_poi to OOB
2074 * @page: page number to write
2075 * @cached: cached programming
2076 * @raw: use _raw version of write_page
2078 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2079 uint32_t offset, int data_len, const uint8_t *buf,
2080 int oob_required, int page, int cached, int raw)
2082 int status, subpage;
2084 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2085 chip->ecc.write_subpage)
2086 subpage = offset || (data_len < mtd->writesize);
2090 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2093 status = chip->ecc.write_page_raw(mtd, chip, buf,
2096 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2099 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2105 * Cached progamming disabled for now. Not sure if it's worth the
2106 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2110 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2112 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2113 status = chip->waitfunc(mtd, chip);
2115 * See if operation failed and additional status checks are
2118 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2119 status = chip->errstat(mtd, chip, FL_WRITING, status,
2122 if (status & NAND_STATUS_FAIL)
2125 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2126 status = chip->waitfunc(mtd, chip);
2133 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2134 * @mtd: MTD device structure
2135 * @oob: oob data buffer
2136 * @len: oob data write length
2137 * @ops: oob ops structure
2139 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2140 struct mtd_oob_ops *ops)
2142 struct nand_chip *chip = mtd->priv;
2145 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2146 * data from a previous OOB read.
2148 memset(chip->oob_poi, 0xff, mtd->oobsize);
2150 switch (ops->mode) {
2152 case MTD_OPS_PLACE_OOB:
2154 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2157 case MTD_OPS_AUTO_OOB: {
2158 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2159 uint32_t boffs = 0, woffs = ops->ooboffs;
2162 for (; free->length && len; free++, len -= bytes) {
2163 /* Write request not from offset 0? */
2164 if (unlikely(woffs)) {
2165 if (woffs >= free->length) {
2166 woffs -= free->length;
2169 boffs = free->offset + woffs;
2170 bytes = min_t(size_t, len,
2171 (free->length - woffs));
2174 bytes = min_t(size_t, len, free->length);
2175 boffs = free->offset;
2177 memcpy(chip->oob_poi + boffs, oob, bytes);
2188 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2191 * nand_do_write_ops - [INTERN] NAND write with ECC
2192 * @mtd: MTD device structure
2193 * @to: offset to write to
2194 * @ops: oob operations description structure
2196 * NAND write with ECC.
2198 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2199 struct mtd_oob_ops *ops)
2201 int chipnr, realpage, page, blockmask, column;
2202 struct nand_chip *chip = mtd->priv;
2203 uint32_t writelen = ops->len;
2205 uint32_t oobwritelen = ops->ooblen;
2206 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2207 mtd->oobavail : mtd->oobsize;
2209 uint8_t *oob = ops->oobbuf;
2210 uint8_t *buf = ops->datbuf;
2212 int oob_required = oob ? 1 : 0;
2218 /* Reject writes, which are not page aligned */
2219 if (NOTALIGNED(to)) {
2220 pr_notice("%s: attempt to write non page aligned data\n",
2225 column = to & (mtd->writesize - 1);
2227 chipnr = (int)(to >> chip->chip_shift);
2228 chip->select_chip(mtd, chipnr);
2230 /* Check, if it is write protected */
2231 if (nand_check_wp(mtd)) {
2236 realpage = (int)(to >> chip->page_shift);
2237 page = realpage & chip->pagemask;
2238 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2240 /* Invalidate the page cache, when we write to the cached page */
2241 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2242 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2245 /* Don't allow multipage oob writes with offset */
2246 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2252 int bytes = mtd->writesize;
2253 int cached = writelen > bytes && page != blockmask;
2254 uint8_t *wbuf = buf;
2256 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2264 /* Partial page write?, or need to use bounce buffer */
2266 pr_debug("%s: using write bounce buffer for buf@%p\n",
2270 bytes = min_t(int, bytes - column, writelen);
2272 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2273 memcpy(&chip->buffers->databuf[column], buf, bytes);
2274 wbuf = chip->buffers->databuf;
2277 if (unlikely(oob)) {
2278 size_t len = min(oobwritelen, oobmaxlen);
2279 oob = nand_fill_oob(mtd, oob, len, ops);
2282 /* We still need to erase leftover OOB data */
2283 memset(chip->oob_poi, 0xff, mtd->oobsize);
2285 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2286 oob_required, page, cached,
2287 (ops->mode == MTD_OPS_RAW));
2299 page = realpage & chip->pagemask;
2300 /* Check, if we cross a chip boundary */
2303 chip->select_chip(mtd, -1);
2304 chip->select_chip(mtd, chipnr);
2308 ops->retlen = ops->len - writelen;
2310 ops->oobretlen = ops->ooblen;
2313 chip->select_chip(mtd, -1);
2318 * panic_nand_write - [MTD Interface] NAND write with ECC
2319 * @mtd: MTD device structure
2320 * @to: offset to write to
2321 * @len: number of bytes to write
2322 * @retlen: pointer to variable to store the number of written bytes
2323 * @buf: the data to write
2325 * NAND write with ECC. Used when performing writes in interrupt context, this
2326 * may for example be called by mtdoops when writing an oops while in panic.
2328 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2329 size_t *retlen, const uint8_t *buf)
2331 struct nand_chip *chip = mtd->priv;
2332 struct mtd_oob_ops ops;
2335 /* Wait for the device to get ready */
2336 panic_nand_wait(mtd, chip, 400);
2338 /* Grab the device */
2339 panic_nand_get_device(chip, mtd, FL_WRITING);
2341 memset(&ops, 0, sizeof(ops));
2343 ops.datbuf = (uint8_t *)buf;
2344 ops.mode = MTD_OPS_PLACE_OOB;
2346 ret = nand_do_write_ops(mtd, to, &ops);
2348 *retlen = ops.retlen;
2353 * nand_write - [MTD Interface] NAND write with ECC
2354 * @mtd: MTD device structure
2355 * @to: offset to write to
2356 * @len: number of bytes to write
2357 * @retlen: pointer to variable to store the number of written bytes
2358 * @buf: the data to write
2360 * NAND write with ECC.
2362 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2363 size_t *retlen, const uint8_t *buf)
2365 struct mtd_oob_ops ops;
2368 nand_get_device(mtd, FL_WRITING);
2369 memset(&ops, 0, sizeof(ops));
2371 ops.datbuf = (uint8_t *)buf;
2372 ops.mode = MTD_OPS_PLACE_OOB;
2373 ret = nand_do_write_ops(mtd, to, &ops);
2374 *retlen = ops.retlen;
2375 nand_release_device(mtd);
2380 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2381 * @mtd: MTD device structure
2382 * @to: offset to write to
2383 * @ops: oob operation description structure
2385 * NAND write out-of-band.
2387 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2388 struct mtd_oob_ops *ops)
2390 int chipnr, page, status, len;
2391 struct nand_chip *chip = mtd->priv;
2393 pr_debug("%s: to = 0x%08x, len = %i\n",
2394 __func__, (unsigned int)to, (int)ops->ooblen);
2396 if (ops->mode == MTD_OPS_AUTO_OOB)
2397 len = chip->ecc.layout->oobavail;
2401 /* Do not allow write past end of page */
2402 if ((ops->ooboffs + ops->ooblen) > len) {
2403 pr_debug("%s: attempt to write past end of page\n",
2408 if (unlikely(ops->ooboffs >= len)) {
2409 pr_debug("%s: attempt to start write outside oob\n",
2414 /* Do not allow write past end of device */
2415 if (unlikely(to >= mtd->size ||
2416 ops->ooboffs + ops->ooblen >
2417 ((mtd->size >> chip->page_shift) -
2418 (to >> chip->page_shift)) * len)) {
2419 pr_debug("%s: attempt to write beyond end of device\n",
2424 chipnr = (int)(to >> chip->chip_shift);
2425 chip->select_chip(mtd, chipnr);
2427 /* Shift to get page */
2428 page = (int)(to >> chip->page_shift);
2431 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2432 * of my DiskOnChip 2000 test units) will clear the whole data page too
2433 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2434 * it in the doc2000 driver in August 1999. dwmw2.
2436 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2438 /* Check, if it is write protected */
2439 if (nand_check_wp(mtd)) {
2440 chip->select_chip(mtd, -1);
2444 /* Invalidate the page cache, if we write to the cached page */
2445 if (page == chip->pagebuf)
2448 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2450 if (ops->mode == MTD_OPS_RAW)
2451 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2453 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2455 chip->select_chip(mtd, -1);
2460 ops->oobretlen = ops->ooblen;
2466 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2467 * @mtd: MTD device structure
2468 * @to: offset to write to
2469 * @ops: oob operation description structure
2471 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2472 struct mtd_oob_ops *ops)
2474 int ret = -ENOTSUPP;
2478 /* Do not allow writes past end of device */
2479 if (ops->datbuf && (to + ops->len) > mtd->size) {
2480 pr_debug("%s: attempt to write beyond end of device\n",
2485 nand_get_device(mtd, FL_WRITING);
2487 switch (ops->mode) {
2488 case MTD_OPS_PLACE_OOB:
2489 case MTD_OPS_AUTO_OOB:
2498 ret = nand_do_write_oob(mtd, to, ops);
2500 ret = nand_do_write_ops(mtd, to, ops);
2503 nand_release_device(mtd);
2508 * single_erase - [GENERIC] NAND standard block erase command function
2509 * @mtd: MTD device structure
2510 * @page: the page address of the block which will be erased
2512 * Standard erase command for NAND chips. Returns NAND status.
2514 static int single_erase(struct mtd_info *mtd, int page)
2516 struct nand_chip *chip = mtd->priv;
2517 /* Send commands to erase a block */
2518 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2519 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2521 return chip->waitfunc(mtd, chip);
2525 * nand_erase - [MTD Interface] erase block(s)
2526 * @mtd: MTD device structure
2527 * @instr: erase instruction
2529 * Erase one ore more blocks.
2531 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2533 return nand_erase_nand(mtd, instr, 0);
2537 * nand_erase_nand - [INTERN] erase block(s)
2538 * @mtd: MTD device structure
2539 * @instr: erase instruction
2540 * @allowbbt: allow erasing the bbt area
2542 * Erase one ore more blocks.
2544 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2547 int page, status, pages_per_block, ret, chipnr;
2548 struct nand_chip *chip = mtd->priv;
2551 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2552 __func__, (unsigned long long)instr->addr,
2553 (unsigned long long)instr->len);
2555 if (check_offs_len(mtd, instr->addr, instr->len))
2558 /* Grab the lock and see if the device is available */
2559 nand_get_device(mtd, FL_ERASING);
2561 /* Shift to get first page */
2562 page = (int)(instr->addr >> chip->page_shift);
2563 chipnr = (int)(instr->addr >> chip->chip_shift);
2565 /* Calculate pages in each block */
2566 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2568 /* Select the NAND device */
2569 chip->select_chip(mtd, chipnr);
2571 /* Check, if it is write protected */
2572 if (nand_check_wp(mtd)) {
2573 pr_debug("%s: device is write protected!\n",
2575 instr->state = MTD_ERASE_FAILED;
2579 /* Loop through the pages */
2582 instr->state = MTD_ERASING;
2587 /* Check if we have a bad block, we do not erase bad blocks! */
2588 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2589 chip->page_shift, 0, allowbbt)) {
2590 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2592 instr->state = MTD_ERASE_FAILED;
2597 * Invalidate the page cache, if we erase the block which
2598 * contains the current cached page.
2600 if (page <= chip->pagebuf && chip->pagebuf <
2601 (page + pages_per_block))
2604 status = chip->erase(mtd, page & chip->pagemask);
2607 * See if operation failed and additional status checks are
2610 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2611 status = chip->errstat(mtd, chip, FL_ERASING,
2614 /* See if block erase succeeded */
2615 if (status & NAND_STATUS_FAIL) {
2616 pr_debug("%s: failed erase, page 0x%08x\n",
2618 instr->state = MTD_ERASE_FAILED;
2620 ((loff_t)page << chip->page_shift);
2624 /* Increment page address and decrement length */
2625 len -= (1ULL << chip->phys_erase_shift);
2626 page += pages_per_block;
2628 /* Check, if we cross a chip boundary */
2629 if (len && !(page & chip->pagemask)) {
2631 chip->select_chip(mtd, -1);
2632 chip->select_chip(mtd, chipnr);
2635 instr->state = MTD_ERASE_DONE;
2639 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2641 /* Deselect and wake up anyone waiting on the device */
2642 chip->select_chip(mtd, -1);
2643 nand_release_device(mtd);
2645 /* Do call back function */
2647 mtd_erase_callback(instr);
2649 /* Return more or less happy */
2654 * nand_sync - [MTD Interface] sync
2655 * @mtd: MTD device structure
2657 * Sync is actually a wait for chip ready function.
2659 static void nand_sync(struct mtd_info *mtd)
2661 pr_debug("%s: called\n", __func__);
2663 /* Grab the lock and see if the device is available */
2664 nand_get_device(mtd, FL_SYNCING);
2665 /* Release it and go back */
2666 nand_release_device(mtd);
2670 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2671 * @mtd: MTD device structure
2672 * @offs: offset relative to mtd start
2674 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2676 return nand_block_checkbad(mtd, offs, 1, 0);
2680 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2681 * @mtd: MTD device structure
2682 * @ofs: offset relative to mtd start
2684 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2688 ret = nand_block_isbad(mtd, ofs);
2690 /* If it was bad already, return success and do nothing */
2696 return nand_block_markbad_lowlevel(mtd, ofs);
2700 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2701 * @mtd: MTD device structure
2702 * @chip: nand chip info structure
2703 * @addr: feature address.
2704 * @subfeature_param: the subfeature parameters, a four bytes array.
2706 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2707 int addr, uint8_t *subfeature_param)
2712 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2713 if (!chip->onfi_version ||
2714 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2715 & ONFI_OPT_CMD_SET_GET_FEATURES))
2719 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2720 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2721 chip->write_byte(mtd, subfeature_param[i]);
2723 status = chip->waitfunc(mtd, chip);
2724 if (status & NAND_STATUS_FAIL)
2730 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2731 * @mtd: MTD device structure
2732 * @chip: nand chip info structure
2733 * @addr: feature address.
2734 * @subfeature_param: the subfeature parameters, a four bytes array.
2736 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2737 int addr, uint8_t *subfeature_param)
2741 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2742 if (!chip->onfi_version ||
2743 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2744 & ONFI_OPT_CMD_SET_GET_FEATURES))
2748 /* clear the sub feature parameters */
2749 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2751 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2752 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2753 *subfeature_param++ = chip->read_byte(mtd);
2757 /* Set default functions */
2758 static void nand_set_defaults(struct nand_chip *chip, int busw)
2760 /* check for proper chip_delay setup, set 20us if not */
2761 if (!chip->chip_delay)
2762 chip->chip_delay = 20;
2764 /* check, if a user supplied command function given */
2765 if (chip->cmdfunc == NULL)
2766 chip->cmdfunc = nand_command;
2768 /* check, if a user supplied wait function given */
2769 if (chip->waitfunc == NULL)
2770 chip->waitfunc = nand_wait;
2772 if (!chip->select_chip)
2773 chip->select_chip = nand_select_chip;
2775 /* set for ONFI nand */
2776 if (!chip->onfi_set_features)
2777 chip->onfi_set_features = nand_onfi_set_features;
2778 if (!chip->onfi_get_features)
2779 chip->onfi_get_features = nand_onfi_get_features;
2781 /* If called twice, pointers that depend on busw may need to be reset */
2782 if (!chip->read_byte || chip->read_byte == nand_read_byte)
2783 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2784 if (!chip->read_word)
2785 chip->read_word = nand_read_word;
2786 if (!chip->block_bad)
2787 chip->block_bad = nand_block_bad;
2788 if (!chip->block_markbad)
2789 chip->block_markbad = nand_default_block_markbad;
2790 if (!chip->write_buf || chip->write_buf == nand_write_buf)
2791 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2792 if (!chip->write_byte || chip->write_byte == nand_write_byte)
2793 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
2794 if (!chip->read_buf || chip->read_buf == nand_read_buf)
2795 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2796 if (!chip->scan_bbt)
2797 chip->scan_bbt = nand_default_bbt;
2799 if (!chip->controller) {
2800 chip->controller = &chip->hwcontrol;
2801 spin_lock_init(&chip->controller->lock);
2802 init_waitqueue_head(&chip->controller->wq);
2807 /* Sanitize ONFI strings so we can safely print them */
2808 static void sanitize_string(char *s, size_t len)
2812 /* Null terminate */
2815 /* Remove non printable chars */
2816 for (i = 0; i < len - 1; i++) {
2817 if (s[i] < ' ' || s[i] > 127)
2821 /* Remove trailing spaces */
2825 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2830 for (i = 0; i < 8; i++)
2831 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2837 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2838 /* Parse the Extended Parameter Page. */
2839 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
2840 struct nand_chip *chip, struct nand_onfi_params *p)
2842 struct onfi_ext_param_page *ep;
2843 struct onfi_ext_section *s;
2844 struct onfi_ext_ecc_info *ecc;
2850 len = le16_to_cpu(p->ext_param_page_length) * 16;
2851 ep = kmalloc(len, GFP_KERNEL);
2855 /* Send our own NAND_CMD_PARAM. */
2856 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2858 /* Use the Change Read Column command to skip the ONFI param pages. */
2859 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
2860 sizeof(*p) * p->num_of_param_pages , -1);
2862 /* Read out the Extended Parameter Page. */
2863 chip->read_buf(mtd, (uint8_t *)ep, len);
2864 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
2865 != le16_to_cpu(ep->crc))) {
2866 pr_debug("fail in the CRC.\n");
2871 * Check the signature.
2872 * Do not strictly follow the ONFI spec, maybe changed in future.
2874 if (strncmp((char *)ep->sig, "EPPS", 4)) {
2875 pr_debug("The signature is invalid.\n");
2879 /* find the ECC section. */
2880 cursor = (uint8_t *)(ep + 1);
2881 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
2882 s = ep->sections + i;
2883 if (s->type == ONFI_SECTION_TYPE_2)
2885 cursor += s->length * 16;
2887 if (i == ONFI_EXT_SECTION_MAX) {
2888 pr_debug("We can not find the ECC section.\n");
2892 /* get the info we want. */
2893 ecc = (struct onfi_ext_ecc_info *)cursor;
2895 if (!ecc->codeword_size) {
2896 pr_debug("Invalid codeword size\n");
2900 chip->ecc_strength_ds = ecc->ecc_bits;
2901 chip->ecc_step_ds = 1 << ecc->codeword_size;
2909 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
2911 struct nand_chip *chip = mtd->priv;
2912 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
2914 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
2919 * Configure chip properties from Micron vendor-specific ONFI table
2921 static void nand_onfi_detect_micron(struct nand_chip *chip,
2922 struct nand_onfi_params *p)
2924 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
2926 if (le16_to_cpu(p->vendor_revision) < 1)
2929 chip->read_retries = micron->read_retry_options;
2930 chip->setup_read_retry = nand_setup_read_retry_micron;
2934 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2936 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2939 struct nand_onfi_params *p = &chip->onfi_params;
2943 /* Try ONFI for unknown chip or LP */
2944 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2945 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2946 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2949 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2950 for (i = 0; i < 3; i++) {
2951 for (j = 0; j < sizeof(*p); j++)
2952 ((uint8_t *)p)[j] = chip->read_byte(mtd);
2953 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2954 le16_to_cpu(p->crc)) {
2960 pr_err("Could not find valid ONFI parameter page; aborting\n");
2965 val = le16_to_cpu(p->revision);
2967 chip->onfi_version = 23;
2968 else if (val & (1 << 4))
2969 chip->onfi_version = 22;
2970 else if (val & (1 << 3))
2971 chip->onfi_version = 21;
2972 else if (val & (1 << 2))
2973 chip->onfi_version = 20;
2974 else if (val & (1 << 1))
2975 chip->onfi_version = 10;
2977 if (!chip->onfi_version) {
2978 pr_info("unsupported ONFI version: %d\n", val);
2982 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2983 sanitize_string(p->model, sizeof(p->model));
2985 mtd->name = p->model;
2987 mtd->writesize = le32_to_cpu(p->byte_per_page);
2990 * pages_per_block and blocks_per_lun may not be a power-of-2 size
2991 * (don't ask me who thought of this...). MTD assumes that these
2992 * dimensions will be power-of-2, so just truncate the remaining area.
2994 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
2995 mtd->erasesize *= mtd->writesize;
2997 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2999 /* See erasesize comment */
3000 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3001 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3002 chip->bits_per_cell = p->bits_per_cell;
3004 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3005 *busw = NAND_BUSWIDTH_16;
3009 if (p->ecc_bits != 0xff) {
3010 chip->ecc_strength_ds = p->ecc_bits;
3011 chip->ecc_step_ds = 512;
3012 } else if (chip->onfi_version >= 21 &&
3013 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3016 * The nand_flash_detect_ext_param_page() uses the
3017 * Change Read Column command which maybe not supported
3018 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3019 * now. We do not replace user supplied command function.
3021 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3022 chip->cmdfunc = nand_command_lp;
3024 /* The Extended Parameter Page is supported since ONFI 2.1. */
3025 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3026 pr_warn("Failed to detect ONFI extended param page\n");
3028 pr_warn("Could not retrieve ONFI ECC requirements\n");
3031 if (p->jedec_id == NAND_MFR_MICRON)
3032 nand_onfi_detect_micron(chip, p);
3037 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3045 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3047 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3050 struct nand_jedec_params *p = &chip->jedec_params;
3051 struct jedec_ecc_info *ecc;
3055 /* Try JEDEC for unknown chip or LP */
3056 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3057 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3058 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3059 chip->read_byte(mtd) != 'C')
3062 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3063 for (i = 0; i < 3; i++) {
3064 for (j = 0; j < sizeof(*p); j++)
3065 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3067 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3068 le16_to_cpu(p->crc))
3073 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3078 val = le16_to_cpu(p->revision);
3080 chip->jedec_version = 10;
3081 else if (val & (1 << 1))
3082 chip->jedec_version = 1; /* vendor specific version */
3084 if (!chip->jedec_version) {
3085 pr_info("unsupported JEDEC version: %d\n", val);
3089 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3090 sanitize_string(p->model, sizeof(p->model));
3092 mtd->name = p->model;
3094 mtd->writesize = le32_to_cpu(p->byte_per_page);
3096 /* Please reference to the comment for nand_flash_detect_onfi. */
3097 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3098 mtd->erasesize *= mtd->writesize;
3100 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3102 /* Please reference to the comment for nand_flash_detect_onfi. */
3103 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3104 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3105 chip->bits_per_cell = p->bits_per_cell;
3107 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3108 *busw = NAND_BUSWIDTH_16;
3113 ecc = &p->ecc_info[0];
3115 if (ecc->codeword_size >= 9) {
3116 chip->ecc_strength_ds = ecc->ecc_bits;
3117 chip->ecc_step_ds = 1 << ecc->codeword_size;
3119 pr_warn("Invalid codeword size\n");
3126 * nand_id_has_period - Check if an ID string has a given wraparound period
3127 * @id_data: the ID string
3128 * @arrlen: the length of the @id_data array
3129 * @period: the period of repitition
3131 * Check if an ID string is repeated within a given sequence of bytes at
3132 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3133 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3134 * if the repetition has a period of @period; otherwise, returns zero.
3136 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3139 for (i = 0; i < period; i++)
3140 for (j = i + period; j < arrlen; j += period)
3141 if (id_data[i] != id_data[j])
3147 * nand_id_len - Get the length of an ID string returned by CMD_READID
3148 * @id_data: the ID string
3149 * @arrlen: the length of the @id_data array
3151 * Returns the length of the ID string, according to known wraparound/trailing
3152 * zero patterns. If no pattern exists, returns the length of the array.
3154 static int nand_id_len(u8 *id_data, int arrlen)
3156 int last_nonzero, period;
3158 /* Find last non-zero byte */
3159 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3160 if (id_data[last_nonzero])
3164 if (last_nonzero < 0)
3167 /* Calculate wraparound period */
3168 for (period = 1; period < arrlen; period++)
3169 if (nand_id_has_period(id_data, arrlen, period))
3172 /* There's a repeated pattern */
3173 if (period < arrlen)
3176 /* There are trailing zeros */
3177 if (last_nonzero < arrlen - 1)
3178 return last_nonzero + 1;
3180 /* No pattern detected */
3184 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3185 static int nand_get_bits_per_cell(u8 cellinfo)
3189 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3190 bits >>= NAND_CI_CELLTYPE_SHIFT;
3195 * Many new NAND share similar device ID codes, which represent the size of the
3196 * chip. The rest of the parameters must be decoded according to generic or
3197 * manufacturer-specific "extended ID" decoding patterns.
3199 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3200 u8 id_data[8], int *busw)
3203 /* The 3rd id byte holds MLC / multichip data */
3204 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3205 /* The 4th id byte is the important one */
3208 id_len = nand_id_len(id_data, 8);
3211 * Field definitions are in the following datasheets:
3212 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3213 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3214 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3216 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3217 * ID to decide what to do.
3219 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3220 !nand_is_slc(chip) && id_data[5] != 0x00) {
3222 mtd->writesize = 2048 << (extid & 0x03);
3225 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3245 default: /* Other cases are "reserved" (unknown) */
3246 mtd->oobsize = 1024;
3250 /* Calc blocksize */
3251 mtd->erasesize = (128 * 1024) <<
3252 (((extid >> 1) & 0x04) | (extid & 0x03));
3254 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3255 !nand_is_slc(chip)) {
3259 mtd->writesize = 2048 << (extid & 0x03);
3262 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3286 /* Calc blocksize */
3287 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3289 mtd->erasesize = (128 * 1024) << tmp;
3290 else if (tmp == 0x03)
3291 mtd->erasesize = 768 * 1024;
3293 mtd->erasesize = (64 * 1024) << tmp;
3297 mtd->writesize = 1024 << (extid & 0x03);
3300 mtd->oobsize = (8 << (extid & 0x01)) *
3301 (mtd->writesize >> 9);
3303 /* Calc blocksize. Blocksize is multiples of 64KiB */
3304 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3306 /* Get buswidth information */
3307 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3310 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3311 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3313 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3315 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3317 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3318 nand_is_slc(chip) &&
3319 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3320 !(id_data[4] & 0x80) /* !BENAND */) {
3321 mtd->oobsize = 32 * mtd->writesize >> 9;
3328 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3329 * decodes a matching ID table entry and assigns the MTD size parameters for
3332 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3333 struct nand_flash_dev *type, u8 id_data[8],
3336 int maf_id = id_data[0];
3338 mtd->erasesize = type->erasesize;
3339 mtd->writesize = type->pagesize;
3340 mtd->oobsize = mtd->writesize / 32;
3341 *busw = type->options & NAND_BUSWIDTH_16;
3343 /* All legacy ID NAND are small-page, SLC */
3344 chip->bits_per_cell = 1;
3347 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3348 * some Spansion chips have erasesize that conflicts with size
3349 * listed in nand_ids table.
3350 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3352 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3353 && id_data[6] == 0x00 && id_data[7] == 0x00
3354 && mtd->writesize == 512) {
3355 mtd->erasesize = 128 * 1024;
3356 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3361 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3362 * heuristic patterns using various detected parameters (e.g., manufacturer,
3363 * page size, cell-type information).
3365 static void nand_decode_bbm_options(struct mtd_info *mtd,
3366 struct nand_chip *chip, u8 id_data[8])
3368 int maf_id = id_data[0];
3370 /* Set the bad block position */
3371 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3372 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3374 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3377 * Bad block marker is stored in the last page of each block on Samsung
3378 * and Hynix MLC devices; stored in first two pages of each block on
3379 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3380 * AMD/Spansion, and Macronix. All others scan only the first page.
3382 if (!nand_is_slc(chip) &&
3383 (maf_id == NAND_MFR_SAMSUNG ||
3384 maf_id == NAND_MFR_HYNIX))
3385 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3386 else if ((nand_is_slc(chip) &&
3387 (maf_id == NAND_MFR_SAMSUNG ||
3388 maf_id == NAND_MFR_HYNIX ||
3389 maf_id == NAND_MFR_TOSHIBA ||
3390 maf_id == NAND_MFR_AMD ||
3391 maf_id == NAND_MFR_MACRONIX)) ||
3392 (mtd->writesize == 2048 &&
3393 maf_id == NAND_MFR_MICRON))
3394 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3397 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3399 return type->id_len;
3402 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3403 struct nand_flash_dev *type, u8 *id_data, int *busw)
3405 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3406 mtd->writesize = type->pagesize;
3407 mtd->erasesize = type->erasesize;
3408 mtd->oobsize = type->oobsize;
3410 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3411 chip->chipsize = (uint64_t)type->chipsize << 20;
3412 chip->options |= type->options;
3413 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3414 chip->ecc_step_ds = NAND_ECC_STEP(type);
3415 chip->onfi_timing_mode_default =
3416 type->onfi_timing_mode_default;
3418 *busw = type->options & NAND_BUSWIDTH_16;
3421 mtd->name = type->name;
3429 * Get the flash and manufacturer id and lookup if the type is supported.
3431 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3432 struct nand_chip *chip,
3433 int *maf_id, int *dev_id,
3434 struct nand_flash_dev *type)
3440 /* Select the device */
3441 chip->select_chip(mtd, 0);
3444 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3447 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3449 /* Send the command for reading device ID */
3450 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3452 /* Read manufacturer and device IDs */
3453 *maf_id = chip->read_byte(mtd);
3454 *dev_id = chip->read_byte(mtd);
3457 * Try again to make sure, as some systems the bus-hold or other
3458 * interface concerns can cause random data which looks like a
3459 * possibly credible NAND flash to appear. If the two results do
3460 * not match, ignore the device completely.
3463 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3465 /* Read entire ID string */
3466 for (i = 0; i < 8; i++)
3467 id_data[i] = chip->read_byte(mtd);
3469 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3470 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3471 *maf_id, *dev_id, id_data[0], id_data[1]);
3472 return ERR_PTR(-ENODEV);
3476 type = nand_flash_ids;
3478 for (; type->name != NULL; type++) {
3479 if (is_full_id_nand(type)) {
3480 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3482 } else if (*dev_id == type->dev_id) {
3487 chip->onfi_version = 0;
3488 if (!type->name || !type->pagesize) {
3489 /* Check if the chip is ONFI compliant */
3490 if (nand_flash_detect_onfi(mtd, chip, &busw))
3493 /* Check if the chip is JEDEC compliant */
3494 if (nand_flash_detect_jedec(mtd, chip, &busw))
3499 return ERR_PTR(-ENODEV);
3502 mtd->name = type->name;
3504 chip->chipsize = (uint64_t)type->chipsize << 20;
3506 if (!type->pagesize && chip->init_size) {
3507 /* Set the pagesize, oobsize, erasesize by the driver */
3508 busw = chip->init_size(mtd, chip, id_data);
3509 } else if (!type->pagesize) {
3510 /* Decode parameters from extended ID */
3511 nand_decode_ext_id(mtd, chip, id_data, &busw);
3513 nand_decode_id(mtd, chip, type, id_data, &busw);
3515 /* Get chip options */
3516 chip->options |= type->options;
3519 * Check if chip is not a Samsung device. Do not clear the
3520 * options for chips which do not have an extended id.
3522 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3523 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3526 /* Try to identify manufacturer */
3527 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3528 if (nand_manuf_ids[maf_idx].id == *maf_id)
3532 if (chip->options & NAND_BUSWIDTH_AUTO) {
3533 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3534 chip->options |= busw;
3535 nand_set_defaults(chip, busw);
3536 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3538 * Check, if buswidth is correct. Hardware drivers should set
3541 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3543 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3544 pr_warn("bus width %d instead %d bit\n",
3545 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3547 return ERR_PTR(-EINVAL);
3550 nand_decode_bbm_options(mtd, chip, id_data);
3552 /* Calculate the address shift from the page size */
3553 chip->page_shift = ffs(mtd->writesize) - 1;
3554 /* Convert chipsize to number of pages per chip -1 */
3555 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3557 chip->bbt_erase_shift = chip->phys_erase_shift =
3558 ffs(mtd->erasesize) - 1;
3559 if (chip->chipsize & 0xffffffff)
3560 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3562 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3563 chip->chip_shift += 32 - 1;
3566 chip->badblockbits = 8;
3567 chip->erase = single_erase;
3569 /* Do not replace user supplied command function! */
3570 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3571 chip->cmdfunc = nand_command_lp;
3573 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3576 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3577 if (chip->onfi_version)
3578 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3579 chip->onfi_params.model);
3580 else if (chip->jedec_version)
3581 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3582 chip->jedec_params.model);
3584 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3587 if (chip->jedec_version)
3588 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3589 chip->jedec_params.model);
3591 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3594 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3598 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3599 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3600 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
3605 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3606 * @mtd: MTD device structure
3607 * @maxchips: number of chips to scan for
3608 * @table: alternative NAND ID table
3610 * This is the first phase of the normal nand_scan() function. It reads the
3611 * flash ID and sets up MTD fields accordingly.
3613 * The mtd->owner field must be set to the module of the caller.
3615 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3616 struct nand_flash_dev *table)
3618 int i, nand_maf_id, nand_dev_id;
3619 struct nand_chip *chip = mtd->priv;
3620 struct nand_flash_dev *type;
3622 /* Set the default functions */
3623 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3625 /* Read the flash type */
3626 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3627 &nand_dev_id, table);
3630 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3631 pr_warn("No NAND device found\n");
3632 chip->select_chip(mtd, -1);
3633 return PTR_ERR(type);
3636 chip->select_chip(mtd, -1);
3638 /* Check for a chip array */
3639 for (i = 1; i < maxchips; i++) {
3640 chip->select_chip(mtd, i);
3641 /* See comment in nand_get_flash_type for reset */
3642 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3643 /* Send the command for reading device ID */
3644 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3645 /* Read manufacturer and device IDs */
3646 if (nand_maf_id != chip->read_byte(mtd) ||
3647 nand_dev_id != chip->read_byte(mtd)) {
3648 chip->select_chip(mtd, -1);
3651 chip->select_chip(mtd, -1);
3656 pr_info("%d chips detected\n", i);
3659 /* Store the number of chips and calc total size for mtd */
3661 mtd->size = i * chip->chipsize;
3665 EXPORT_SYMBOL(nand_scan_ident);
3668 * Check if the chip configuration meet the datasheet requirements.
3670 * If our configuration corrects A bits per B bytes and the minimum
3671 * required correction level is X bits per Y bytes, then we must ensure
3672 * both of the following are true:
3674 * (1) A / B >= X / Y
3677 * Requirement (1) ensures we can correct for the required bitflip density.
3678 * Requirement (2) ensures we can correct even when all bitflips are clumped
3679 * in the same sector.
3681 static bool nand_ecc_strength_good(struct mtd_info *mtd)
3683 struct nand_chip *chip = mtd->priv;
3684 struct nand_ecc_ctrl *ecc = &chip->ecc;
3687 if (ecc->size == 0 || chip->ecc_step_ds == 0)
3688 /* Not enough information */
3692 * We get the number of corrected bits per page to compare
3693 * the correction density.
3695 corr = (mtd->writesize * ecc->strength) / ecc->size;
3696 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
3698 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
3702 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3703 * @mtd: MTD device structure
3705 * This is the second phase of the normal nand_scan() function. It fills out
3706 * all the uninitialized function pointers with the defaults and scans for a
3707 * bad block table if appropriate.
3709 int nand_scan_tail(struct mtd_info *mtd)
3712 struct nand_chip *chip = mtd->priv;
3713 struct nand_ecc_ctrl *ecc = &chip->ecc;
3714 struct nand_buffers *nbuf;
3716 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3717 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3718 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3720 if (!(chip->options & NAND_OWN_BUFFERS)) {
3721 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
3722 chip->buffers = nbuf;
3728 /* Set the internal oob buffer location, just after the page data */
3729 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3732 * If no default placement scheme is given, select an appropriate one.
3734 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
3735 switch (mtd->oobsize) {
3737 ecc->layout = &nand_oob_8;
3740 ecc->layout = &nand_oob_16;
3743 ecc->layout = &nand_oob_64;
3746 ecc->layout = &nand_oob_128;
3749 pr_warn("No oob scheme defined for oobsize %d\n",
3755 if (!chip->write_page)
3756 chip->write_page = nand_write_page;
3759 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3760 * selected and we have 256 byte pagesize fallback to software ECC
3763 switch (ecc->mode) {
3764 case NAND_ECC_HW_OOB_FIRST:
3765 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3766 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
3767 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
3770 if (!ecc->read_page)
3771 ecc->read_page = nand_read_page_hwecc_oob_first;
3774 /* Use standard hwecc read page function? */
3775 if (!ecc->read_page)
3776 ecc->read_page = nand_read_page_hwecc;
3777 if (!ecc->write_page)
3778 ecc->write_page = nand_write_page_hwecc;
3779 if (!ecc->read_page_raw)
3780 ecc->read_page_raw = nand_read_page_raw;
3781 if (!ecc->write_page_raw)
3782 ecc->write_page_raw = nand_write_page_raw;
3784 ecc->read_oob = nand_read_oob_std;
3785 if (!ecc->write_oob)
3786 ecc->write_oob = nand_write_oob_std;
3787 if (!ecc->read_subpage)
3788 ecc->read_subpage = nand_read_subpage;
3789 if (!ecc->write_subpage)
3790 ecc->write_subpage = nand_write_subpage_hwecc;
3792 case NAND_ECC_HW_SYNDROME:
3793 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
3795 ecc->read_page == nand_read_page_hwecc ||
3797 ecc->write_page == nand_write_page_hwecc)) {
3798 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
3801 /* Use standard syndrome read/write page function? */
3802 if (!ecc->read_page)
3803 ecc->read_page = nand_read_page_syndrome;
3804 if (!ecc->write_page)
3805 ecc->write_page = nand_write_page_syndrome;
3806 if (!ecc->read_page_raw)
3807 ecc->read_page_raw = nand_read_page_raw_syndrome;
3808 if (!ecc->write_page_raw)
3809 ecc->write_page_raw = nand_write_page_raw_syndrome;
3811 ecc->read_oob = nand_read_oob_syndrome;
3812 if (!ecc->write_oob)
3813 ecc->write_oob = nand_write_oob_syndrome;
3815 if (mtd->writesize >= ecc->size) {
3816 if (!ecc->strength) {
3817 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3822 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
3823 ecc->size, mtd->writesize);
3824 ecc->mode = NAND_ECC_SOFT;
3827 ecc->calculate = nand_calculate_ecc;
3828 ecc->correct = nand_correct_data;
3829 ecc->read_page = nand_read_page_swecc;
3830 ecc->read_subpage = nand_read_subpage;
3831 ecc->write_page = nand_write_page_swecc;
3832 ecc->read_page_raw = nand_read_page_raw;
3833 ecc->write_page_raw = nand_write_page_raw;
3834 ecc->read_oob = nand_read_oob_std;
3835 ecc->write_oob = nand_write_oob_std;
3842 case NAND_ECC_SOFT_BCH:
3843 if (!mtd_nand_has_bch()) {
3844 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
3847 ecc->calculate = nand_bch_calculate_ecc;
3848 ecc->correct = nand_bch_correct_data;
3849 ecc->read_page = nand_read_page_swecc;
3850 ecc->read_subpage = nand_read_subpage;
3851 ecc->write_page = nand_write_page_swecc;
3852 ecc->read_page_raw = nand_read_page_raw;
3853 ecc->write_page_raw = nand_write_page_raw;
3854 ecc->read_oob = nand_read_oob_std;
3855 ecc->write_oob = nand_write_oob_std;
3857 * Board driver should supply ecc.size and ecc.strength values
3858 * to select how many bits are correctable. Otherwise, default
3859 * to 4 bits for large page devices.
3861 if (!ecc->size && (mtd->oobsize >= 64)) {
3866 /* See nand_bch_init() for details. */
3867 ecc->bytes = DIV_ROUND_UP(
3868 ecc->strength * fls(8 * ecc->size), 8);
3869 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
3872 pr_warn("BCH ECC initialization failed!\n");
3878 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
3879 ecc->read_page = nand_read_page_raw;
3880 ecc->write_page = nand_write_page_raw;
3881 ecc->read_oob = nand_read_oob_std;
3882 ecc->read_page_raw = nand_read_page_raw;
3883 ecc->write_page_raw = nand_write_page_raw;
3884 ecc->write_oob = nand_write_oob_std;
3885 ecc->size = mtd->writesize;
3891 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
3895 /* For many systems, the standard OOB write also works for raw */
3896 if (!ecc->read_oob_raw)
3897 ecc->read_oob_raw = ecc->read_oob;
3898 if (!ecc->write_oob_raw)
3899 ecc->write_oob_raw = ecc->write_oob;
3902 * The number of bytes available for a client to place data into
3903 * the out of band area.
3905 ecc->layout->oobavail = 0;
3906 for (i = 0; ecc->layout->oobfree[i].length
3907 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
3908 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
3909 mtd->oobavail = ecc->layout->oobavail;
3911 /* ECC sanity check: warn if it's too weak */
3912 if (!nand_ecc_strength_good(mtd))
3913 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
3917 * Set the number of read / write steps for one page depending on ECC
3920 ecc->steps = mtd->writesize / ecc->size;
3921 if (ecc->steps * ecc->size != mtd->writesize) {
3922 pr_warn("Invalid ECC parameters\n");
3925 ecc->total = ecc->steps * ecc->bytes;
3927 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3928 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
3929 switch (ecc->steps) {
3931 mtd->subpage_sft = 1;
3936 mtd->subpage_sft = 2;
3940 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3942 /* Initialize state */
3943 chip->state = FL_READY;
3945 /* Invalidate the pagebuffer reference */
3948 /* Large page NAND with SOFT_ECC should support subpage reads */
3949 switch (ecc->mode) {
3951 case NAND_ECC_SOFT_BCH:
3952 if (chip->page_shift > 9)
3953 chip->options |= NAND_SUBPAGE_READ;
3960 /* Fill in remaining MTD driver data */
3961 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
3962 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3964 mtd->_erase = nand_erase;
3965 mtd->_read = nand_read;
3966 mtd->_write = nand_write;
3967 mtd->_panic_write = panic_nand_write;
3968 mtd->_read_oob = nand_read_oob;
3969 mtd->_write_oob = nand_write_oob;
3970 mtd->_sync = nand_sync;
3972 mtd->_unlock = NULL;
3973 mtd->_block_isreserved = nand_block_isreserved;
3974 mtd->_block_isbad = nand_block_isbad;
3975 mtd->_block_markbad = nand_block_markbad;
3976 mtd->writebufsize = mtd->writesize;
3978 /* propagate ecc info to mtd_info */
3979 mtd->ecclayout = ecc->layout;
3980 mtd->ecc_strength = ecc->strength;
3981 mtd->ecc_step_size = ecc->size;
3983 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3984 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3987 if (!mtd->bitflip_threshold)
3988 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
3992 EXPORT_SYMBOL(nand_scan_tail);
3995 * is_module_text_address() isn't exported, and it's mostly a pointless
3996 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3997 * to call us from in-kernel code if the core NAND support is modular.
4000 #define caller_is_module() (1)
4002 #define caller_is_module() \
4003 is_module_text_address((unsigned long)__builtin_return_address(0))
4007 * nand_scan - [NAND Interface] Scan for the NAND device
4008 * @mtd: MTD device structure
4009 * @maxchips: number of chips to scan for
4011 * This fills out all the uninitialized function pointers with the defaults.
4012 * The flash ID is read and the mtd/chip structures are filled with the
4013 * appropriate values. The mtd->owner field must be set to the module of the
4016 int nand_scan(struct mtd_info *mtd, int maxchips)
4020 /* Many callers got this wrong, so check for it for a while... */
4021 if (!mtd->owner && caller_is_module()) {
4022 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4026 ret = nand_scan_ident(mtd, maxchips, NULL);
4028 ret = nand_scan_tail(mtd);
4031 EXPORT_SYMBOL(nand_scan);
4033 module_init(nand_base_init);
4034 module_exit(nand_base_exit);
4036 MODULE_LICENSE("GPL");
4037 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4038 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4039 MODULE_DESCRIPTION("Generic NAND flash driver code");