5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
37 #define ENOTSUPP 524 /* Operation is not supported */
41 #include <linux/err.h>
42 #include <linux/mtd/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
47 #ifdef CONFIG_MTD_PARTITIONS
48 #include <linux/mtd/partitions.h>
52 #include <asm/errno.h>
55 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
56 * a flash. NAND flash is initialized prior to interrupts so standard timers
57 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
58 * which is greater than (max NAND reset time / NAND status read time).
59 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
61 #ifndef CONFIG_SYS_NAND_RESET_CNT
62 #define CONFIG_SYS_NAND_RESET_CNT 200000
65 /* Define default oob placement schemes for large and small page devices */
66 static struct nand_ecclayout nand_oob_8 = {
76 static struct nand_ecclayout nand_oob_16 = {
78 .eccpos = {0, 1, 2, 3, 6, 7},
84 static struct nand_ecclayout nand_oob_64 = {
87 40, 41, 42, 43, 44, 45, 46, 47,
88 48, 49, 50, 51, 52, 53, 54, 55,
89 56, 57, 58, 59, 60, 61, 62, 63},
95 static struct nand_ecclayout nand_oob_128 = {
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100, 101, 102, 103,
101 104, 105, 106, 107, 108, 109, 110, 111,
102 112, 113, 114, 115, 116, 117, 118, 119,
103 120, 121, 122, 123, 124, 125, 126, 127},
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
119 * nand_release_device - [GENERIC] release chip
120 * @mtd: MTD device structure
122 * Deselect, release chip lock and wake up anyone waiting on the device
124 static void nand_release_device (struct mtd_info *mtd)
126 struct nand_chip *this = mtd->priv;
127 this->select_chip(mtd, -1); /* De-select the NAND device */
131 * nand_read_byte - [DEFAULT] read one byte from the chip
132 * @mtd: MTD device structure
134 * Default read function for 8bit buswith
136 static uint8_t nand_read_byte(struct mtd_info *mtd)
138 struct nand_chip *chip = mtd->priv;
139 return readb(chip->IO_ADDR_R);
143 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
144 * @mtd: MTD device structure
146 * Default read function for 16bit buswith with
147 * endianess conversion
149 static uint8_t nand_read_byte16(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
152 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
156 * nand_read_word - [DEFAULT] read one word from the chip
157 * @mtd: MTD device structure
159 * Default read function for 16bit buswith without
160 * endianess conversion
162 static u16 nand_read_word(struct mtd_info *mtd)
164 struct nand_chip *chip = mtd->priv;
165 return readw(chip->IO_ADDR_R);
169 * nand_select_chip - [DEFAULT] control CE line
170 * @mtd: MTD device structure
171 * @chipnr: chipnumber to select, -1 for deselect
173 * Default select function for 1 chip devices.
175 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
177 struct nand_chip *chip = mtd->priv;
181 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
192 * nand_write_buf - [DEFAULT] write buffer to chip
193 * @mtd: MTD device structure
195 * @len: number of bytes to write
197 * Default write function for 8bit buswith
199 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
202 struct nand_chip *chip = mtd->priv;
204 for (i = 0; i < len; i++)
205 writeb(buf[i], chip->IO_ADDR_W);
209 * nand_read_buf - [DEFAULT] read chip data into buffer
210 * @mtd: MTD device structure
211 * @buf: buffer to store date
212 * @len: number of bytes to read
214 * Default read function for 8bit buswith
216 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
219 struct nand_chip *chip = mtd->priv;
221 for (i = 0; i < len; i++)
222 buf[i] = readb(chip->IO_ADDR_R);
226 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
227 * @mtd: MTD device structure
228 * @buf: buffer containing the data to compare
229 * @len: number of bytes to compare
231 * Default verify function for 8bit buswith
233 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
236 struct nand_chip *chip = mtd->priv;
238 for (i = 0; i < len; i++)
239 if (buf[i] != readb(chip->IO_ADDR_R))
245 * nand_write_buf16 - [DEFAULT] write buffer to chip
246 * @mtd: MTD device structure
248 * @len: number of bytes to write
250 * Default write function for 16bit buswith
252 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
255 struct nand_chip *chip = mtd->priv;
256 u16 *p = (u16 *) buf;
259 for (i = 0; i < len; i++)
260 writew(p[i], chip->IO_ADDR_W);
265 * nand_read_buf16 - [DEFAULT] read chip data into buffer
266 * @mtd: MTD device structure
267 * @buf: buffer to store date
268 * @len: number of bytes to read
270 * Default read function for 16bit buswith
272 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
275 struct nand_chip *chip = mtd->priv;
276 u16 *p = (u16 *) buf;
279 for (i = 0; i < len; i++)
280 p[i] = readw(chip->IO_ADDR_R);
284 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
285 * @mtd: MTD device structure
286 * @buf: buffer containing the data to compare
287 * @len: number of bytes to compare
289 * Default verify function for 16bit buswith
291 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
294 struct nand_chip *chip = mtd->priv;
295 u16 *p = (u16 *) buf;
298 for (i = 0; i < len; i++)
299 if (p[i] != readw(chip->IO_ADDR_R))
306 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
307 * @mtd: MTD device structure
308 * @ofs: offset from device start
309 * @getchip: 0, if the chip is already selected
311 * Check, if the block is bad.
313 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
315 int page, chipnr, res = 0;
316 struct nand_chip *chip = mtd->priv;
319 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
322 chipnr = (int)(ofs >> chip->chip_shift);
324 nand_get_device(chip, mtd, FL_READING);
326 /* Select the NAND device */
327 chip->select_chip(mtd, chipnr);
330 if (chip->options & NAND_BUSWIDTH_16) {
331 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
333 bad = cpu_to_le16(chip->read_word(mtd));
334 if (chip->badblockpos & 0x1)
336 if ((bad & 0xFF) != 0xff)
339 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
340 if (chip->read_byte(mtd) != 0xff)
345 nand_release_device(mtd);
351 * nand_default_block_markbad - [DEFAULT] mark a block bad
352 * @mtd: MTD device structure
353 * @ofs: offset from device start
355 * This is the default implementation, which can be overridden by
356 * a hardware specific driver.
358 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
360 struct nand_chip *chip = mtd->priv;
361 uint8_t buf[2] = { 0, 0 };
364 /* Get block number */
365 block = (int)(ofs >> chip->bbt_erase_shift);
367 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
369 /* Do we have a flash based bad block table ? */
370 if (chip->options & NAND_USE_FLASH_BBT)
371 ret = nand_update_bbt(mtd, ofs);
373 /* We write two bytes, so we dont have to mess with 16 bit
376 nand_get_device(chip, mtd, FL_WRITING);
378 chip->ops.len = chip->ops.ooblen = 2;
379 chip->ops.datbuf = NULL;
380 chip->ops.oobbuf = buf;
381 chip->ops.ooboffs = chip->badblockpos & ~0x01;
383 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
384 nand_release_device(mtd);
387 mtd->ecc_stats.badblocks++;
393 * nand_check_wp - [GENERIC] check if the chip is write protected
394 * @mtd: MTD device structure
395 * Check, if the device is write protected
397 * The function expects, that the device is already selected
399 static int nand_check_wp(struct mtd_info *mtd)
401 struct nand_chip *chip = mtd->priv;
402 /* Check the WP bit */
403 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
404 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
408 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
409 * @mtd: MTD device structure
410 * @ofs: offset from device start
411 * @getchip: 0, if the chip is already selected
412 * @allowbbt: 1, if its allowed to access the bbt area
414 * Check, if the block is bad. Either by reading the bad block table or
415 * calling of the scan function.
417 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
420 struct nand_chip *chip = mtd->priv;
422 if (!(chip->options & NAND_BBT_SCANNED)) {
423 chip->options |= NAND_BBT_SCANNED;
428 return chip->block_bad(mtd, ofs, getchip);
430 /* Return info from the table */
431 return nand_isbad_bbt(mtd, ofs, allowbbt);
435 * Wait for the ready pin, after a command
436 * The timeout is catched later.
438 void nand_wait_ready(struct mtd_info *mtd)
440 struct nand_chip *chip = mtd->priv;
441 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
444 time_start = get_timer(0);
446 /* wait until command is processed or timeout occures */
447 while (get_timer(time_start) < timeo) {
449 if (chip->dev_ready(mtd))
455 * nand_command - [DEFAULT] Send command to NAND device
456 * @mtd: MTD device structure
457 * @command: the command to be sent
458 * @column: the column address for this command, -1 if none
459 * @page_addr: the page address for this command, -1 if none
461 * Send command to NAND device. This function is used for small page
462 * devices (256/512 Bytes per page)
464 static void nand_command(struct mtd_info *mtd, unsigned int command,
465 int column, int page_addr)
467 register struct nand_chip *chip = mtd->priv;
468 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
469 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
472 * Write out the command to the device.
474 if (command == NAND_CMD_SEQIN) {
477 if (column >= mtd->writesize) {
479 column -= mtd->writesize;
480 readcmd = NAND_CMD_READOOB;
481 } else if (column < 256) {
482 /* First 256 bytes --> READ0 */
483 readcmd = NAND_CMD_READ0;
486 readcmd = NAND_CMD_READ1;
488 chip->cmd_ctrl(mtd, readcmd, ctrl);
489 ctrl &= ~NAND_CTRL_CHANGE;
491 chip->cmd_ctrl(mtd, command, ctrl);
494 * Address cycle, when necessary
496 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
497 /* Serially input address */
499 /* Adjust columns for 16 bit buswidth */
500 if (chip->options & NAND_BUSWIDTH_16)
502 chip->cmd_ctrl(mtd, column, ctrl);
503 ctrl &= ~NAND_CTRL_CHANGE;
505 if (page_addr != -1) {
506 chip->cmd_ctrl(mtd, page_addr, ctrl);
507 ctrl &= ~NAND_CTRL_CHANGE;
508 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
509 /* One more address cycle for devices > 32MiB */
510 if (chip->chipsize > (32 << 20))
511 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
513 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
516 * program and erase have their own busy handlers
517 * status and sequential in needs no delay
521 case NAND_CMD_PAGEPROG:
522 case NAND_CMD_ERASE1:
523 case NAND_CMD_ERASE2:
525 case NAND_CMD_STATUS:
531 udelay(chip->chip_delay);
532 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
533 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
535 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
536 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
540 /* This applies to read commands */
543 * If we don't have access to the busy pin, we apply the given
546 if (!chip->dev_ready) {
547 udelay(chip->chip_delay);
551 /* Apply this short delay always to ensure that we do wait tWB in
552 * any case on any machine. */
555 nand_wait_ready(mtd);
559 * nand_command_lp - [DEFAULT] Send command to NAND large page device
560 * @mtd: MTD device structure
561 * @command: the command to be sent
562 * @column: the column address for this command, -1 if none
563 * @page_addr: the page address for this command, -1 if none
565 * Send command to NAND device. This is the version for the new large page
566 * devices We dont have the separate regions as we have in the small page
567 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
569 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
570 int column, int page_addr)
572 register struct nand_chip *chip = mtd->priv;
573 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
575 /* Emulate NAND_CMD_READOOB */
576 if (command == NAND_CMD_READOOB) {
577 column += mtd->writesize;
578 command = NAND_CMD_READ0;
581 /* Command latch cycle */
582 chip->cmd_ctrl(mtd, command & 0xff,
583 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
585 if (column != -1 || page_addr != -1) {
586 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
588 /* Serially input address */
590 /* Adjust columns for 16 bit buswidth */
591 if (chip->options & NAND_BUSWIDTH_16)
593 chip->cmd_ctrl(mtd, column, ctrl);
594 ctrl &= ~NAND_CTRL_CHANGE;
595 chip->cmd_ctrl(mtd, column >> 8, ctrl);
597 if (page_addr != -1) {
598 chip->cmd_ctrl(mtd, page_addr, ctrl);
599 chip->cmd_ctrl(mtd, page_addr >> 8,
600 NAND_NCE | NAND_ALE);
601 /* One more address cycle for devices > 128MiB */
602 if (chip->chipsize > (128 << 20))
603 chip->cmd_ctrl(mtd, page_addr >> 16,
604 NAND_NCE | NAND_ALE);
607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
610 * program and erase have their own busy handlers
611 * status, sequential in, and deplete1 need no delay
615 case NAND_CMD_CACHEDPROG:
616 case NAND_CMD_PAGEPROG:
617 case NAND_CMD_ERASE1:
618 case NAND_CMD_ERASE2:
621 case NAND_CMD_STATUS:
622 case NAND_CMD_DEPLETE1:
626 * read error status commands require only a short delay
628 case NAND_CMD_STATUS_ERROR:
629 case NAND_CMD_STATUS_ERROR0:
630 case NAND_CMD_STATUS_ERROR1:
631 case NAND_CMD_STATUS_ERROR2:
632 case NAND_CMD_STATUS_ERROR3:
633 udelay(chip->chip_delay);
639 udelay(chip->chip_delay);
640 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
641 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
642 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
643 NAND_NCE | NAND_CTRL_CHANGE);
644 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
648 case NAND_CMD_RNDOUT:
649 /* No ready / busy check necessary */
650 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
651 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
652 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
653 NAND_NCE | NAND_CTRL_CHANGE);
657 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
658 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
659 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
660 NAND_NCE | NAND_CTRL_CHANGE);
662 /* This applies to read commands */
665 * If we don't have access to the busy pin, we apply the given
668 if (!chip->dev_ready) {
669 udelay(chip->chip_delay);
674 /* Apply this short delay always to ensure that we do wait tWB in
675 * any case on any machine. */
678 nand_wait_ready(mtd);
682 * nand_get_device - [GENERIC] Get chip for selected access
683 * @chip: the nand chip descriptor
684 * @mtd: MTD device structure
685 * @new_state: the state which is requested
687 * Get the device and lock it for exclusive access
689 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
691 this->state = new_state;
696 * nand_wait - [DEFAULT] wait until the command is done
697 * @mtd: MTD device structure
698 * @chip: NAND chip structure
700 * Wait for command done. This applies to erase and program only
701 * Erase can take up to 400ms and program up to 20ms according to
702 * general NAND and SmartMedia specs
704 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
707 int state = this->state;
710 if (state == FL_ERASING)
711 timeo = (CONFIG_SYS_HZ * 400) / 1000;
713 timeo = (CONFIG_SYS_HZ * 20) / 1000;
715 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
716 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
718 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
720 time_start = get_timer(0);
723 if (get_timer(time_start) > timeo) {
728 if (this->dev_ready) {
729 if (this->dev_ready(mtd))
732 if (this->read_byte(mtd) & NAND_STATUS_READY)
736 #ifdef PPCHAMELON_NAND_TIMER_HACK
737 time_start = get_timer(0);
738 while (get_timer(time_start) < 10)
740 #endif /* PPCHAMELON_NAND_TIMER_HACK */
742 return this->read_byte(mtd);
746 * nand_read_page_raw - [Intern] read raw page data without ecc
747 * @mtd: mtd info structure
748 * @chip: nand chip info structure
749 * @buf: buffer to store read data
750 * @page: page number to read
752 * Not for syndrome calculating ecc controllers, which use a special oob layout
754 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
755 uint8_t *buf, int page)
757 chip->read_buf(mtd, buf, mtd->writesize);
758 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
763 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
764 * @mtd: mtd info structure
765 * @chip: nand chip info structure
766 * @buf: buffer to store read data
767 * @page: page number to read
769 * We need a special oob layout and handling even when OOB isn't used.
771 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
772 uint8_t *buf, int page)
774 int eccsize = chip->ecc.size;
775 int eccbytes = chip->ecc.bytes;
776 uint8_t *oob = chip->oob_poi;
779 for (steps = chip->ecc.steps; steps > 0; steps--) {
780 chip->read_buf(mtd, buf, eccsize);
783 if (chip->ecc.prepad) {
784 chip->read_buf(mtd, oob, chip->ecc.prepad);
785 oob += chip->ecc.prepad;
788 chip->read_buf(mtd, oob, eccbytes);
791 if (chip->ecc.postpad) {
792 chip->read_buf(mtd, oob, chip->ecc.postpad);
793 oob += chip->ecc.postpad;
797 size = mtd->oobsize - (oob - chip->oob_poi);
799 chip->read_buf(mtd, oob, size);
805 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
806 * @mtd: mtd info structure
807 * @chip: nand chip info structure
808 * @buf: buffer to store read data
809 * @page: page number to read
811 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
812 uint8_t *buf, int page)
814 int i, eccsize = chip->ecc.size;
815 int eccbytes = chip->ecc.bytes;
816 int eccsteps = chip->ecc.steps;
818 uint8_t *ecc_calc = chip->buffers->ecccalc;
819 uint8_t *ecc_code = chip->buffers->ecccode;
820 uint32_t *eccpos = chip->ecc.layout->eccpos;
822 chip->ecc.read_page_raw(mtd, chip, buf, page);
824 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
825 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
827 for (i = 0; i < chip->ecc.total; i++)
828 ecc_code[i] = chip->oob_poi[eccpos[i]];
830 eccsteps = chip->ecc.steps;
833 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
836 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
838 mtd->ecc_stats.failed++;
840 mtd->ecc_stats.corrected += stat;
846 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
847 * @mtd: mtd info structure
848 * @chip: nand chip info structure
849 * @data_offs: offset of requested data within the page
850 * @readlen: data length
851 * @bufpoi: buffer to store read data
853 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
855 int start_step, end_step, num_steps;
856 uint32_t *eccpos = chip->ecc.layout->eccpos;
858 int data_col_addr, i, gaps = 0;
859 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
860 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
862 /* Column address wihin the page aligned to ECC size (256bytes). */
863 start_step = data_offs / chip->ecc.size;
864 end_step = (data_offs + readlen - 1) / chip->ecc.size;
865 num_steps = end_step - start_step + 1;
867 /* Data size aligned to ECC ecc.size*/
868 datafrag_len = num_steps * chip->ecc.size;
869 eccfrag_len = num_steps * chip->ecc.bytes;
871 data_col_addr = start_step * chip->ecc.size;
872 /* If we read not a page aligned data */
873 if (data_col_addr != 0)
874 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
876 p = bufpoi + data_col_addr;
877 chip->read_buf(mtd, p, datafrag_len);
880 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
881 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
883 /* The performance is faster if to position offsets
884 according to ecc.pos. Let make sure here that
885 there are no gaps in ecc positions */
886 for (i = 0; i < eccfrag_len - 1; i++) {
887 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
888 eccpos[i + start_step * chip->ecc.bytes + 1]) {
894 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
895 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
897 /* send the command to read the particular ecc bytes */
898 /* take care about buswidth alignment in read_buf */
899 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
900 aligned_len = eccfrag_len;
901 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
903 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
906 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
907 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
910 for (i = 0; i < eccfrag_len; i++)
911 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
913 p = bufpoi + data_col_addr;
914 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
917 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
919 mtd->ecc_stats.failed++;
921 mtd->ecc_stats.corrected += stat;
927 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
928 * @mtd: mtd info structure
929 * @chip: nand chip info structure
930 * @buf: buffer to store read data
931 * @page: page number to read
933 * Not for syndrome calculating ecc controllers which need a special oob layout
935 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
936 uint8_t *buf, int page)
938 int i, eccsize = chip->ecc.size;
939 int eccbytes = chip->ecc.bytes;
940 int eccsteps = chip->ecc.steps;
942 uint8_t *ecc_calc = chip->buffers->ecccalc;
943 uint8_t *ecc_code = chip->buffers->ecccode;
944 uint32_t *eccpos = chip->ecc.layout->eccpos;
946 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
947 chip->ecc.hwctl(mtd, NAND_ECC_READ);
948 chip->read_buf(mtd, p, eccsize);
949 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
951 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
953 for (i = 0; i < chip->ecc.total; i++)
954 ecc_code[i] = chip->oob_poi[eccpos[i]];
956 eccsteps = chip->ecc.steps;
959 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
962 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
964 mtd->ecc_stats.failed++;
966 mtd->ecc_stats.corrected += stat;
972 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
973 * @mtd: mtd info structure
974 * @chip: nand chip info structure
975 * @buf: buffer to store read data
976 * @page: page number to read
978 * Hardware ECC for large page chips, require OOB to be read first.
979 * For this ECC mode, the write_page method is re-used from ECC_HW.
980 * These methods read/write ECC from the OOB area, unlike the
981 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
982 * "infix ECC" scheme and reads/writes ECC from the data area, by
983 * overwriting the NAND manufacturer bad block markings.
985 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
986 struct nand_chip *chip, uint8_t *buf, int page)
988 int i, eccsize = chip->ecc.size;
989 int eccbytes = chip->ecc.bytes;
990 int eccsteps = chip->ecc.steps;
992 uint8_t *ecc_code = chip->buffers->ecccode;
993 uint32_t *eccpos = chip->ecc.layout->eccpos;
994 uint8_t *ecc_calc = chip->buffers->ecccalc;
996 /* Read the OOB area first */
997 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
998 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
999 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1001 for (i = 0; i < chip->ecc.total; i++)
1002 ecc_code[i] = chip->oob_poi[eccpos[i]];
1004 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1007 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1008 chip->read_buf(mtd, p, eccsize);
1009 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1011 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1013 mtd->ecc_stats.failed++;
1015 mtd->ecc_stats.corrected += stat;
1021 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1022 * @mtd: mtd info structure
1023 * @chip: nand chip info structure
1024 * @buf: buffer to store read data
1025 * @page: page number to read
1027 * The hw generator calculates the error syndrome automatically. Therefor
1028 * we need a special oob layout and handling.
1030 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1031 uint8_t *buf, int page)
1033 int i, eccsize = chip->ecc.size;
1034 int eccbytes = chip->ecc.bytes;
1035 int eccsteps = chip->ecc.steps;
1037 uint8_t *oob = chip->oob_poi;
1039 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1042 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1043 chip->read_buf(mtd, p, eccsize);
1045 if (chip->ecc.prepad) {
1046 chip->read_buf(mtd, oob, chip->ecc.prepad);
1047 oob += chip->ecc.prepad;
1050 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1051 chip->read_buf(mtd, oob, eccbytes);
1052 stat = chip->ecc.correct(mtd, p, oob, NULL);
1055 mtd->ecc_stats.failed++;
1057 mtd->ecc_stats.corrected += stat;
1061 if (chip->ecc.postpad) {
1062 chip->read_buf(mtd, oob, chip->ecc.postpad);
1063 oob += chip->ecc.postpad;
1067 /* Calculate remaining oob bytes */
1068 i = mtd->oobsize - (oob - chip->oob_poi);
1070 chip->read_buf(mtd, oob, i);
1076 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1077 * @chip: nand chip structure
1078 * @oob: oob destination address
1079 * @ops: oob ops structure
1080 * @len: size of oob to transfer
1082 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1083 struct mtd_oob_ops *ops, size_t len)
1089 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1092 case MTD_OOB_AUTO: {
1093 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1094 uint32_t boffs = 0, roffs = ops->ooboffs;
1097 for(; free->length && len; free++, len -= bytes) {
1098 /* Read request not from offset 0 ? */
1099 if (unlikely(roffs)) {
1100 if (roffs >= free->length) {
1101 roffs -= free->length;
1104 boffs = free->offset + roffs;
1105 bytes = min_t(size_t, len,
1106 (free->length - roffs));
1109 bytes = min_t(size_t, len, free->length);
1110 boffs = free->offset;
1112 memcpy(oob, chip->oob_poi + boffs, bytes);
1124 * nand_do_read_ops - [Internal] Read data with ECC
1126 * @mtd: MTD device structure
1127 * @from: offset to read from
1128 * @ops: oob ops structure
1130 * Internal function. Called with chip held.
1132 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1133 struct mtd_oob_ops *ops)
1135 int chipnr, page, realpage, col, bytes, aligned;
1136 struct nand_chip *chip = mtd->priv;
1137 struct mtd_ecc_stats stats;
1138 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1141 uint32_t readlen = ops->len;
1142 uint32_t oobreadlen = ops->ooblen;
1143 uint8_t *bufpoi, *oob, *buf;
1145 stats = mtd->ecc_stats;
1147 chipnr = (int)(from >> chip->chip_shift);
1148 chip->select_chip(mtd, chipnr);
1150 realpage = (int)(from >> chip->page_shift);
1151 page = realpage & chip->pagemask;
1153 col = (int)(from & (mtd->writesize - 1));
1161 bytes = min(mtd->writesize - col, readlen);
1162 aligned = (bytes == mtd->writesize);
1164 /* Is the current page in the buffer ? */
1165 if (realpage != chip->pagebuf || oob) {
1166 bufpoi = aligned ? buf : chip->buffers->databuf;
1168 if (likely(sndcmd)) {
1169 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1173 /* Now read the page into the buffer */
1174 if (unlikely(ops->mode == MTD_OOB_RAW))
1175 ret = chip->ecc.read_page_raw(mtd, chip,
1177 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1178 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1180 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1185 /* Transfer not aligned data */
1187 if (!NAND_SUBPAGE_READ(chip) && !oob)
1188 chip->pagebuf = realpage;
1189 memcpy(buf, chip->buffers->databuf + col, bytes);
1194 if (unlikely(oob)) {
1195 /* Raw mode does data:oob:data:oob */
1196 if (ops->mode != MTD_OOB_RAW) {
1197 int toread = min(oobreadlen,
1198 chip->ecc.layout->oobavail);
1200 oob = nand_transfer_oob(chip,
1202 oobreadlen -= toread;
1205 buf = nand_transfer_oob(chip,
1206 buf, ops, mtd->oobsize);
1209 if (!(chip->options & NAND_NO_READRDY)) {
1211 * Apply delay or wait for ready/busy pin. Do
1212 * this before the AUTOINCR check, so no
1213 * problems arise if a chip which does auto
1214 * increment is marked as NOAUTOINCR by the
1217 if (!chip->dev_ready)
1218 udelay(chip->chip_delay);
1220 nand_wait_ready(mtd);
1223 memcpy(buf, chip->buffers->databuf + col, bytes);
1232 /* For subsequent reads align to page boundary. */
1234 /* Increment page address */
1237 page = realpage & chip->pagemask;
1238 /* Check, if we cross a chip boundary */
1241 chip->select_chip(mtd, -1);
1242 chip->select_chip(mtd, chipnr);
1245 /* Check, if the chip supports auto page increment
1246 * or if we have hit a block boundary.
1248 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1252 ops->retlen = ops->len - (size_t) readlen;
1254 ops->oobretlen = ops->ooblen - oobreadlen;
1259 if (mtd->ecc_stats.failed - stats.failed)
1262 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1266 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1267 * @mtd: MTD device structure
1268 * @from: offset to read from
1269 * @len: number of bytes to read
1270 * @retlen: pointer to variable to store the number of read bytes
1271 * @buf: the databuffer to put data
1273 * Get hold of the chip and call nand_do_read
1275 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1276 size_t *retlen, uint8_t *buf)
1278 struct nand_chip *chip = mtd->priv;
1281 /* Do not allow reads past end of device */
1282 if ((from + len) > mtd->size)
1287 nand_get_device(chip, mtd, FL_READING);
1289 chip->ops.len = len;
1290 chip->ops.datbuf = buf;
1291 chip->ops.oobbuf = NULL;
1293 ret = nand_do_read_ops(mtd, from, &chip->ops);
1295 *retlen = chip->ops.retlen;
1297 nand_release_device(mtd);
1303 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1304 * @mtd: mtd info structure
1305 * @chip: nand chip info structure
1306 * @page: page number to read
1307 * @sndcmd: flag whether to issue read command or not
1309 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1310 int page, int sndcmd)
1313 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1316 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1321 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1323 * @mtd: mtd info structure
1324 * @chip: nand chip info structure
1325 * @page: page number to read
1326 * @sndcmd: flag whether to issue read command or not
1328 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1329 int page, int sndcmd)
1331 uint8_t *buf = chip->oob_poi;
1332 int length = mtd->oobsize;
1333 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1334 int eccsize = chip->ecc.size;
1335 uint8_t *bufpoi = buf;
1336 int i, toread, sndrnd = 0, pos;
1338 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1339 for (i = 0; i < chip->ecc.steps; i++) {
1341 pos = eccsize + i * (eccsize + chunk);
1342 if (mtd->writesize > 512)
1343 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1345 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1348 toread = min_t(int, length, chunk);
1349 chip->read_buf(mtd, bufpoi, toread);
1354 chip->read_buf(mtd, bufpoi, length);
1360 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1361 * @mtd: mtd info structure
1362 * @chip: nand chip info structure
1363 * @page: page number to write
1365 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1369 const uint8_t *buf = chip->oob_poi;
1370 int length = mtd->oobsize;
1372 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1373 chip->write_buf(mtd, buf, length);
1374 /* Send command to program the OOB data */
1375 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1377 status = chip->waitfunc(mtd, chip);
1379 return status & NAND_STATUS_FAIL ? -EIO : 0;
1383 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1384 * with syndrome - only for large page flash !
1385 * @mtd: mtd info structure
1386 * @chip: nand chip info structure
1387 * @page: page number to write
1389 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1390 struct nand_chip *chip, int page)
1392 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1393 int eccsize = chip->ecc.size, length = mtd->oobsize;
1394 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1395 const uint8_t *bufpoi = chip->oob_poi;
1398 * data-ecc-data-ecc ... ecc-oob
1400 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1402 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1403 pos = steps * (eccsize + chunk);
1408 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1409 for (i = 0; i < steps; i++) {
1411 if (mtd->writesize <= 512) {
1412 uint32_t fill = 0xFFFFFFFF;
1416 int num = min_t(int, len, 4);
1417 chip->write_buf(mtd, (uint8_t *)&fill,
1422 pos = eccsize + i * (eccsize + chunk);
1423 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1427 len = min_t(int, length, chunk);
1428 chip->write_buf(mtd, bufpoi, len);
1433 chip->write_buf(mtd, bufpoi, length);
1435 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1436 status = chip->waitfunc(mtd, chip);
1438 return status & NAND_STATUS_FAIL ? -EIO : 0;
1442 * nand_do_read_oob - [Intern] NAND read out-of-band
1443 * @mtd: MTD device structure
1444 * @from: offset to read from
1445 * @ops: oob operations description structure
1447 * NAND read out-of-band data from the spare area
1449 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1450 struct mtd_oob_ops *ops)
1452 int page, realpage, chipnr, sndcmd = 1;
1453 struct nand_chip *chip = mtd->priv;
1454 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1455 int readlen = ops->ooblen;
1457 uint8_t *buf = ops->oobbuf;
1459 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1460 (unsigned long long)from, readlen);
1462 if (ops->mode == MTD_OOB_AUTO)
1463 len = chip->ecc.layout->oobavail;
1467 if (unlikely(ops->ooboffs >= len)) {
1468 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1469 "Attempt to start read outside oob\n");
1473 /* Do not allow reads past end of device */
1474 if (unlikely(from >= mtd->size ||
1475 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1476 (from >> chip->page_shift)) * len)) {
1477 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1478 "Attempt read beyond end of device\n");
1482 chipnr = (int)(from >> chip->chip_shift);
1483 chip->select_chip(mtd, chipnr);
1485 /* Shift to get page */
1486 realpage = (int)(from >> chip->page_shift);
1487 page = realpage & chip->pagemask;
1491 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1493 len = min(len, readlen);
1494 buf = nand_transfer_oob(chip, buf, ops, len);
1496 if (!(chip->options & NAND_NO_READRDY)) {
1498 * Apply delay or wait for ready/busy pin. Do this
1499 * before the AUTOINCR check, so no problems arise if a
1500 * chip which does auto increment is marked as
1501 * NOAUTOINCR by the board driver.
1503 if (!chip->dev_ready)
1504 udelay(chip->chip_delay);
1506 nand_wait_ready(mtd);
1513 /* Increment page address */
1516 page = realpage & chip->pagemask;
1517 /* Check, if we cross a chip boundary */
1520 chip->select_chip(mtd, -1);
1521 chip->select_chip(mtd, chipnr);
1524 /* Check, if the chip supports auto page increment
1525 * or if we have hit a block boundary.
1527 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1531 ops->oobretlen = ops->ooblen;
1536 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1537 * @mtd: MTD device structure
1538 * @from: offset to read from
1539 * @ops: oob operation description structure
1541 * NAND read data and/or out-of-band data
1543 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1544 struct mtd_oob_ops *ops)
1546 struct nand_chip *chip = mtd->priv;
1547 int ret = -ENOTSUPP;
1551 /* Do not allow reads past end of device */
1552 if (ops->datbuf && (from + ops->len) > mtd->size) {
1553 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1554 "Attempt read beyond end of device\n");
1558 nand_get_device(chip, mtd, FL_READING);
1571 ret = nand_do_read_oob(mtd, from, ops);
1573 ret = nand_do_read_ops(mtd, from, ops);
1576 nand_release_device(mtd);
1582 * nand_write_page_raw - [Intern] raw page write function
1583 * @mtd: mtd info structure
1584 * @chip: nand chip info structure
1587 * Not for syndrome calculating ecc controllers, which use a special oob layout
1589 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1592 chip->write_buf(mtd, buf, mtd->writesize);
1593 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1597 * nand_write_page_raw_syndrome - [Intern] raw page write function
1598 * @mtd: mtd info structure
1599 * @chip: nand chip info structure
1602 * We need a special oob layout and handling even when ECC isn't checked.
1604 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1607 int eccsize = chip->ecc.size;
1608 int eccbytes = chip->ecc.bytes;
1609 uint8_t *oob = chip->oob_poi;
1612 for (steps = chip->ecc.steps; steps > 0; steps--) {
1613 chip->write_buf(mtd, buf, eccsize);
1616 if (chip->ecc.prepad) {
1617 chip->write_buf(mtd, oob, chip->ecc.prepad);
1618 oob += chip->ecc.prepad;
1621 chip->read_buf(mtd, oob, eccbytes);
1624 if (chip->ecc.postpad) {
1625 chip->write_buf(mtd, oob, chip->ecc.postpad);
1626 oob += chip->ecc.postpad;
1630 size = mtd->oobsize - (oob - chip->oob_poi);
1632 chip->write_buf(mtd, oob, size);
1635 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1636 * @mtd: mtd info structure
1637 * @chip: nand chip info structure
1640 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1643 int i, eccsize = chip->ecc.size;
1644 int eccbytes = chip->ecc.bytes;
1645 int eccsteps = chip->ecc.steps;
1646 uint8_t *ecc_calc = chip->buffers->ecccalc;
1647 const uint8_t *p = buf;
1648 uint32_t *eccpos = chip->ecc.layout->eccpos;
1650 /* Software ecc calculation */
1651 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1652 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1654 for (i = 0; i < chip->ecc.total; i++)
1655 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1657 chip->ecc.write_page_raw(mtd, chip, buf);
1661 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1662 * @mtd: mtd info structure
1663 * @chip: nand chip info structure
1666 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1669 int i, eccsize = chip->ecc.size;
1670 int eccbytes = chip->ecc.bytes;
1671 int eccsteps = chip->ecc.steps;
1672 uint8_t *ecc_calc = chip->buffers->ecccalc;
1673 const uint8_t *p = buf;
1674 uint32_t *eccpos = chip->ecc.layout->eccpos;
1676 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1677 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1678 chip->write_buf(mtd, p, eccsize);
1679 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1682 for (i = 0; i < chip->ecc.total; i++)
1683 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1685 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1689 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1690 * @mtd: mtd info structure
1691 * @chip: nand chip info structure
1694 * The hw generator calculates the error syndrome automatically. Therefor
1695 * we need a special oob layout and handling.
1697 static void nand_write_page_syndrome(struct mtd_info *mtd,
1698 struct nand_chip *chip, const uint8_t *buf)
1700 int i, eccsize = chip->ecc.size;
1701 int eccbytes = chip->ecc.bytes;
1702 int eccsteps = chip->ecc.steps;
1703 const uint8_t *p = buf;
1704 uint8_t *oob = chip->oob_poi;
1706 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1708 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1709 chip->write_buf(mtd, p, eccsize);
1711 if (chip->ecc.prepad) {
1712 chip->write_buf(mtd, oob, chip->ecc.prepad);
1713 oob += chip->ecc.prepad;
1716 chip->ecc.calculate(mtd, p, oob);
1717 chip->write_buf(mtd, oob, eccbytes);
1720 if (chip->ecc.postpad) {
1721 chip->write_buf(mtd, oob, chip->ecc.postpad);
1722 oob += chip->ecc.postpad;
1726 /* Calculate remaining oob bytes */
1727 i = mtd->oobsize - (oob - chip->oob_poi);
1729 chip->write_buf(mtd, oob, i);
1733 * nand_write_page - [REPLACEABLE] write one page
1734 * @mtd: MTD device structure
1735 * @chip: NAND chip descriptor
1736 * @buf: the data to write
1737 * @page: page number to write
1738 * @cached: cached programming
1739 * @raw: use _raw version of write_page
1741 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1742 const uint8_t *buf, int page, int cached, int raw)
1746 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1749 chip->ecc.write_page_raw(mtd, chip, buf);
1751 chip->ecc.write_page(mtd, chip, buf);
1754 * Cached progamming disabled for now, Not sure if its worth the
1755 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1759 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1761 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1762 status = chip->waitfunc(mtd, chip);
1764 * See if operation failed and additional status checks are
1767 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1768 status = chip->errstat(mtd, chip, FL_WRITING, status,
1771 if (status & NAND_STATUS_FAIL)
1774 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1775 status = chip->waitfunc(mtd, chip);
1778 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1779 /* Send command to read back the data */
1780 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1782 if (chip->verify_buf(mtd, buf, mtd->writesize))
1789 * nand_fill_oob - [Internal] Transfer client buffer to oob
1790 * @chip: nand chip structure
1791 * @oob: oob data buffer
1792 * @ops: oob ops structure
1794 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1795 struct mtd_oob_ops *ops)
1797 size_t len = ops->ooblen;
1803 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1806 case MTD_OOB_AUTO: {
1807 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1808 uint32_t boffs = 0, woffs = ops->ooboffs;
1811 for(; free->length && len; free++, len -= bytes) {
1812 /* Write request not from offset 0 ? */
1813 if (unlikely(woffs)) {
1814 if (woffs >= free->length) {
1815 woffs -= free->length;
1818 boffs = free->offset + woffs;
1819 bytes = min_t(size_t, len,
1820 (free->length - woffs));
1823 bytes = min_t(size_t, len, free->length);
1824 boffs = free->offset;
1826 memcpy(chip->oob_poi + boffs, oob, bytes);
1837 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1840 * nand_do_write_ops - [Internal] NAND write with ECC
1841 * @mtd: MTD device structure
1842 * @to: offset to write to
1843 * @ops: oob operations description structure
1845 * NAND write with ECC
1847 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1848 struct mtd_oob_ops *ops)
1850 int chipnr, realpage, page, blockmask, column;
1851 struct nand_chip *chip = mtd->priv;
1852 uint32_t writelen = ops->len;
1853 uint8_t *oob = ops->oobbuf;
1854 uint8_t *buf = ops->datbuf;
1861 column = to & (mtd->writesize - 1);
1862 subpage = column || (writelen & (mtd->writesize - 1));
1867 chipnr = (int)(to >> chip->chip_shift);
1868 chip->select_chip(mtd, chipnr);
1870 /* Check, if it is write protected */
1871 if (nand_check_wp(mtd)) {
1872 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1876 realpage = (int)(to >> chip->page_shift);
1877 page = realpage & chip->pagemask;
1878 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1880 /* Invalidate the page cache, when we write to the cached page */
1881 if (to <= (chip->pagebuf << chip->page_shift) &&
1882 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1885 /* If we're not given explicit OOB data, let it be 0xFF */
1887 memset(chip->oob_poi, 0xff, mtd->oobsize);
1892 int bytes = mtd->writesize;
1893 int cached = writelen > bytes && page != blockmask;
1894 uint8_t *wbuf = buf;
1896 /* Partial page write ? */
1897 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1899 bytes = min_t(int, bytes - column, (int) writelen);
1901 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1902 memcpy(&chip->buffers->databuf[column], buf, bytes);
1903 wbuf = chip->buffers->databuf;
1907 oob = nand_fill_oob(chip, oob, ops);
1909 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1910 (ops->mode == MTD_OOB_RAW));
1922 page = realpage & chip->pagemask;
1923 /* Check, if we cross a chip boundary */
1926 chip->select_chip(mtd, -1);
1927 chip->select_chip(mtd, chipnr);
1931 ops->retlen = ops->len - writelen;
1933 ops->oobretlen = ops->ooblen;
1938 * nand_write - [MTD Interface] NAND write with ECC
1939 * @mtd: MTD device structure
1940 * @to: offset to write to
1941 * @len: number of bytes to write
1942 * @retlen: pointer to variable to store the number of written bytes
1943 * @buf: the data to write
1945 * NAND write with ECC
1947 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1948 size_t *retlen, const uint8_t *buf)
1950 struct nand_chip *chip = mtd->priv;
1953 /* Do not allow writes past end of device */
1954 if ((to + len) > mtd->size)
1959 nand_get_device(chip, mtd, FL_WRITING);
1961 chip->ops.len = len;
1962 chip->ops.datbuf = (uint8_t *)buf;
1963 chip->ops.oobbuf = NULL;
1965 ret = nand_do_write_ops(mtd, to, &chip->ops);
1967 *retlen = chip->ops.retlen;
1969 nand_release_device(mtd);
1975 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1976 * @mtd: MTD device structure
1977 * @to: offset to write to
1978 * @ops: oob operation description structure
1980 * NAND write out-of-band
1982 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1983 struct mtd_oob_ops *ops)
1985 int chipnr, page, status, len;
1986 struct nand_chip *chip = mtd->priv;
1988 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1989 (unsigned int)to, (int)ops->ooblen);
1991 if (ops->mode == MTD_OOB_AUTO)
1992 len = chip->ecc.layout->oobavail;
1996 /* Do not allow write past end of page */
1997 if ((ops->ooboffs + ops->ooblen) > len) {
1998 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1999 "Attempt to write past end of page\n");
2003 if (unlikely(ops->ooboffs >= len)) {
2004 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2005 "Attempt to start write outside oob\n");
2009 /* Do not allow reads past end of device */
2010 if (unlikely(to >= mtd->size ||
2011 ops->ooboffs + ops->ooblen >
2012 ((mtd->size >> chip->page_shift) -
2013 (to >> chip->page_shift)) * len)) {
2014 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2015 "Attempt write beyond end of device\n");
2019 chipnr = (int)(to >> chip->chip_shift);
2020 chip->select_chip(mtd, chipnr);
2022 /* Shift to get page */
2023 page = (int)(to >> chip->page_shift);
2026 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2027 * of my DiskOnChip 2000 test units) will clear the whole data page too
2028 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2029 * it in the doc2000 driver in August 1999. dwmw2.
2031 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2033 /* Check, if it is write protected */
2034 if (nand_check_wp(mtd))
2037 /* Invalidate the page cache, if we write to the cached page */
2038 if (page == chip->pagebuf)
2041 memset(chip->oob_poi, 0xff, mtd->oobsize);
2042 nand_fill_oob(chip, ops->oobbuf, ops);
2043 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2044 memset(chip->oob_poi, 0xff, mtd->oobsize);
2049 ops->oobretlen = ops->ooblen;
2055 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2056 * @mtd: MTD device structure
2057 * @to: offset to write to
2058 * @ops: oob operation description structure
2060 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2061 struct mtd_oob_ops *ops)
2063 struct nand_chip *chip = mtd->priv;
2064 int ret = -ENOTSUPP;
2068 /* Do not allow writes past end of device */
2069 if (ops->datbuf && (to + ops->len) > mtd->size) {
2070 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2071 "Attempt read beyond end of device\n");
2075 nand_get_device(chip, mtd, FL_WRITING);
2088 ret = nand_do_write_oob(mtd, to, ops);
2090 ret = nand_do_write_ops(mtd, to, ops);
2093 nand_release_device(mtd);
2098 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2099 * @mtd: MTD device structure
2100 * @page: the page address of the block which will be erased
2102 * Standard erase command for NAND chips
2104 static void single_erase_cmd(struct mtd_info *mtd, int page)
2106 struct nand_chip *chip = mtd->priv;
2107 /* Send commands to erase a block */
2108 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2109 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2113 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2114 * @mtd: MTD device structure
2115 * @page: the page address of the block which will be erased
2117 * AND multi block erase command function
2118 * Erase 4 consecutive blocks
2120 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2122 struct nand_chip *chip = mtd->priv;
2123 /* Send commands to erase a block */
2124 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2125 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2126 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2127 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2128 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2132 * nand_erase - [MTD Interface] erase block(s)
2133 * @mtd: MTD device structure
2134 * @instr: erase instruction
2136 * Erase one ore more blocks
2138 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2140 return nand_erase_nand(mtd, instr, 0);
2143 #define BBT_PAGE_MASK 0xffffff3f
2145 * nand_erase_nand - [Internal] erase block(s)
2146 * @mtd: MTD device structure
2147 * @instr: erase instruction
2148 * @allowbbt: allow erasing the bbt area
2150 * Erase one ore more blocks
2152 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2155 int page, status, pages_per_block, ret, chipnr;
2156 struct nand_chip *chip = mtd->priv;
2157 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2158 unsigned int bbt_masked_page = 0xffffffff;
2161 MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2162 "len = %llu\n", (unsigned long long) instr->addr,
2163 (unsigned long long) instr->len);
2165 /* Start address must align on block boundary */
2166 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2167 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2171 /* Length must align on block boundary */
2172 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2173 MTDDEBUG (MTD_DEBUG_LEVEL0,
2174 "nand_erase: Length not block aligned\n");
2178 /* Do not allow erase past end of device */
2179 if ((instr->len + instr->addr) > mtd->size) {
2180 MTDDEBUG (MTD_DEBUG_LEVEL0,
2181 "nand_erase: Erase past end of device\n");
2185 instr->fail_addr = 0xffffffff;
2187 /* Grab the lock and see if the device is available */
2188 nand_get_device(chip, mtd, FL_ERASING);
2190 /* Shift to get first page */
2191 page = (int)(instr->addr >> chip->page_shift);
2192 chipnr = (int)(instr->addr >> chip->chip_shift);
2194 /* Calculate pages in each block */
2195 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2197 /* Select the NAND device */
2198 chip->select_chip(mtd, chipnr);
2200 /* Check, if it is write protected */
2201 if (nand_check_wp(mtd)) {
2202 MTDDEBUG (MTD_DEBUG_LEVEL0,
2203 "nand_erase: Device is write protected!!!\n");
2204 instr->state = MTD_ERASE_FAILED;
2209 * If BBT requires refresh, set the BBT page mask to see if the BBT
2210 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2211 * can not be matched. This is also done when the bbt is actually
2212 * erased to avoid recusrsive updates
2214 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2215 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2217 /* Loop through the pages */
2220 instr->state = MTD_ERASING;
2225 * heck if we have a bad block, we do not erase bad blocks !
2227 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2228 chip->page_shift, 0, allowbbt)) {
2229 printk(KERN_WARNING "nand_erase: attempt to erase a "
2230 "bad block at page 0x%08x\n", page);
2231 instr->state = MTD_ERASE_FAILED;
2236 * Invalidate the page cache, if we erase the block which
2237 * contains the current cached page
2239 if (page <= chip->pagebuf && chip->pagebuf <
2240 (page + pages_per_block))
2243 chip->erase_cmd(mtd, page & chip->pagemask);
2245 status = chip->waitfunc(mtd, chip);
2248 * See if operation failed and additional status checks are
2251 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2252 status = chip->errstat(mtd, chip, FL_ERASING,
2255 /* See if block erase succeeded */
2256 if (status & NAND_STATUS_FAIL) {
2257 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2258 "Failed erase, page 0x%08x\n", page);
2259 instr->state = MTD_ERASE_FAILED;
2260 instr->fail_addr = ((loff_t)page << chip->page_shift);
2265 * If BBT requires refresh, set the BBT rewrite flag to the
2268 if (bbt_masked_page != 0xffffffff &&
2269 (page & BBT_PAGE_MASK) == bbt_masked_page)
2270 rewrite_bbt[chipnr] =
2271 ((loff_t)page << chip->page_shift);
2273 /* Increment page address and decrement length */
2274 len -= (1 << chip->phys_erase_shift);
2275 page += pages_per_block;
2277 /* Check, if we cross a chip boundary */
2278 if (len && !(page & chip->pagemask)) {
2280 chip->select_chip(mtd, -1);
2281 chip->select_chip(mtd, chipnr);
2284 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2285 * page mask to see if this BBT should be rewritten
2287 if (bbt_masked_page != 0xffffffff &&
2288 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2289 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2293 instr->state = MTD_ERASE_DONE;
2297 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2299 /* Deselect and wake up anyone waiting on the device */
2300 nand_release_device(mtd);
2302 /* Do call back function */
2304 mtd_erase_callback(instr);
2307 * If BBT requires refresh and erase was successful, rewrite any
2308 * selected bad block tables
2310 if (bbt_masked_page == 0xffffffff || ret)
2313 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2314 if (!rewrite_bbt[chipnr])
2316 /* update the BBT for chip */
2317 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2318 "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2319 chip->bbt_td->pages[chipnr]);
2320 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2323 /* Return more or less happy */
2328 * nand_sync - [MTD Interface] sync
2329 * @mtd: MTD device structure
2331 * Sync is actually a wait for chip ready function
2333 static void nand_sync(struct mtd_info *mtd)
2335 struct nand_chip *chip = mtd->priv;
2337 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2339 /* Grab the lock and see if the device is available */
2340 nand_get_device(chip, mtd, FL_SYNCING);
2341 /* Release it and go back */
2342 nand_release_device(mtd);
2346 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2347 * @mtd: MTD device structure
2348 * @offs: offset relative to mtd start
2350 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2352 /* Check for invalid offset */
2353 if (offs > mtd->size)
2356 return nand_block_checkbad(mtd, offs, 1, 0);
2360 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2361 * @mtd: MTD device structure
2362 * @ofs: offset relative to mtd start
2364 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2366 struct nand_chip *chip = mtd->priv;
2369 if ((ret = nand_block_isbad(mtd, ofs))) {
2370 /* If it was bad already, return success and do nothing. */
2376 return chip->block_markbad(mtd, ofs);
2380 * Set default functions
2382 static void nand_set_defaults(struct nand_chip *chip, int busw)
2384 /* check for proper chip_delay setup, set 20us if not */
2385 if (!chip->chip_delay)
2386 chip->chip_delay = 20;
2388 /* check, if a user supplied command function given */
2389 if (chip->cmdfunc == NULL)
2390 chip->cmdfunc = nand_command;
2392 /* check, if a user supplied wait function given */
2393 if (chip->waitfunc == NULL)
2394 chip->waitfunc = nand_wait;
2396 if (!chip->select_chip)
2397 chip->select_chip = nand_select_chip;
2398 if (!chip->read_byte)
2399 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2400 if (!chip->read_word)
2401 chip->read_word = nand_read_word;
2402 if (!chip->block_bad)
2403 chip->block_bad = nand_block_bad;
2404 if (!chip->block_markbad)
2405 chip->block_markbad = nand_default_block_markbad;
2406 if (!chip->write_buf)
2407 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2408 if (!chip->read_buf)
2409 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2410 if (!chip->verify_buf)
2411 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2412 if (!chip->scan_bbt)
2413 chip->scan_bbt = nand_default_bbt;
2414 if (!chip->controller)
2415 chip->controller = &chip->hwcontrol;
2418 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2419 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2425 for (i = 0; i < 8; i++)
2426 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2433 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2435 static int nand_flash_detect_onfi(struct mtd_info *mtd,
2436 struct nand_chip *chip,
2439 struct nand_onfi_params *p = &chip->onfi_params;
2443 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2444 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2445 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2448 printk(KERN_INFO "ONFI flash detected\n");
2449 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2450 for (i = 0; i < 3; i++) {
2451 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2452 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2453 le16_to_cpu(p->crc)) {
2454 printk(KERN_INFO "ONFI param page %d valid\n", i);
2463 val = le16_to_cpu(p->revision);
2465 chip->onfi_version = 23;
2466 else if (val & (1 << 4))
2467 chip->onfi_version = 22;
2468 else if (val & (1 << 3))
2469 chip->onfi_version = 21;
2470 else if (val & (1 << 2))
2471 chip->onfi_version = 20;
2472 else if (val & (1 << 1))
2473 chip->onfi_version = 10;
2475 chip->onfi_version = 0;
2477 if (!chip->onfi_version) {
2478 printk(KERN_INFO "%s: unsupported ONFI "
2479 "version: %d\n", __func__, val);
2484 mtd->name = p->model;
2486 mtd->writesize = le32_to_cpu(p->byte_per_page);
2487 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2488 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2489 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2491 if (le16_to_cpu(p->features) & 1)
2492 *busw = NAND_BUSWIDTH_16;
2497 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2498 struct nand_chip *chip,
2505 static void nand_flash_detect_non_onfi(struct mtd_info *mtd,
2506 struct nand_chip *chip,
2507 const struct nand_flash_dev *type,
2510 /* Newer devices have all the information in additional id bytes */
2511 if (!type->pagesize) {
2513 /* The 3rd id byte holds MLC / multichip data */
2514 chip->cellinfo = chip->read_byte(mtd);
2515 /* The 4th id byte is the important one */
2516 extid = chip->read_byte(mtd);
2518 mtd->writesize = 1024 << (extid & 0x3);
2521 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2523 /* Calc blocksize. Blocksize is multiples of 64KiB */
2524 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2526 /* Get buswidth information */
2527 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2531 * Old devices have chip data hardcoded in the device id table
2533 mtd->erasesize = type->erasesize;
2534 mtd->writesize = type->pagesize;
2535 mtd->oobsize = mtd->writesize / 32;
2536 *busw = type->options & NAND_BUSWIDTH_16;
2541 * Get the flash and manufacturer id and lookup if the type is supported
2543 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2544 struct nand_chip *chip,
2546 int *maf_id, int *dev_id,
2547 const struct nand_flash_dev *type)
2550 int tmp_id, tmp_manf;
2552 /* Select the device */
2553 chip->select_chip(mtd, 0);
2556 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2559 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2561 /* Send the command for reading device ID */
2562 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2564 /* Read manufacturer and device IDs */
2565 *maf_id = chip->read_byte(mtd);
2566 *dev_id = chip->read_byte(mtd);
2568 /* Try again to make sure, as some systems the bus-hold or other
2569 * interface concerns can cause random data which looks like a
2570 * possibly credible NAND flash to appear. If the two results do
2571 * not match, ignore the device completely.
2574 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2576 /* Read manufacturer and device IDs */
2578 tmp_manf = chip->read_byte(mtd);
2579 tmp_id = chip->read_byte(mtd);
2581 if (tmp_manf != *maf_id || tmp_id != *dev_id) {
2582 printk(KERN_INFO "%s: second ID read did not match "
2583 "%02x,%02x against %02x,%02x\n", __func__,
2584 *maf_id, *dev_id, tmp_manf, tmp_id);
2585 return ERR_PTR(-ENODEV);
2589 type = nand_flash_ids;
2591 for (; type->name != NULL; type++)
2592 if (*dev_id == type->id)
2596 /* supress warning if there is no nand */
2597 if (*maf_id != 0x00 && *maf_id != 0xff &&
2598 *dev_id != 0x00 && *dev_id != 0xff)
2599 printk(KERN_INFO "%s: unknown NAND device: "
2600 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2601 __func__, *maf_id, *dev_id);
2602 return ERR_PTR(-ENODEV);
2606 mtd->name = type->name;
2608 chip->chipsize = (uint64_t)type->chipsize << 20;
2609 chip->onfi_version = 0;
2611 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2613 nand_flash_detect_non_onfi(mtd, chip, type, &busw);
2615 /* Get chip options, preserve non chip based options */
2616 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2617 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2620 * Set chip as a default. Board drivers can override it, if necessary
2622 chip->options |= NAND_NO_AUTOINCR;
2624 /* Try to identify manufacturer */
2625 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2626 if (nand_manuf_ids[maf_idx].id == *maf_id)
2631 * Check, if buswidth is correct. Hardware drivers should set
2634 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2635 printk(KERN_INFO "NAND device: Manufacturer ID:"
2636 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2637 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2638 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2639 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2641 return ERR_PTR(-EINVAL);
2644 /* Calculate the address shift from the page size */
2645 chip->page_shift = ffs(mtd->writesize) - 1;
2646 /* Convert chipsize to number of pages per chip -1. */
2647 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2649 chip->bbt_erase_shift = chip->phys_erase_shift =
2650 ffs(mtd->erasesize) - 1;
2651 if (chip->chipsize & 0xffffffff)
2652 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2654 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2656 /* Set the bad block position */
2657 chip->badblockpos = mtd->writesize > 512 ?
2658 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2660 /* Check if chip is a not a samsung device. Do not clear the
2661 * options for chips which are not having an extended id.
2663 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2664 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2666 /* Check for AND chips with 4 page planes */
2667 if (chip->options & NAND_4PAGE_ARRAY)
2668 chip->erase_cmd = multi_erase_cmd;
2670 chip->erase_cmd = single_erase_cmd;
2672 /* Do not replace user supplied command function ! */
2673 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2674 chip->cmdfunc = nand_command_lp;
2676 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2677 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
2678 nand_manuf_ids[maf_idx].name, type->name);
2684 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2685 * @mtd: MTD device structure
2686 * @maxchips: Number of chips to scan for
2687 * @table: Alternative NAND ID table
2689 * This is the first phase of the normal nand_scan() function. It
2690 * reads the flash ID and sets up MTD fields accordingly.
2692 * The mtd->owner field must be set to the module of the caller.
2694 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2695 const struct nand_flash_dev *table)
2697 int i, busw, nand_maf_id, nand_dev_id;
2698 struct nand_chip *chip = mtd->priv;
2699 const struct nand_flash_dev *type;
2701 /* Get buswidth to select the correct functions */
2702 busw = chip->options & NAND_BUSWIDTH_16;
2703 /* Set the default functions */
2704 nand_set_defaults(chip, busw);
2706 /* Read the flash type */
2707 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, &nand_dev_id, table);
2710 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2711 printk(KERN_WARNING "No NAND device found!!!\n");
2713 chip->select_chip(mtd, -1);
2714 return PTR_ERR(type);
2717 /* Check for a chip array */
2718 for (i = 1; i < maxchips; i++) {
2719 chip->select_chip(mtd, i);
2720 /* See comment in nand_get_flash_type for reset */
2721 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2722 /* Send the command for reading device ID */
2723 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2724 /* Read manufacturer and device IDs */
2725 if (nand_maf_id != chip->read_byte(mtd) ||
2726 nand_dev_id != chip->read_byte(mtd))
2731 printk(KERN_INFO "%d NAND chips detected\n", i);
2734 /* Store the number of chips and calc total size for mtd */
2736 mtd->size = i * chip->chipsize;
2743 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2744 * @mtd: MTD device structure
2746 * This is the second phase of the normal nand_scan() function. It
2747 * fills out all the uninitialized function pointers with the defaults
2748 * and scans for a bad block table if appropriate.
2750 int nand_scan_tail(struct mtd_info *mtd)
2753 struct nand_chip *chip = mtd->priv;
2755 if (!(chip->options & NAND_OWN_BUFFERS))
2756 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2760 /* Set the internal oob buffer location, just after the page data */
2761 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2764 * If no default placement scheme is given, select an appropriate one
2766 if (!chip->ecc.layout) {
2767 switch (mtd->oobsize) {
2769 chip->ecc.layout = &nand_oob_8;
2772 chip->ecc.layout = &nand_oob_16;
2775 chip->ecc.layout = &nand_oob_64;
2778 chip->ecc.layout = &nand_oob_128;
2781 printk(KERN_WARNING "No oob scheme defined for "
2782 "oobsize %d\n", mtd->oobsize);
2786 if (!chip->write_page)
2787 chip->write_page = nand_write_page;
2790 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2791 * selected and we have 256 byte pagesize fallback to software ECC
2794 switch (chip->ecc.mode) {
2795 case NAND_ECC_HW_OOB_FIRST:
2796 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2797 if (!chip->ecc.calculate || !chip->ecc.correct ||
2799 printk(KERN_WARNING "No ECC functions supplied, "
2800 "Hardware ECC not possible\n");
2803 if (!chip->ecc.read_page)
2804 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2807 /* Use standard hwecc read page function ? */
2808 if (!chip->ecc.read_page)
2809 chip->ecc.read_page = nand_read_page_hwecc;
2810 if (!chip->ecc.write_page)
2811 chip->ecc.write_page = nand_write_page_hwecc;
2812 if (!chip->ecc.read_page_raw)
2813 chip->ecc.read_page_raw = nand_read_page_raw;
2814 if (!chip->ecc.write_page_raw)
2815 chip->ecc.write_page_raw = nand_write_page_raw;
2816 if (!chip->ecc.read_oob)
2817 chip->ecc.read_oob = nand_read_oob_std;
2818 if (!chip->ecc.write_oob)
2819 chip->ecc.write_oob = nand_write_oob_std;
2821 case NAND_ECC_HW_SYNDROME:
2822 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2823 !chip->ecc.hwctl) &&
2824 (!chip->ecc.read_page ||
2825 chip->ecc.read_page == nand_read_page_hwecc ||
2826 !chip->ecc.write_page ||
2827 chip->ecc.write_page == nand_write_page_hwecc)) {
2828 printk(KERN_WARNING "No ECC functions supplied, "
2829 "Hardware ECC not possible\n");
2832 /* Use standard syndrome read/write page function ? */
2833 if (!chip->ecc.read_page)
2834 chip->ecc.read_page = nand_read_page_syndrome;
2835 if (!chip->ecc.write_page)
2836 chip->ecc.write_page = nand_write_page_syndrome;
2837 if (!chip->ecc.read_page_raw)
2838 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2839 if (!chip->ecc.write_page_raw)
2840 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2841 if (!chip->ecc.read_oob)
2842 chip->ecc.read_oob = nand_read_oob_syndrome;
2843 if (!chip->ecc.write_oob)
2844 chip->ecc.write_oob = nand_write_oob_syndrome;
2846 if (mtd->writesize >= chip->ecc.size)
2848 printk(KERN_WARNING "%d byte HW ECC not possible on "
2849 "%d byte page size, fallback to SW ECC\n",
2850 chip->ecc.size, mtd->writesize);
2851 chip->ecc.mode = NAND_ECC_SOFT;
2854 chip->ecc.calculate = nand_calculate_ecc;
2855 chip->ecc.correct = nand_correct_data;
2856 chip->ecc.read_page = nand_read_page_swecc;
2857 chip->ecc.read_subpage = nand_read_subpage;
2858 chip->ecc.write_page = nand_write_page_swecc;
2859 chip->ecc.read_page_raw = nand_read_page_raw;
2860 chip->ecc.write_page_raw = nand_write_page_raw;
2861 chip->ecc.read_oob = nand_read_oob_std;
2862 chip->ecc.write_oob = nand_write_oob_std;
2863 chip->ecc.size = 256;
2864 chip->ecc.bytes = 3;
2868 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2869 "This is not recommended !!\n");
2870 chip->ecc.read_page = nand_read_page_raw;
2871 chip->ecc.write_page = nand_write_page_raw;
2872 chip->ecc.read_oob = nand_read_oob_std;
2873 chip->ecc.read_page_raw = nand_read_page_raw;
2874 chip->ecc.write_page_raw = nand_write_page_raw;
2875 chip->ecc.write_oob = nand_write_oob_std;
2876 chip->ecc.size = mtd->writesize;
2877 chip->ecc.bytes = 0;
2881 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2887 * The number of bytes available for a client to place data into
2888 * the out of band area
2890 chip->ecc.layout->oobavail = 0;
2891 for (i = 0; chip->ecc.layout->oobfree[i].length
2892 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2893 chip->ecc.layout->oobavail +=
2894 chip->ecc.layout->oobfree[i].length;
2895 mtd->oobavail = chip->ecc.layout->oobavail;
2898 * Set the number of read / write steps for one page depending on ECC
2901 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2902 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2903 printk(KERN_WARNING "Invalid ecc parameters\n");
2906 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2909 * Allow subpage writes up to ecc.steps. Not possible for MLC
2912 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2913 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2914 switch(chip->ecc.steps) {
2916 mtd->subpage_sft = 1;
2921 mtd->subpage_sft = 2;
2925 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2927 /* Initialize state */
2928 chip->state = FL_READY;
2930 /* De-select the device */
2931 chip->select_chip(mtd, -1);
2933 /* Invalidate the pagebuffer reference */
2936 /* Fill in remaining MTD driver data */
2937 mtd->type = MTD_NANDFLASH;
2938 mtd->flags = MTD_CAP_NANDFLASH;
2939 mtd->erase = nand_erase;
2941 mtd->unpoint = NULL;
2942 mtd->read = nand_read;
2943 mtd->write = nand_write;
2944 mtd->read_oob = nand_read_oob;
2945 mtd->write_oob = nand_write_oob;
2946 mtd->sync = nand_sync;
2949 mtd->block_isbad = nand_block_isbad;
2950 mtd->block_markbad = nand_block_markbad;
2952 /* propagate ecc.layout to mtd_info */
2953 mtd->ecclayout = chip->ecc.layout;
2955 /* Check, if we should skip the bad block table scan */
2956 if (chip->options & NAND_SKIP_BBTSCAN)
2957 chip->options |= NAND_BBT_SCANNED;
2963 * nand_scan - [NAND Interface] Scan for the NAND device
2964 * @mtd: MTD device structure
2965 * @maxchips: Number of chips to scan for
2967 * This fills out all the uninitialized function pointers
2968 * with the defaults.
2969 * The flash ID is read and the mtd/chip structures are
2970 * filled with the appropriate values.
2971 * The mtd->owner field must be set to the module of the caller
2974 int nand_scan(struct mtd_info *mtd, int maxchips)
2978 ret = nand_scan_ident(mtd, maxchips, NULL);
2980 ret = nand_scan_tail(mtd);
2985 * nand_release - [NAND Interface] Free resources held by the NAND device
2986 * @mtd: MTD device structure
2988 void nand_release(struct mtd_info *mtd)
2990 struct nand_chip *chip = mtd->priv;
2992 #ifdef CONFIG_MTD_PARTITIONS
2993 /* Deregister partitions */
2994 del_mtd_partitions(mtd);
2997 /* Free bad block table memory */
2999 if (!(chip->options & NAND_OWN_BUFFERS))
3000 kfree(chip->buffers);