5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/err.h>
57 #include <linux/compat.h>
58 #include <linux/mtd/mtd.h>
59 #include <linux/mtd/nand.h>
60 #include <linux/mtd/nand_ecc.h>
61 #include <linux/mtd/nand_bch.h>
62 #ifdef CONFIG_MTD_PARTITIONS
63 #include <linux/mtd/partitions.h>
66 #include <asm/errno.h>
69 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
70 * a flash. NAND flash is initialized prior to interrupts so standard timers
71 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
72 * which is greater than (max NAND reset time / NAND status read time).
73 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
75 #ifndef CONFIG_SYS_NAND_RESET_CNT
76 #define CONFIG_SYS_NAND_RESET_CNT 200000
79 static bool is_module_text_address(unsigned long addr) {return 0;}
82 /* Define default oob placement schemes for large and small page devices */
83 static struct nand_ecclayout nand_oob_8 = {
93 static struct nand_ecclayout nand_oob_16 = {
95 .eccpos = {0, 1, 2, 3, 6, 7},
101 static struct nand_ecclayout nand_oob_64 = {
104 40, 41, 42, 43, 44, 45, 46, 47,
105 48, 49, 50, 51, 52, 53, 54, 55,
106 56, 57, 58, 59, 60, 61, 62, 63},
112 static struct nand_ecclayout nand_oob_128 = {
115 80, 81, 82, 83, 84, 85, 86, 87,
116 88, 89, 90, 91, 92, 93, 94, 95,
117 96, 97, 98, 99, 100, 101, 102, 103,
118 104, 105, 106, 107, 108, 109, 110, 111,
119 112, 113, 114, 115, 116, 117, 118, 119,
120 120, 121, 122, 123, 124, 125, 126, 127},
126 static int nand_get_device(struct mtd_info *mtd, int new_state);
128 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
129 struct mtd_oob_ops *ops);
132 * For devices which display every fart in the system on a separate LED. Is
133 * compiled away when LED support is disabled.
135 DEFINE_LED_TRIGGER(nand_led_trigger);
137 static int check_offs_len(struct mtd_info *mtd,
138 loff_t ofs, uint64_t len)
140 struct nand_chip *chip = mtd->priv;
143 /* Start address must align on block boundary */
144 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
145 pr_debug("%s: unaligned address\n", __func__);
149 /* Length must align on block boundary */
150 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
151 pr_debug("%s: length not block aligned\n", __func__);
159 * nand_release_device - [GENERIC] release chip
160 * @mtd: MTD device structure
162 * Release chip lock and wake up anyone waiting on the device.
164 static void nand_release_device(struct mtd_info *mtd)
166 struct nand_chip *chip = mtd->priv;
169 /* Release the controller and the chip */
170 spin_lock(&chip->controller->lock);
171 chip->controller->active = NULL;
172 chip->state = FL_READY;
173 wake_up(&chip->controller->wq);
174 spin_unlock(&chip->controller->lock);
176 /* De-select the NAND device */
177 chip->select_chip(mtd, -1);
182 * nand_read_byte - [DEFAULT] read one byte from the chip
183 * @mtd: MTD device structure
185 * Default read function for 8bit buswidth
188 static uint8_t nand_read_byte(struct mtd_info *mtd)
190 uint8_t nand_read_byte(struct mtd_info *mtd)
193 struct nand_chip *chip = mtd->priv;
194 return readb(chip->IO_ADDR_R);
198 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
199 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
200 * @mtd: MTD device structure
202 * Default read function for 16bit buswidth with endianness conversion.
205 static uint8_t nand_read_byte16(struct mtd_info *mtd)
207 struct nand_chip *chip = mtd->priv;
208 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
212 * nand_read_word - [DEFAULT] read one word from the chip
213 * @mtd: MTD device structure
215 * Default read function for 16bit buswidth without endianness conversion.
217 static u16 nand_read_word(struct mtd_info *mtd)
219 struct nand_chip *chip = mtd->priv;
220 return readw(chip->IO_ADDR_R);
224 * nand_select_chip - [DEFAULT] control CE line
225 * @mtd: MTD device structure
226 * @chipnr: chipnumber to select, -1 for deselect
228 * Default select function for 1 chip devices.
230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
232 struct nand_chip *chip = mtd->priv;
236 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
247 * nand_write_byte - [DEFAULT] write single byte to chip
248 * @mtd: MTD device structure
249 * @byte: value to write
251 * Default function to write a byte to I/O[7:0]
253 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
255 struct nand_chip *chip = mtd->priv;
257 chip->write_buf(mtd, &byte, 1);
261 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
262 * @mtd: MTD device structure
263 * @byte: value to write
265 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
267 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
269 struct nand_chip *chip = mtd->priv;
270 uint16_t word = byte;
273 * It's not entirely clear what should happen to I/O[15:8] when writing
274 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
276 * When the host supports a 16-bit bus width, only data is
277 * transferred at the 16-bit width. All address and command line
278 * transfers shall use only the lower 8-bits of the data bus. During
279 * command transfers, the host may place any value on the upper
280 * 8-bits of the data bus. During address transfers, the host shall
281 * set the upper 8-bits of the data bus to 00h.
283 * One user of the write_byte callback is nand_onfi_set_features. The
284 * four parameters are specified to be written to I/O[7:0], but this is
285 * neither an address nor a command transfer. Let's assume a 0 on the
286 * upper I/O lines is OK.
288 chip->write_buf(mtd, (uint8_t *)&word, 2);
291 #if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN)
292 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
296 for (i = 0; i < len; i++)
297 writeb(buf[i], addr);
299 static void ioread8_rep(void *addr, uint8_t *buf, int len)
303 for (i = 0; i < len; i++)
304 buf[i] = readb(addr);
307 static void ioread16_rep(void *addr, void *buf, int len)
310 u16 *p = (u16 *) buf;
313 for (i = 0; i < len; i++)
317 static void iowrite16_rep(void *addr, void *buf, int len)
320 u16 *p = (u16 *) buf;
323 for (i = 0; i < len; i++)
329 * nand_write_buf - [DEFAULT] write buffer to chip
330 * @mtd: MTD device structure
332 * @len: number of bytes to write
334 * Default write function for 8bit buswidth.
337 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
339 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
342 struct nand_chip *chip = mtd->priv;
344 iowrite8_rep(chip->IO_ADDR_W, buf, len);
348 * nand_read_buf - [DEFAULT] read chip data into buffer
349 * @mtd: MTD device structure
350 * @buf: buffer to store date
351 * @len: number of bytes to read
353 * Default read function for 8bit buswidth.
356 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
358 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
361 struct nand_chip *chip = mtd->priv;
363 ioread8_rep(chip->IO_ADDR_R, buf, len);
367 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
369 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
370 * @mtd: MTD device structure
371 * @buf: buffer containing the data to compare
372 * @len: number of bytes to compare
374 * Default verify function for 8bit buswidth.
376 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
379 struct nand_chip *chip = mtd->priv;
381 for (i = 0; i < len; i++)
382 if (buf[i] != readb(chip->IO_ADDR_R))
388 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
389 * @mtd: MTD device structure
390 * @buf: buffer containing the data to compare
391 * @len: number of bytes to compare
393 * Default verify function for 16bit buswidth.
395 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
398 struct nand_chip *chip = mtd->priv;
399 u16 *p = (u16 *) buf;
402 for (i = 0; i < len; i++)
403 if (p[i] != readw(chip->IO_ADDR_R))
412 * nand_write_buf16 - [DEFAULT] write buffer to chip
413 * @mtd: MTD device structure
415 * @len: number of bytes to write
417 * Default write function for 16bit buswidth.
420 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
422 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
425 struct nand_chip *chip = mtd->priv;
426 u16 *p = (u16 *) buf;
428 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
432 * nand_read_buf16 - [DEFAULT] read chip data into buffer
433 * @mtd: MTD device structure
434 * @buf: buffer to store date
435 * @len: number of bytes to read
437 * Default read function for 16bit buswidth.
440 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
442 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
445 struct nand_chip *chip = mtd->priv;
446 u16 *p = (u16 *) buf;
448 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
452 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
453 * @mtd: MTD device structure
454 * @ofs: offset from device start
455 * @getchip: 0, if the chip is already selected
457 * Check, if the block is bad.
459 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
461 int page, chipnr, res = 0, i = 0;
462 struct nand_chip *chip = mtd->priv;
465 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
466 ofs += mtd->erasesize - mtd->writesize;
468 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
471 chipnr = (int)(ofs >> chip->chip_shift);
473 nand_get_device(mtd, FL_READING);
475 /* Select the NAND device */
476 chip->select_chip(mtd, chipnr);
480 if (chip->options & NAND_BUSWIDTH_16) {
481 chip->cmdfunc(mtd, NAND_CMD_READOOB,
482 chip->badblockpos & 0xFE, page);
483 bad = cpu_to_le16(chip->read_word(mtd));
484 if (chip->badblockpos & 0x1)
489 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
491 bad = chip->read_byte(mtd);
494 if (likely(chip->badblockbits == 8))
497 res = hweight8(bad) < chip->badblockbits;
498 ofs += mtd->writesize;
499 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
501 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
504 chip->select_chip(mtd, -1);
505 nand_release_device(mtd);
512 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
513 * @mtd: MTD device structure
514 * @ofs: offset from device start
516 * This is the default implementation, which can be overridden by a hardware
517 * specific driver. It provides the details for writing a bad block marker to a
520 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
522 struct nand_chip *chip = mtd->priv;
523 struct mtd_oob_ops ops;
524 uint8_t buf[2] = { 0, 0 };
525 int ret = 0, res, i = 0;
529 ops.ooboffs = chip->badblockpos;
530 if (chip->options & NAND_BUSWIDTH_16) {
531 ops.ooboffs &= ~0x01;
532 ops.len = ops.ooblen = 2;
534 ops.len = ops.ooblen = 1;
536 ops.mode = MTD_OPS_PLACE_OOB;
538 /* Write to first/last page(s) if necessary */
539 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
540 ofs += mtd->erasesize - mtd->writesize;
542 res = nand_do_write_oob(mtd, ofs, &ops);
547 ofs += mtd->writesize;
548 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
554 * nand_block_markbad_lowlevel - mark a block bad
555 * @mtd: MTD device structure
556 * @ofs: offset from device start
558 * This function performs the generic NAND bad block marking steps (i.e., bad
559 * block table(s) and/or marker(s)). We only allow the hardware driver to
560 * specify how to write bad block markers to OOB (chip->block_markbad).
562 * We try operations in the following order:
563 * (1) erase the affected block, to allow OOB marker to be written cleanly
564 * (2) write bad block marker to OOB area of affected block (unless flag
565 * NAND_BBT_NO_OOB_BBM is present)
567 * Note that we retain the first error encountered in (2) or (3), finish the
568 * procedures, and dump the error in the end.
570 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
572 struct nand_chip *chip = mtd->priv;
575 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
576 struct erase_info einfo;
578 /* Attempt erase before marking OOB */
579 memset(&einfo, 0, sizeof(einfo));
582 einfo.len = 1ULL << chip->phys_erase_shift;
583 nand_erase_nand(mtd, &einfo, 0);
585 /* Write bad block marker to OOB */
586 nand_get_device(mtd, FL_WRITING);
587 ret = chip->block_markbad(mtd, ofs);
588 nand_release_device(mtd);
591 /* Mark block bad in BBT */
593 res = nand_markbad_bbt(mtd, ofs);
599 mtd->ecc_stats.badblocks++;
605 * nand_check_wp - [GENERIC] check if the chip is write protected
606 * @mtd: MTD device structure
608 * Check, if the device is write protected. The function expects, that the
609 * device is already selected.
611 static int nand_check_wp(struct mtd_info *mtd)
613 struct nand_chip *chip = mtd->priv;
615 /* Broken xD cards report WP despite being writable */
616 if (chip->options & NAND_BROKEN_XD)
619 /* Check the WP bit */
620 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
621 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
625 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
626 * @mtd: MTD device structure
627 * @ofs: offset from device start
628 * @getchip: 0, if the chip is already selected
629 * @allowbbt: 1, if its allowed to access the bbt area
631 * Check, if the block is bad. Either by reading the bad block table or
632 * calling of the scan function.
634 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
637 struct nand_chip *chip = mtd->priv;
640 return chip->block_bad(mtd, ofs, getchip);
642 /* Return info from the table */
643 return nand_isbad_bbt(mtd, ofs, allowbbt);
648 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
649 * @mtd: MTD device structure
652 * Helper function for nand_wait_ready used when needing to wait in interrupt
655 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
657 struct nand_chip *chip = mtd->priv;
660 /* Wait for the device to get ready */
661 for (i = 0; i < timeo; i++) {
662 if (chip->dev_ready(mtd))
664 touch_softlockup_watchdog();
670 /* Wait for the ready pin, after a command. The timeout is caught later. */
671 void nand_wait_ready(struct mtd_info *mtd)
673 struct nand_chip *chip = mtd->priv;
675 unsigned long timeo = jiffies + msecs_to_jiffies(20);
678 if (in_interrupt() || oops_in_progress)
679 return panic_nand_wait_ready(mtd, 400);
681 led_trigger_event(nand_led_trigger, LED_FULL);
682 /* Wait until command is processed or timeout occurs */
684 if (chip->dev_ready(mtd))
686 touch_softlockup_watchdog();
687 } while (time_before(jiffies, timeo));
688 led_trigger_event(nand_led_trigger, LED_OFF);
690 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
693 time_start = get_timer(0);
694 /* Wait until command is processed or timeout occurs */
695 while (get_timer(time_start) < timeo) {
697 if (chip->dev_ready(mtd))
702 EXPORT_SYMBOL_GPL(nand_wait_ready);
705 * nand_command - [DEFAULT] Send command to NAND device
706 * @mtd: MTD device structure
707 * @command: the command to be sent
708 * @column: the column address for this command, -1 if none
709 * @page_addr: the page address for this command, -1 if none
711 * Send command to NAND device. This function is used for small page devices
712 * (512 Bytes per page).
714 static void nand_command(struct mtd_info *mtd, unsigned int command,
715 int column, int page_addr)
717 register struct nand_chip *chip = mtd->priv;
718 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
719 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
721 /* Write out the command to the device */
722 if (command == NAND_CMD_SEQIN) {
725 if (column >= mtd->writesize) {
727 column -= mtd->writesize;
728 readcmd = NAND_CMD_READOOB;
729 } else if (column < 256) {
730 /* First 256 bytes --> READ0 */
731 readcmd = NAND_CMD_READ0;
734 readcmd = NAND_CMD_READ1;
736 chip->cmd_ctrl(mtd, readcmd, ctrl);
737 ctrl &= ~NAND_CTRL_CHANGE;
739 chip->cmd_ctrl(mtd, command, ctrl);
741 /* Address cycle, when necessary */
742 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
743 /* Serially input address */
745 /* Adjust columns for 16 bit buswidth */
746 if (chip->options & NAND_BUSWIDTH_16 &&
747 !nand_opcode_8bits(command))
749 chip->cmd_ctrl(mtd, column, ctrl);
750 ctrl &= ~NAND_CTRL_CHANGE;
752 if (page_addr != -1) {
753 chip->cmd_ctrl(mtd, page_addr, ctrl);
754 ctrl &= ~NAND_CTRL_CHANGE;
755 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
756 /* One more address cycle for devices > 32MiB */
757 if (chip->chipsize > (32 << 20))
758 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
760 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
763 * Program and erase have their own busy handlers status and sequential
768 case NAND_CMD_PAGEPROG:
769 case NAND_CMD_ERASE1:
770 case NAND_CMD_ERASE2:
772 case NAND_CMD_STATUS:
778 udelay(chip->chip_delay);
779 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
780 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
782 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
783 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
787 /* This applies to read commands */
790 * If we don't have access to the busy pin, we apply the given
793 if (!chip->dev_ready) {
794 udelay(chip->chip_delay);
799 * Apply this short delay always to ensure that we do wait tWB in
800 * any case on any machine.
804 nand_wait_ready(mtd);
808 * nand_command_lp - [DEFAULT] Send command to NAND large page device
809 * @mtd: MTD device structure
810 * @command: the command to be sent
811 * @column: the column address for this command, -1 if none
812 * @page_addr: the page address for this command, -1 if none
814 * Send command to NAND device. This is the version for the new large page
815 * devices. We don't have the separate regions as we have in the small page
816 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
818 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
819 int column, int page_addr)
821 register struct nand_chip *chip = mtd->priv;
822 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
824 /* Emulate NAND_CMD_READOOB */
825 if (command == NAND_CMD_READOOB) {
826 column += mtd->writesize;
827 command = NAND_CMD_READ0;
830 /* Command latch cycle */
831 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
833 if (column != -1 || page_addr != -1) {
834 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
836 /* Serially input address */
838 /* Adjust columns for 16 bit buswidth */
839 if (chip->options & NAND_BUSWIDTH_16 &&
840 !nand_opcode_8bits(command))
842 chip->cmd_ctrl(mtd, column, ctrl);
843 ctrl &= ~NAND_CTRL_CHANGE;
844 chip->cmd_ctrl(mtd, column >> 8, ctrl);
846 if (page_addr != -1) {
847 chip->cmd_ctrl(mtd, page_addr, ctrl);
848 chip->cmd_ctrl(mtd, page_addr >> 8,
849 NAND_NCE | NAND_ALE);
850 /* One more address cycle for devices > 128MiB */
851 if (chip->chipsize > (128 << 20))
852 chip->cmd_ctrl(mtd, page_addr >> 16,
853 NAND_NCE | NAND_ALE);
856 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
859 * Program and erase have their own busy handlers status, sequential
860 * in, and deplete1 need no delay.
864 case NAND_CMD_CACHEDPROG:
865 case NAND_CMD_PAGEPROG:
866 case NAND_CMD_ERASE1:
867 case NAND_CMD_ERASE2:
870 case NAND_CMD_STATUS:
876 udelay(chip->chip_delay);
877 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
878 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
879 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
880 NAND_NCE | NAND_CTRL_CHANGE);
881 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
885 case NAND_CMD_RNDOUT:
886 /* No ready / busy check necessary */
887 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
888 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
889 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
890 NAND_NCE | NAND_CTRL_CHANGE);
894 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
895 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
896 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
897 NAND_NCE | NAND_CTRL_CHANGE);
899 /* This applies to read commands */
902 * If we don't have access to the busy pin, we apply the given
905 if (!chip->dev_ready) {
906 udelay(chip->chip_delay);
912 * Apply this short delay always to ensure that we do wait tWB in
913 * any case on any machine.
917 nand_wait_ready(mtd);
921 * panic_nand_get_device - [GENERIC] Get chip for selected access
922 * @chip: the nand chip descriptor
923 * @mtd: MTD device structure
924 * @new_state: the state which is requested
926 * Used when in panic, no locks are taken.
928 static void panic_nand_get_device(struct nand_chip *chip,
929 struct mtd_info *mtd, int new_state)
931 /* Hardware controller shared among independent devices */
932 chip->controller->active = chip;
933 chip->state = new_state;
937 * nand_get_device - [GENERIC] Get chip for selected access
938 * @mtd: MTD device structure
939 * @new_state: the state which is requested
941 * Get the device and lock it for exclusive access
944 nand_get_device(struct mtd_info *mtd, int new_state)
946 struct nand_chip *chip = mtd->priv;
948 spinlock_t *lock = &chip->controller->lock;
949 wait_queue_head_t *wq = &chip->controller->wq;
950 DECLARE_WAITQUEUE(wait, current);
954 /* Hardware controller shared among independent devices */
955 if (!chip->controller->active)
956 chip->controller->active = chip;
958 if (chip->controller->active == chip && chip->state == FL_READY) {
959 chip->state = new_state;
963 if (new_state == FL_PM_SUSPENDED) {
964 if (chip->controller->active->state == FL_PM_SUSPENDED) {
965 chip->state = FL_PM_SUSPENDED;
970 set_current_state(TASK_UNINTERRUPTIBLE);
971 add_wait_queue(wq, &wait);
974 remove_wait_queue(wq, &wait);
977 chip->state = new_state;
983 * panic_nand_wait - [GENERIC] wait until the command is done
984 * @mtd: MTD device structure
985 * @chip: NAND chip structure
988 * Wait for command done. This is a helper function for nand_wait used when
989 * we are in interrupt context. May happen when in panic and trying to write
990 * an oops through mtdoops.
992 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
996 for (i = 0; i < timeo; i++) {
997 if (chip->dev_ready) {
998 if (chip->dev_ready(mtd))
1001 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1009 * nand_wait - [DEFAULT] wait until the command is done
1010 * @mtd: MTD device structure
1011 * @chip: NAND chip structure
1013 * Wait for command done. This applies to erase and program only. Erase can
1014 * take up to 400ms and program up to 20ms according to general NAND and
1017 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1020 int status, state = chip->state;
1021 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1023 led_trigger_event(nand_led_trigger, LED_FULL);
1026 * Apply this short delay always to ensure that we do wait tWB in any
1027 * case on any machine.
1031 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1034 if (in_interrupt() || oops_in_progress)
1035 panic_nand_wait(mtd, chip, timeo);
1037 timeo = jiffies + msecs_to_jiffies(timeo);
1038 while (time_before(jiffies, timeo)) {
1039 if (chip->dev_ready) {
1040 if (chip->dev_ready(mtd))
1043 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1050 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
1053 time_start = get_timer(0);
1054 while (get_timer(time_start) < timer) {
1055 if (chip->dev_ready) {
1056 if (chip->dev_ready(mtd))
1059 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1064 #ifdef PPCHAMELON_NAND_TIMER_HACK
1065 time_start = get_timer(0);
1066 while (get_timer(time_start) < 10)
1068 #endif /* PPCHAMELON_NAND_TIMER_HACK */
1069 led_trigger_event(nand_led_trigger, LED_OFF);
1071 status = (int)chip->read_byte(mtd);
1072 /* This can happen if in case of timeout or buggy dev_ready */
1073 WARN_ON(!(status & NAND_STATUS_READY));
1079 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1081 * @ofs: offset to start unlock from
1082 * @len: length to unlock
1083 * @invert: when = 0, unlock the range of blocks within the lower and
1084 * upper boundary address
1085 * when = 1, unlock the range of blocks outside the boundaries
1086 * of the lower and upper boundary address
1088 * Returs unlock status.
1090 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1091 uint64_t len, int invert)
1095 struct nand_chip *chip = mtd->priv;
1097 /* Submit address of first page to unlock */
1098 page = ofs >> chip->page_shift;
1099 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1101 /* Submit address of last page to unlock */
1102 page = (ofs + len) >> chip->page_shift;
1103 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1104 (page | invert) & chip->pagemask);
1106 /* Call wait ready function */
1107 status = chip->waitfunc(mtd, chip);
1108 /* See if device thinks it succeeded */
1109 if (status & NAND_STATUS_FAIL) {
1110 pr_debug("%s: error status = 0x%08x\n",
1119 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1121 * @ofs: offset to start unlock from
1122 * @len: length to unlock
1124 * Returns unlock status.
1126 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1130 struct nand_chip *chip = mtd->priv;
1132 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1133 __func__, (unsigned long long)ofs, len);
1135 if (check_offs_len(mtd, ofs, len))
1138 /* Align to last block address if size addresses end of the device */
1139 if (ofs + len == mtd->size)
1140 len -= mtd->erasesize;
1142 nand_get_device(mtd, FL_UNLOCKING);
1144 /* Shift to get chip number */
1145 chipnr = ofs >> chip->chip_shift;
1147 chip->select_chip(mtd, chipnr);
1149 /* Check, if it is write protected */
1150 if (nand_check_wp(mtd)) {
1151 pr_debug("%s: device is write protected!\n",
1157 ret = __nand_unlock(mtd, ofs, len, 0);
1160 chip->select_chip(mtd, -1);
1161 nand_release_device(mtd);
1165 EXPORT_SYMBOL(nand_unlock);
1168 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1170 * @ofs: offset to start unlock from
1171 * @len: length to unlock
1173 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1174 * have this feature, but it allows only to lock all blocks, not for specified
1175 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1178 * Returns lock status.
1180 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1183 int chipnr, status, page;
1184 struct nand_chip *chip = mtd->priv;
1186 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1187 __func__, (unsigned long long)ofs, len);
1189 if (check_offs_len(mtd, ofs, len))
1192 nand_get_device(mtd, FL_LOCKING);
1194 /* Shift to get chip number */
1195 chipnr = ofs >> chip->chip_shift;
1197 chip->select_chip(mtd, chipnr);
1199 /* Check, if it is write protected */
1200 if (nand_check_wp(mtd)) {
1201 pr_debug("%s: device is write protected!\n",
1203 status = MTD_ERASE_FAILED;
1208 /* Submit address of first page to lock */
1209 page = ofs >> chip->page_shift;
1210 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1212 /* Call wait ready function */
1213 status = chip->waitfunc(mtd, chip);
1214 /* See if device thinks it succeeded */
1215 if (status & NAND_STATUS_FAIL) {
1216 pr_debug("%s: error status = 0x%08x\n",
1222 ret = __nand_unlock(mtd, ofs, len, 0x1);
1225 chip->select_chip(mtd, -1);
1226 nand_release_device(mtd);
1230 EXPORT_SYMBOL(nand_lock);
1234 * nand_read_page_raw - [INTERN] read raw page data without ecc
1235 * @mtd: mtd info structure
1236 * @chip: nand chip info structure
1237 * @buf: buffer to store read data
1238 * @oob_required: caller requires OOB data read to chip->oob_poi
1239 * @page: page number to read
1241 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1243 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1244 uint8_t *buf, int oob_required, int page)
1246 chip->read_buf(mtd, buf, mtd->writesize);
1248 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1253 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1254 * @mtd: mtd info structure
1255 * @chip: nand chip info structure
1256 * @buf: buffer to store read data
1257 * @oob_required: caller requires OOB data read to chip->oob_poi
1258 * @page: page number to read
1260 * We need a special oob layout and handling even when OOB isn't used.
1262 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1263 struct nand_chip *chip, uint8_t *buf,
1264 int oob_required, int page)
1266 int eccsize = chip->ecc.size;
1267 int eccbytes = chip->ecc.bytes;
1268 uint8_t *oob = chip->oob_poi;
1271 for (steps = chip->ecc.steps; steps > 0; steps--) {
1272 chip->read_buf(mtd, buf, eccsize);
1275 if (chip->ecc.prepad) {
1276 chip->read_buf(mtd, oob, chip->ecc.prepad);
1277 oob += chip->ecc.prepad;
1280 chip->read_buf(mtd, oob, eccbytes);
1283 if (chip->ecc.postpad) {
1284 chip->read_buf(mtd, oob, chip->ecc.postpad);
1285 oob += chip->ecc.postpad;
1289 size = mtd->oobsize - (oob - chip->oob_poi);
1291 chip->read_buf(mtd, oob, size);
1297 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1298 * @mtd: mtd info structure
1299 * @chip: nand chip info structure
1300 * @buf: buffer to store read data
1301 * @oob_required: caller requires OOB data read to chip->oob_poi
1302 * @page: page number to read
1304 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1305 uint8_t *buf, int oob_required, int page)
1307 int i, eccsize = chip->ecc.size;
1308 int eccbytes = chip->ecc.bytes;
1309 int eccsteps = chip->ecc.steps;
1311 uint8_t *ecc_calc = chip->buffers->ecccalc;
1312 uint8_t *ecc_code = chip->buffers->ecccode;
1313 uint32_t *eccpos = chip->ecc.layout->eccpos;
1314 unsigned int max_bitflips = 0;
1316 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1318 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1319 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1321 for (i = 0; i < chip->ecc.total; i++)
1322 ecc_code[i] = chip->oob_poi[eccpos[i]];
1324 eccsteps = chip->ecc.steps;
1327 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1330 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1332 mtd->ecc_stats.failed++;
1334 mtd->ecc_stats.corrected += stat;
1335 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1338 return max_bitflips;
1342 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1343 * @mtd: mtd info structure
1344 * @chip: nand chip info structure
1345 * @data_offs: offset of requested data within the page
1346 * @readlen: data length
1347 * @bufpoi: buffer to store read data
1348 * @page: page number to read
1350 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1351 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1354 int start_step, end_step, num_steps;
1355 uint32_t *eccpos = chip->ecc.layout->eccpos;
1357 int data_col_addr, i, gaps = 0;
1358 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1359 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1361 unsigned int max_bitflips = 0;
1363 /* Column address within the page aligned to ECC size (256bytes) */
1364 start_step = data_offs / chip->ecc.size;
1365 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1366 num_steps = end_step - start_step + 1;
1367 index = start_step * chip->ecc.bytes;
1369 /* Data size aligned to ECC ecc.size */
1370 datafrag_len = num_steps * chip->ecc.size;
1371 eccfrag_len = num_steps * chip->ecc.bytes;
1373 data_col_addr = start_step * chip->ecc.size;
1374 /* If we read not a page aligned data */
1375 if (data_col_addr != 0)
1376 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1378 p = bufpoi + data_col_addr;
1379 chip->read_buf(mtd, p, datafrag_len);
1382 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1383 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1386 * The performance is faster if we position offsets according to
1387 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1389 for (i = 0; i < eccfrag_len - 1; i++) {
1390 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1391 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1397 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1398 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1401 * Send the command to read the particular ECC bytes take care
1402 * about buswidth alignment in read_buf.
1404 aligned_pos = eccpos[index] & ~(busw - 1);
1405 aligned_len = eccfrag_len;
1406 if (eccpos[index] & (busw - 1))
1408 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1411 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1412 mtd->writesize + aligned_pos, -1);
1413 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1416 for (i = 0; i < eccfrag_len; i++)
1417 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1419 p = bufpoi + data_col_addr;
1420 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1423 stat = chip->ecc.correct(mtd, p,
1424 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1426 mtd->ecc_stats.failed++;
1428 mtd->ecc_stats.corrected += stat;
1429 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1432 return max_bitflips;
1436 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1437 * @mtd: mtd info structure
1438 * @chip: nand chip info structure
1439 * @buf: buffer to store read data
1440 * @oob_required: caller requires OOB data read to chip->oob_poi
1441 * @page: page number to read
1443 * Not for syndrome calculating ECC controllers which need a special oob layout.
1445 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1446 uint8_t *buf, int oob_required, int page)
1448 int i, eccsize = chip->ecc.size;
1449 int eccbytes = chip->ecc.bytes;
1450 int eccsteps = chip->ecc.steps;
1452 uint8_t *ecc_calc = chip->buffers->ecccalc;
1453 uint8_t *ecc_code = chip->buffers->ecccode;
1454 uint32_t *eccpos = chip->ecc.layout->eccpos;
1455 unsigned int max_bitflips = 0;
1457 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1458 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1459 chip->read_buf(mtd, p, eccsize);
1460 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1462 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1464 for (i = 0; i < chip->ecc.total; i++)
1465 ecc_code[i] = chip->oob_poi[eccpos[i]];
1467 eccsteps = chip->ecc.steps;
1470 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1473 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1475 mtd->ecc_stats.failed++;
1477 mtd->ecc_stats.corrected += stat;
1478 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1481 return max_bitflips;
1485 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1486 * @mtd: mtd info structure
1487 * @chip: nand chip info structure
1488 * @buf: buffer to store read data
1489 * @oob_required: caller requires OOB data read to chip->oob_poi
1490 * @page: page number to read
1492 * Hardware ECC for large page chips, require OOB to be read first. For this
1493 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1494 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1495 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1496 * the data area, by overwriting the NAND manufacturer bad block markings.
1498 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1499 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1501 int i, eccsize = chip->ecc.size;
1502 int eccbytes = chip->ecc.bytes;
1503 int eccsteps = chip->ecc.steps;
1505 uint8_t *ecc_code = chip->buffers->ecccode;
1506 uint32_t *eccpos = chip->ecc.layout->eccpos;
1507 uint8_t *ecc_calc = chip->buffers->ecccalc;
1508 unsigned int max_bitflips = 0;
1510 /* Read the OOB area first */
1511 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1512 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1513 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1515 for (i = 0; i < chip->ecc.total; i++)
1516 ecc_code[i] = chip->oob_poi[eccpos[i]];
1518 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1521 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1522 chip->read_buf(mtd, p, eccsize);
1523 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1525 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1527 mtd->ecc_stats.failed++;
1529 mtd->ecc_stats.corrected += stat;
1530 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1533 return max_bitflips;
1537 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1538 * @mtd: mtd info structure
1539 * @chip: nand chip info structure
1540 * @buf: buffer to store read data
1541 * @oob_required: caller requires OOB data read to chip->oob_poi
1542 * @page: page number to read
1544 * The hw generator calculates the error syndrome automatically. Therefore we
1545 * need a special oob layout and handling.
1547 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1548 uint8_t *buf, int oob_required, int page)
1550 int i, eccsize = chip->ecc.size;
1551 int eccbytes = chip->ecc.bytes;
1552 int eccsteps = chip->ecc.steps;
1554 uint8_t *oob = chip->oob_poi;
1555 unsigned int max_bitflips = 0;
1557 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1560 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1561 chip->read_buf(mtd, p, eccsize);
1563 if (chip->ecc.prepad) {
1564 chip->read_buf(mtd, oob, chip->ecc.prepad);
1565 oob += chip->ecc.prepad;
1568 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1569 chip->read_buf(mtd, oob, eccbytes);
1570 stat = chip->ecc.correct(mtd, p, oob, NULL);
1573 mtd->ecc_stats.failed++;
1575 mtd->ecc_stats.corrected += stat;
1576 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1581 if (chip->ecc.postpad) {
1582 chip->read_buf(mtd, oob, chip->ecc.postpad);
1583 oob += chip->ecc.postpad;
1587 /* Calculate remaining oob bytes */
1588 i = mtd->oobsize - (oob - chip->oob_poi);
1590 chip->read_buf(mtd, oob, i);
1592 return max_bitflips;
1596 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1597 * @chip: nand chip structure
1598 * @oob: oob destination address
1599 * @ops: oob ops structure
1600 * @len: size of oob to transfer
1602 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1603 struct mtd_oob_ops *ops, size_t len)
1605 switch (ops->mode) {
1607 case MTD_OPS_PLACE_OOB:
1609 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1612 case MTD_OPS_AUTO_OOB: {
1613 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1614 uint32_t boffs = 0, roffs = ops->ooboffs;
1617 for (; free->length && len; free++, len -= bytes) {
1618 /* Read request not from offset 0? */
1619 if (unlikely(roffs)) {
1620 if (roffs >= free->length) {
1621 roffs -= free->length;
1624 boffs = free->offset + roffs;
1625 bytes = min_t(size_t, len,
1626 (free->length - roffs));
1629 bytes = min_t(size_t, len, free->length);
1630 boffs = free->offset;
1632 memcpy(oob, chip->oob_poi + boffs, bytes);
1644 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1645 * @mtd: MTD device structure
1646 * @retry_mode: the retry mode to use
1648 * Some vendors supply a special command to shift the Vt threshold, to be used
1649 * when there are too many bitflips in a page (i.e., ECC error). After setting
1650 * a new threshold, the host should retry reading the page.
1652 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1654 struct nand_chip *chip = mtd->priv;
1656 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1658 if (retry_mode >= chip->read_retries)
1661 if (!chip->setup_read_retry)
1664 return chip->setup_read_retry(mtd, retry_mode);
1668 * nand_do_read_ops - [INTERN] Read data with ECC
1669 * @mtd: MTD device structure
1670 * @from: offset to read from
1671 * @ops: oob ops structure
1673 * Internal function. Called with chip held.
1675 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1676 struct mtd_oob_ops *ops)
1678 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1679 struct nand_chip *chip = mtd->priv;
1681 uint32_t readlen = ops->len;
1682 uint32_t oobreadlen = ops->ooblen;
1683 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1684 mtd->oobavail : mtd->oobsize;
1686 uint8_t *bufpoi, *oob, *buf;
1687 unsigned int max_bitflips = 0;
1689 bool ecc_fail = false;
1691 chipnr = (int)(from >> chip->chip_shift);
1692 chip->select_chip(mtd, chipnr);
1694 realpage = (int)(from >> chip->page_shift);
1695 page = realpage & chip->pagemask;
1697 col = (int)(from & (mtd->writesize - 1));
1701 oob_required = oob ? 1 : 0;
1704 unsigned int ecc_failures = mtd->ecc_stats.failed;
1707 bytes = min(mtd->writesize - col, readlen);
1708 aligned = (bytes == mtd->writesize);
1710 /* Is the current page in the buffer? */
1711 if (realpage != chip->pagebuf || oob) {
1712 bufpoi = aligned ? buf : chip->buffers->databuf;
1715 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1718 * Now read the page into the buffer. Absent an error,
1719 * the read methods return max bitflips per ecc step.
1721 if (unlikely(ops->mode == MTD_OPS_RAW))
1722 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1725 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1727 ret = chip->ecc.read_subpage(mtd, chip,
1731 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1732 oob_required, page);
1735 /* Invalidate page cache */
1740 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1742 /* Transfer not aligned data */
1744 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1745 !(mtd->ecc_stats.failed - ecc_failures) &&
1746 (ops->mode != MTD_OPS_RAW)) {
1747 chip->pagebuf = realpage;
1748 chip->pagebuf_bitflips = ret;
1750 /* Invalidate page cache */
1753 memcpy(buf, chip->buffers->databuf + col, bytes);
1756 if (unlikely(oob)) {
1757 int toread = min(oobreadlen, max_oobsize);
1760 oob = nand_transfer_oob(chip,
1762 oobreadlen -= toread;
1766 if (chip->options & NAND_NEED_READRDY) {
1767 /* Apply delay or wait for ready/busy pin */
1768 if (!chip->dev_ready)
1769 udelay(chip->chip_delay);
1771 nand_wait_ready(mtd);
1774 if (mtd->ecc_stats.failed - ecc_failures) {
1775 if (retry_mode + 1 < chip->read_retries) {
1777 ret = nand_setup_read_retry(mtd,
1782 /* Reset failures; retry */
1783 mtd->ecc_stats.failed = ecc_failures;
1786 /* No more retry modes; real failure */
1793 memcpy(buf, chip->buffers->databuf + col, bytes);
1795 max_bitflips = max_t(unsigned int, max_bitflips,
1796 chip->pagebuf_bitflips);
1801 /* Reset to retry mode 0 */
1803 ret = nand_setup_read_retry(mtd, 0);
1812 /* For subsequent reads align to page boundary */
1814 /* Increment page address */
1817 page = realpage & chip->pagemask;
1818 /* Check, if we cross a chip boundary */
1821 chip->select_chip(mtd, -1);
1822 chip->select_chip(mtd, chipnr);
1825 chip->select_chip(mtd, -1);
1827 ops->retlen = ops->len - (size_t) readlen;
1829 ops->oobretlen = ops->ooblen - oobreadlen;
1837 return max_bitflips;
1841 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1842 * @mtd: MTD device structure
1843 * @from: offset to read from
1844 * @len: number of bytes to read
1845 * @retlen: pointer to variable to store the number of read bytes
1846 * @buf: the databuffer to put data
1848 * Get hold of the chip and call nand_do_read.
1850 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1851 size_t *retlen, uint8_t *buf)
1853 struct mtd_oob_ops ops;
1856 nand_get_device(mtd, FL_READING);
1860 ops.mode = MTD_OPS_PLACE_OOB;
1861 ret = nand_do_read_ops(mtd, from, &ops);
1862 *retlen = ops.retlen;
1863 nand_release_device(mtd);
1868 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1869 * @mtd: mtd info structure
1870 * @chip: nand chip info structure
1871 * @page: page number to read
1873 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1876 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1877 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1882 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1884 * @mtd: mtd info structure
1885 * @chip: nand chip info structure
1886 * @page: page number to read
1888 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1891 uint8_t *buf = chip->oob_poi;
1892 int length = mtd->oobsize;
1893 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1894 int eccsize = chip->ecc.size;
1895 uint8_t *bufpoi = buf;
1896 int i, toread, sndrnd = 0, pos;
1898 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1899 for (i = 0; i < chip->ecc.steps; i++) {
1901 pos = eccsize + i * (eccsize + chunk);
1902 if (mtd->writesize > 512)
1903 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1905 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1908 toread = min_t(int, length, chunk);
1909 chip->read_buf(mtd, bufpoi, toread);
1914 chip->read_buf(mtd, bufpoi, length);
1920 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1921 * @mtd: mtd info structure
1922 * @chip: nand chip info structure
1923 * @page: page number to write
1925 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1929 const uint8_t *buf = chip->oob_poi;
1930 int length = mtd->oobsize;
1932 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1933 chip->write_buf(mtd, buf, length);
1934 /* Send command to program the OOB data */
1935 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1937 status = chip->waitfunc(mtd, chip);
1939 return status & NAND_STATUS_FAIL ? -EIO : 0;
1943 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1944 * with syndrome - only for large page flash
1945 * @mtd: mtd info structure
1946 * @chip: nand chip info structure
1947 * @page: page number to write
1949 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1950 struct nand_chip *chip, int page)
1952 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1953 int eccsize = chip->ecc.size, length = mtd->oobsize;
1954 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1955 const uint8_t *bufpoi = chip->oob_poi;
1958 * data-ecc-data-ecc ... ecc-oob
1960 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1962 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1963 pos = steps * (eccsize + chunk);
1968 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1969 for (i = 0; i < steps; i++) {
1971 if (mtd->writesize <= 512) {
1972 uint32_t fill = 0xFFFFFFFF;
1976 int num = min_t(int, len, 4);
1977 chip->write_buf(mtd, (uint8_t *)&fill,
1982 pos = eccsize + i * (eccsize + chunk);
1983 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1987 len = min_t(int, length, chunk);
1988 chip->write_buf(mtd, bufpoi, len);
1993 chip->write_buf(mtd, bufpoi, length);
1995 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1996 status = chip->waitfunc(mtd, chip);
1998 return status & NAND_STATUS_FAIL ? -EIO : 0;
2002 * nand_do_read_oob - [INTERN] NAND read out-of-band
2003 * @mtd: MTD device structure
2004 * @from: offset to read from
2005 * @ops: oob operations description structure
2007 * NAND read out-of-band data from the spare area.
2009 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2010 struct mtd_oob_ops *ops)
2012 int page, realpage, chipnr;
2013 struct nand_chip *chip = mtd->priv;
2014 struct mtd_ecc_stats stats;
2015 int readlen = ops->ooblen;
2017 uint8_t *buf = ops->oobbuf;
2020 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2021 __func__, (unsigned long long)from, readlen);
2023 stats = mtd->ecc_stats;
2025 if (ops->mode == MTD_OPS_AUTO_OOB)
2026 len = chip->ecc.layout->oobavail;
2030 if (unlikely(ops->ooboffs >= len)) {
2031 pr_debug("%s: attempt to start read outside oob\n",
2036 /* Do not allow reads past end of device */
2037 if (unlikely(from >= mtd->size ||
2038 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2039 (from >> chip->page_shift)) * len)) {
2040 pr_debug("%s: attempt to read beyond end of device\n",
2045 chipnr = (int)(from >> chip->chip_shift);
2046 chip->select_chip(mtd, chipnr);
2048 /* Shift to get page */
2049 realpage = (int)(from >> chip->page_shift);
2050 page = realpage & chip->pagemask;
2055 if (ops->mode == MTD_OPS_RAW)
2056 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2058 ret = chip->ecc.read_oob(mtd, chip, page);
2063 len = min(len, readlen);
2064 buf = nand_transfer_oob(chip, buf, ops, len);
2066 if (chip->options & NAND_NEED_READRDY) {
2067 /* Apply delay or wait for ready/busy pin */
2068 if (!chip->dev_ready)
2069 udelay(chip->chip_delay);
2071 nand_wait_ready(mtd);
2078 /* Increment page address */
2081 page = realpage & chip->pagemask;
2082 /* Check, if we cross a chip boundary */
2085 chip->select_chip(mtd, -1);
2086 chip->select_chip(mtd, chipnr);
2089 chip->select_chip(mtd, -1);
2091 ops->oobretlen = ops->ooblen - readlen;
2096 if (mtd->ecc_stats.failed - stats.failed)
2099 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2103 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2104 * @mtd: MTD device structure
2105 * @from: offset to read from
2106 * @ops: oob operation description structure
2108 * NAND read data and/or out-of-band data.
2110 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2111 struct mtd_oob_ops *ops)
2113 int ret = -ENOTSUPP;
2117 /* Do not allow reads past end of device */
2118 if (ops->datbuf && (from + ops->len) > mtd->size) {
2119 pr_debug("%s: attempt to read beyond end of device\n",
2124 nand_get_device(mtd, FL_READING);
2126 switch (ops->mode) {
2127 case MTD_OPS_PLACE_OOB:
2128 case MTD_OPS_AUTO_OOB:
2137 ret = nand_do_read_oob(mtd, from, ops);
2139 ret = nand_do_read_ops(mtd, from, ops);
2142 nand_release_device(mtd);
2148 * nand_write_page_raw - [INTERN] raw page write function
2149 * @mtd: mtd info structure
2150 * @chip: nand chip info structure
2152 * @oob_required: must write chip->oob_poi to OOB
2154 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2156 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2157 const uint8_t *buf, int oob_required)
2159 chip->write_buf(mtd, buf, mtd->writesize);
2161 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2167 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2168 * @mtd: mtd info structure
2169 * @chip: nand chip info structure
2171 * @oob_required: must write chip->oob_poi to OOB
2173 * We need a special oob layout and handling even when ECC isn't checked.
2175 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2176 struct nand_chip *chip,
2177 const uint8_t *buf, int oob_required)
2179 int eccsize = chip->ecc.size;
2180 int eccbytes = chip->ecc.bytes;
2181 uint8_t *oob = chip->oob_poi;
2184 for (steps = chip->ecc.steps; steps > 0; steps--) {
2185 chip->write_buf(mtd, buf, eccsize);
2188 if (chip->ecc.prepad) {
2189 chip->write_buf(mtd, oob, chip->ecc.prepad);
2190 oob += chip->ecc.prepad;
2193 chip->write_buf(mtd, oob, eccbytes);
2196 if (chip->ecc.postpad) {
2197 chip->write_buf(mtd, oob, chip->ecc.postpad);
2198 oob += chip->ecc.postpad;
2202 size = mtd->oobsize - (oob - chip->oob_poi);
2204 chip->write_buf(mtd, oob, size);
2209 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2210 * @mtd: mtd info structure
2211 * @chip: nand chip info structure
2213 * @oob_required: must write chip->oob_poi to OOB
2215 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2216 const uint8_t *buf, int oob_required)
2218 int i, eccsize = chip->ecc.size;
2219 int eccbytes = chip->ecc.bytes;
2220 int eccsteps = chip->ecc.steps;
2221 uint8_t *ecc_calc = chip->buffers->ecccalc;
2222 const uint8_t *p = buf;
2223 uint32_t *eccpos = chip->ecc.layout->eccpos;
2225 /* Software ECC calculation */
2226 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2227 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2229 for (i = 0; i < chip->ecc.total; i++)
2230 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2232 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2236 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2237 * @mtd: mtd info structure
2238 * @chip: nand chip info structure
2240 * @oob_required: must write chip->oob_poi to OOB
2242 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2243 const uint8_t *buf, int oob_required)
2245 int i, eccsize = chip->ecc.size;
2246 int eccbytes = chip->ecc.bytes;
2247 int eccsteps = chip->ecc.steps;
2248 uint8_t *ecc_calc = chip->buffers->ecccalc;
2249 const uint8_t *p = buf;
2250 uint32_t *eccpos = chip->ecc.layout->eccpos;
2252 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2253 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2254 chip->write_buf(mtd, p, eccsize);
2255 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2258 for (i = 0; i < chip->ecc.total; i++)
2259 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2261 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2268 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2269 * @mtd: mtd info structure
2270 * @chip: nand chip info structure
2271 * @offset: column address of subpage within the page
2272 * @data_len: data length
2274 * @oob_required: must write chip->oob_poi to OOB
2276 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2277 struct nand_chip *chip, uint32_t offset,
2278 uint32_t data_len, const uint8_t *buf,
2281 uint8_t *oob_buf = chip->oob_poi;
2282 uint8_t *ecc_calc = chip->buffers->ecccalc;
2283 int ecc_size = chip->ecc.size;
2284 int ecc_bytes = chip->ecc.bytes;
2285 int ecc_steps = chip->ecc.steps;
2286 uint32_t *eccpos = chip->ecc.layout->eccpos;
2287 uint32_t start_step = offset / ecc_size;
2288 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2289 int oob_bytes = mtd->oobsize / ecc_steps;
2292 for (step = 0; step < ecc_steps; step++) {
2293 /* configure controller for WRITE access */
2294 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2296 /* write data (untouched subpages already masked by 0xFF) */
2297 chip->write_buf(mtd, buf, ecc_size);
2299 /* mask ECC of un-touched subpages by padding 0xFF */
2300 if ((step < start_step) || (step > end_step))
2301 memset(ecc_calc, 0xff, ecc_bytes);
2303 chip->ecc.calculate(mtd, buf, ecc_calc);
2305 /* mask OOB of un-touched subpages by padding 0xFF */
2306 /* if oob_required, preserve OOB metadata of written subpage */
2307 if (!oob_required || (step < start_step) || (step > end_step))
2308 memset(oob_buf, 0xff, oob_bytes);
2311 ecc_calc += ecc_bytes;
2312 oob_buf += oob_bytes;
2315 /* copy calculated ECC for whole page to chip->buffer->oob */
2316 /* this include masked-value(0xFF) for unwritten subpages */
2317 ecc_calc = chip->buffers->ecccalc;
2318 for (i = 0; i < chip->ecc.total; i++)
2319 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2321 /* write OOB buffer to NAND device */
2322 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2329 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2330 * @mtd: mtd info structure
2331 * @chip: nand chip info structure
2333 * @oob_required: must write chip->oob_poi to OOB
2335 * The hw generator calculates the error syndrome automatically. Therefore we
2336 * need a special oob layout and handling.
2338 static int nand_write_page_syndrome(struct mtd_info *mtd,
2339 struct nand_chip *chip,
2340 const uint8_t *buf, int oob_required)
2342 int i, eccsize = chip->ecc.size;
2343 int eccbytes = chip->ecc.bytes;
2344 int eccsteps = chip->ecc.steps;
2345 const uint8_t *p = buf;
2346 uint8_t *oob = chip->oob_poi;
2348 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2350 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2351 chip->write_buf(mtd, p, eccsize);
2353 if (chip->ecc.prepad) {
2354 chip->write_buf(mtd, oob, chip->ecc.prepad);
2355 oob += chip->ecc.prepad;
2358 chip->ecc.calculate(mtd, p, oob);
2359 chip->write_buf(mtd, oob, eccbytes);
2362 if (chip->ecc.postpad) {
2363 chip->write_buf(mtd, oob, chip->ecc.postpad);
2364 oob += chip->ecc.postpad;
2368 /* Calculate remaining oob bytes */
2369 i = mtd->oobsize - (oob - chip->oob_poi);
2371 chip->write_buf(mtd, oob, i);
2377 * nand_write_page - [REPLACEABLE] write one page
2378 * @mtd: MTD device structure
2379 * @chip: NAND chip descriptor
2380 * @offset: address offset within the page
2381 * @data_len: length of actual data to be written
2382 * @buf: the data to write
2383 * @oob_required: must write chip->oob_poi to OOB
2384 * @page: page number to write
2385 * @cached: cached programming
2386 * @raw: use _raw version of write_page
2388 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2389 uint32_t offset, int data_len, const uint8_t *buf,
2390 int oob_required, int page, int cached, int raw)
2392 int status, subpage;
2394 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2395 chip->ecc.write_subpage)
2396 subpage = offset || (data_len < mtd->writesize);
2400 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2403 status = chip->ecc.write_page_raw(mtd, chip, buf,
2406 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2409 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2415 * Cached progamming disabled for now. Not sure if it's worth the
2416 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2420 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2422 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2423 status = chip->waitfunc(mtd, chip);
2425 * See if operation failed and additional status checks are
2428 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2429 status = chip->errstat(mtd, chip, FL_WRITING, status,
2432 if (status & NAND_STATUS_FAIL)
2435 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2436 status = chip->waitfunc(mtd, chip);
2441 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
2442 /* Send command to read back the data */
2443 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2445 if (chip->verify_buf(mtd, buf, mtd->writesize))
2448 /* Make sure the next page prog is preceded by a status read */
2449 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2457 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2458 * @mtd: MTD device structure
2459 * @oob: oob data buffer
2460 * @len: oob data write length
2461 * @ops: oob ops structure
2463 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2464 struct mtd_oob_ops *ops)
2466 struct nand_chip *chip = mtd->priv;
2469 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2470 * data from a previous OOB read.
2472 memset(chip->oob_poi, 0xff, mtd->oobsize);
2474 switch (ops->mode) {
2476 case MTD_OPS_PLACE_OOB:
2478 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2481 case MTD_OPS_AUTO_OOB: {
2482 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2483 uint32_t boffs = 0, woffs = ops->ooboffs;
2486 for (; free->length && len; free++, len -= bytes) {
2487 /* Write request not from offset 0? */
2488 if (unlikely(woffs)) {
2489 if (woffs >= free->length) {
2490 woffs -= free->length;
2493 boffs = free->offset + woffs;
2494 bytes = min_t(size_t, len,
2495 (free->length - woffs));
2498 bytes = min_t(size_t, len, free->length);
2499 boffs = free->offset;
2501 memcpy(chip->oob_poi + boffs, oob, bytes);
2512 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2515 * nand_do_write_ops - [INTERN] NAND write with ECC
2516 * @mtd: MTD device structure
2517 * @to: offset to write to
2518 * @ops: oob operations description structure
2520 * NAND write with ECC.
2522 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2523 struct mtd_oob_ops *ops)
2525 int chipnr, realpage, page, blockmask, column;
2526 struct nand_chip *chip = mtd->priv;
2527 uint32_t writelen = ops->len;
2529 uint32_t oobwritelen = ops->ooblen;
2530 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2531 mtd->oobavail : mtd->oobsize;
2533 uint8_t *oob = ops->oobbuf;
2534 uint8_t *buf = ops->datbuf;
2536 int oob_required = oob ? 1 : 0;
2543 /* Reject writes, which are not page aligned */
2544 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2546 /* Reject writes, which are not page aligned */
2547 if (NOTALIGNED(to)) {
2549 pr_notice("%s: attempt to write non page aligned data\n",
2554 column = to & (mtd->writesize - 1);
2556 chipnr = (int)(to >> chip->chip_shift);
2557 chip->select_chip(mtd, chipnr);
2559 /* Check, if it is write protected */
2560 if (nand_check_wp(mtd)) {
2565 realpage = (int)(to >> chip->page_shift);
2566 page = realpage & chip->pagemask;
2567 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2569 /* Invalidate the page cache, when we write to the cached page */
2570 if (to <= (chip->pagebuf << chip->page_shift) &&
2571 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2574 /* Don't allow multipage oob writes with offset */
2575 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2581 int bytes = mtd->writesize;
2582 int cached = writelen > bytes && page != blockmask;
2583 uint8_t *wbuf = buf;
2586 /* Partial page write? */
2587 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2589 bytes = min_t(int, bytes - column, (int) writelen);
2591 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2592 memcpy(&chip->buffers->databuf[column], buf, bytes);
2593 wbuf = chip->buffers->databuf;
2596 if (unlikely(oob)) {
2597 size_t len = min(oobwritelen, oobmaxlen);
2598 oob = nand_fill_oob(mtd, oob, len, ops);
2601 /* We still need to erase leftover OOB data */
2602 memset(chip->oob_poi, 0xff, mtd->oobsize);
2604 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2605 oob_required, page, cached,
2606 (ops->mode == MTD_OPS_RAW));
2618 page = realpage & chip->pagemask;
2619 /* Check, if we cross a chip boundary */
2622 chip->select_chip(mtd, -1);
2623 chip->select_chip(mtd, chipnr);
2627 ops->retlen = ops->len - writelen;
2629 ops->oobretlen = ops->ooblen;
2632 chip->select_chip(mtd, -1);
2637 * panic_nand_write - [MTD Interface] NAND write with ECC
2638 * @mtd: MTD device structure
2639 * @to: offset to write to
2640 * @len: number of bytes to write
2641 * @retlen: pointer to variable to store the number of written bytes
2642 * @buf: the data to write
2644 * NAND write with ECC. Used when performing writes in interrupt context, this
2645 * may for example be called by mtdoops when writing an oops while in panic.
2647 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2648 size_t *retlen, const uint8_t *buf)
2650 struct nand_chip *chip = mtd->priv;
2651 struct mtd_oob_ops ops;
2654 /* Wait for the device to get ready */
2655 panic_nand_wait(mtd, chip, 400);
2657 /* Grab the device */
2658 panic_nand_get_device(chip, mtd, FL_WRITING);
2661 ops.datbuf = (uint8_t *)buf;
2663 ops.mode = MTD_OPS_PLACE_OOB;
2665 ret = nand_do_write_ops(mtd, to, &ops);
2667 *retlen = ops.retlen;
2672 * nand_write - [MTD Interface] NAND write with ECC
2673 * @mtd: MTD device structure
2674 * @to: offset to write to
2675 * @len: number of bytes to write
2676 * @retlen: pointer to variable to store the number of written bytes
2677 * @buf: the data to write
2679 * NAND write with ECC.
2681 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2682 size_t *retlen, const uint8_t *buf)
2684 struct mtd_oob_ops ops;
2687 nand_get_device(mtd, FL_WRITING);
2689 ops.datbuf = (uint8_t *)buf;
2691 ops.mode = MTD_OPS_PLACE_OOB;
2692 ret = nand_do_write_ops(mtd, to, &ops);
2693 *retlen = ops.retlen;
2694 nand_release_device(mtd);
2699 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2700 * @mtd: MTD device structure
2701 * @to: offset to write to
2702 * @ops: oob operation description structure
2704 * NAND write out-of-band.
2706 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2707 struct mtd_oob_ops *ops)
2709 int chipnr, page, status, len;
2710 struct nand_chip *chip = mtd->priv;
2712 pr_debug("%s: to = 0x%08x, len = %i\n",
2713 __func__, (unsigned int)to, (int)ops->ooblen);
2715 if (ops->mode == MTD_OPS_AUTO_OOB)
2716 len = chip->ecc.layout->oobavail;
2720 /* Do not allow write past end of page */
2721 if ((ops->ooboffs + ops->ooblen) > len) {
2722 pr_debug("%s: attempt to write past end of page\n",
2727 if (unlikely(ops->ooboffs >= len)) {
2728 pr_debug("%s: attempt to start write outside oob\n",
2733 /* Do not allow write past end of device */
2734 if (unlikely(to >= mtd->size ||
2735 ops->ooboffs + ops->ooblen >
2736 ((mtd->size >> chip->page_shift) -
2737 (to >> chip->page_shift)) * len)) {
2738 pr_debug("%s: attempt to write beyond end of device\n",
2743 chipnr = (int)(to >> chip->chip_shift);
2744 chip->select_chip(mtd, chipnr);
2746 /* Shift to get page */
2747 page = (int)(to >> chip->page_shift);
2750 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2751 * of my DiskOnChip 2000 test units) will clear the whole data page too
2752 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2753 * it in the doc2000 driver in August 1999. dwmw2.
2755 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2757 /* Check, if it is write protected */
2758 if (nand_check_wp(mtd)) {
2759 chip->select_chip(mtd, -1);
2763 /* Invalidate the page cache, if we write to the cached page */
2764 if (page == chip->pagebuf)
2767 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2769 if (ops->mode == MTD_OPS_RAW)
2770 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2772 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2774 chip->select_chip(mtd, -1);
2779 ops->oobretlen = ops->ooblen;
2785 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2786 * @mtd: MTD device structure
2787 * @to: offset to write to
2788 * @ops: oob operation description structure
2790 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2791 struct mtd_oob_ops *ops)
2793 int ret = -ENOTSUPP;
2797 /* Do not allow writes past end of device */
2798 if (ops->datbuf && (to + ops->len) > mtd->size) {
2799 pr_debug("%s: attempt to write beyond end of device\n",
2804 nand_get_device(mtd, FL_WRITING);
2806 switch (ops->mode) {
2807 case MTD_OPS_PLACE_OOB:
2808 case MTD_OPS_AUTO_OOB:
2817 ret = nand_do_write_oob(mtd, to, ops);
2819 ret = nand_do_write_ops(mtd, to, ops);
2822 nand_release_device(mtd);
2827 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2828 * @mtd: MTD device structure
2829 * @page: the page address of the block which will be erased
2831 * Standard erase command for NAND chips.
2833 static void single_erase_cmd(struct mtd_info *mtd, int page)
2835 struct nand_chip *chip = mtd->priv;
2836 /* Send commands to erase a block */
2837 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2838 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2842 * nand_erase - [MTD Interface] erase block(s)
2843 * @mtd: MTD device structure
2844 * @instr: erase instruction
2846 * Erase one ore more blocks.
2848 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2850 return nand_erase_nand(mtd, instr, 0);
2854 * nand_erase_nand - [INTERN] erase block(s)
2855 * @mtd: MTD device structure
2856 * @instr: erase instruction
2857 * @allowbbt: allow erasing the bbt area
2859 * Erase one ore more blocks.
2861 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2864 int page, status, pages_per_block, ret, chipnr;
2865 struct nand_chip *chip = mtd->priv;
2868 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2869 __func__, (unsigned long long)instr->addr,
2870 (unsigned long long)instr->len);
2872 if (check_offs_len(mtd, instr->addr, instr->len))
2875 /* Grab the lock and see if the device is available */
2876 nand_get_device(mtd, FL_ERASING);
2878 /* Shift to get first page */
2879 page = (int)(instr->addr >> chip->page_shift);
2880 chipnr = (int)(instr->addr >> chip->chip_shift);
2882 /* Calculate pages in each block */
2883 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2885 /* Select the NAND device */
2886 chip->select_chip(mtd, chipnr);
2888 /* Check, if it is write protected */
2889 if (nand_check_wp(mtd)) {
2890 pr_debug("%s: device is write protected!\n",
2892 instr->state = MTD_ERASE_FAILED;
2896 /* Loop through the pages */
2899 instr->state = MTD_ERASING;
2904 /* Check if we have a bad block, we do not erase bad blocks! */
2905 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2906 chip->page_shift, 0, allowbbt)) {
2907 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2909 instr->state = MTD_ERASE_FAILED;
2914 * Invalidate the page cache, if we erase the block which
2915 * contains the current cached page.
2917 if (page <= chip->pagebuf && chip->pagebuf <
2918 (page + pages_per_block))
2921 chip->erase_cmd(mtd, page & chip->pagemask);
2923 status = chip->waitfunc(mtd, chip);
2926 * See if operation failed and additional status checks are
2929 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2930 status = chip->errstat(mtd, chip, FL_ERASING,
2933 /* See if block erase succeeded */
2934 if (status & NAND_STATUS_FAIL) {
2935 pr_debug("%s: failed erase, page 0x%08x\n",
2937 instr->state = MTD_ERASE_FAILED;
2939 ((loff_t)page << chip->page_shift);
2943 /* Increment page address and decrement length */
2944 len -= (1ULL << chip->phys_erase_shift);
2945 page += pages_per_block;
2947 /* Check, if we cross a chip boundary */
2948 if (len && !(page & chip->pagemask)) {
2950 chip->select_chip(mtd, -1);
2951 chip->select_chip(mtd, chipnr);
2954 instr->state = MTD_ERASE_DONE;
2958 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2960 /* Deselect and wake up anyone waiting on the device */
2961 chip->select_chip(mtd, -1);
2962 nand_release_device(mtd);
2964 /* Do call back function */
2966 mtd_erase_callback(instr);
2968 /* Return more or less happy */
2973 * nand_sync - [MTD Interface] sync
2974 * @mtd: MTD device structure
2976 * Sync is actually a wait for chip ready function.
2978 static void nand_sync(struct mtd_info *mtd)
2980 pr_debug("%s: called\n", __func__);
2982 /* Grab the lock and see if the device is available */
2983 nand_get_device(mtd, FL_SYNCING);
2984 /* Release it and go back */
2985 nand_release_device(mtd);
2989 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2990 * @mtd: MTD device structure
2991 * @offs: offset relative to mtd start
2993 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2995 return nand_block_checkbad(mtd, offs, 1, 0);
2999 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3000 * @mtd: MTD device structure
3001 * @ofs: offset relative to mtd start
3003 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3007 ret = nand_block_isbad(mtd, ofs);
3009 /* If it was bad already, return success and do nothing */
3015 return nand_block_markbad_lowlevel(mtd, ofs);
3019 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3020 * @mtd: MTD device structure
3021 * @chip: nand chip info structure
3022 * @addr: feature address.
3023 * @subfeature_param: the subfeature parameters, a four bytes array.
3025 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3026 int addr, uint8_t *subfeature_param)
3031 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3032 if (!chip->onfi_version ||
3033 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3034 & ONFI_OPT_CMD_SET_GET_FEATURES))
3038 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3039 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3040 chip->write_byte(mtd, subfeature_param[i]);
3042 status = chip->waitfunc(mtd, chip);
3043 if (status & NAND_STATUS_FAIL)
3049 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3050 * @mtd: MTD device structure
3051 * @chip: nand chip info structure
3052 * @addr: feature address.
3053 * @subfeature_param: the subfeature parameters, a four bytes array.
3055 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3056 int addr, uint8_t *subfeature_param)
3060 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3061 if (!chip->onfi_version ||
3062 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3063 & ONFI_OPT_CMD_SET_GET_FEATURES))
3067 /* clear the sub feature parameters */
3068 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3070 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3071 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3072 *subfeature_param++ = chip->read_byte(mtd);
3078 * nand_suspend - [MTD Interface] Suspend the NAND flash
3079 * @mtd: MTD device structure
3081 static int nand_suspend(struct mtd_info *mtd)
3083 return nand_get_device(mtd, FL_PM_SUSPENDED);
3087 * nand_resume - [MTD Interface] Resume the NAND flash
3088 * @mtd: MTD device structure
3090 static void nand_resume(struct mtd_info *mtd)
3092 struct nand_chip *chip = mtd->priv;
3094 if (chip->state == FL_PM_SUSPENDED)
3095 nand_release_device(mtd);
3097 pr_err("%s called for a chip which is not in suspended state\n",
3102 /* Set default functions */
3103 static void nand_set_defaults(struct nand_chip *chip, int busw)
3105 /* check for proper chip_delay setup, set 20us if not */
3106 if (!chip->chip_delay)
3107 chip->chip_delay = 20;
3109 /* check, if a user supplied command function given */
3110 if (chip->cmdfunc == NULL)
3111 chip->cmdfunc = nand_command;
3113 /* check, if a user supplied wait function given */
3114 if (chip->waitfunc == NULL)
3115 chip->waitfunc = nand_wait;
3117 if (!chip->select_chip)
3118 chip->select_chip = nand_select_chip;
3120 /* set for ONFI nand */
3121 if (!chip->onfi_set_features)
3122 chip->onfi_set_features = nand_onfi_set_features;
3123 if (!chip->onfi_get_features)
3124 chip->onfi_get_features = nand_onfi_get_features;
3126 /* If called twice, pointers that depend on busw may need to be reset */
3127 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3128 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3129 if (!chip->read_word)
3130 chip->read_word = nand_read_word;
3131 if (!chip->block_bad)
3132 chip->block_bad = nand_block_bad;
3133 if (!chip->block_markbad)
3134 chip->block_markbad = nand_default_block_markbad;
3135 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3136 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3137 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3138 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3139 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3140 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3141 if (!chip->scan_bbt)
3142 chip->scan_bbt = nand_default_bbt;
3144 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
3145 if (!chip->verify_buf)
3146 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
3150 if (!chip->controller) {
3151 chip->controller = &chip->hwcontrol;
3152 spin_lock_init(&chip->controller->lock);
3153 init_waitqueue_head(&chip->controller->wq);
3158 /* Sanitize ONFI strings so we can safely print them */
3160 static void sanitize_string(uint8_t *s, size_t len)
3162 static void sanitize_string(char *s, size_t len)
3167 /* Null terminate */
3170 /* Remove non printable chars */
3171 for (i = 0; i < len - 1; i++) {
3172 if (s[i] < ' ' || s[i] > 127)
3176 /* Remove trailing spaces */
3180 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3185 for (i = 0; i < 8; i++)
3186 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3192 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3193 /* Parse the Extended Parameter Page. */
3194 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3195 struct nand_chip *chip, struct nand_onfi_params *p)
3197 struct onfi_ext_param_page *ep;
3198 struct onfi_ext_section *s;
3199 struct onfi_ext_ecc_info *ecc;
3205 len = le16_to_cpu(p->ext_param_page_length) * 16;
3206 ep = kmalloc(len, GFP_KERNEL);
3210 /* Send our own NAND_CMD_PARAM. */
3211 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3213 /* Use the Change Read Column command to skip the ONFI param pages. */
3214 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3215 sizeof(*p) * p->num_of_param_pages , -1);
3217 /* Read out the Extended Parameter Page. */
3218 chip->read_buf(mtd, (uint8_t *)ep, len);
3219 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3220 != le16_to_cpu(ep->crc))) {
3221 pr_debug("fail in the CRC.\n");
3226 * Check the signature.
3227 * Do not strictly follow the ONFI spec, maybe changed in future.
3230 if (strncmp(ep->sig, "EPPS", 4)) {
3232 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3234 pr_debug("The signature is invalid.\n");
3238 /* find the ECC section. */
3239 cursor = (uint8_t *)(ep + 1);
3240 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3241 s = ep->sections + i;
3242 if (s->type == ONFI_SECTION_TYPE_2)
3244 cursor += s->length * 16;
3246 if (i == ONFI_EXT_SECTION_MAX) {
3247 pr_debug("We can not find the ECC section.\n");
3251 /* get the info we want. */
3252 ecc = (struct onfi_ext_ecc_info *)cursor;
3254 if (!ecc->codeword_size) {
3255 pr_debug("Invalid codeword size\n");
3259 chip->ecc_strength_ds = ecc->ecc_bits;
3260 chip->ecc_step_ds = 1 << ecc->codeword_size;
3268 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3270 struct nand_chip *chip = mtd->priv;
3271 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3273 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3278 * Configure chip properties from Micron vendor-specific ONFI table
3280 static void nand_onfi_detect_micron(struct nand_chip *chip,
3281 struct nand_onfi_params *p)
3283 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3285 if (le16_to_cpu(p->vendor_revision) < 1)
3288 chip->read_retries = micron->read_retry_options;
3289 chip->setup_read_retry = nand_setup_read_retry_micron;
3293 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3295 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3298 struct nand_onfi_params *p = &chip->onfi_params;
3302 /* Try ONFI for unknown chip or LP */
3303 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3304 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3305 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3308 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3309 for (i = 0; i < 3; i++) {
3310 for (j = 0; j < sizeof(*p); j++)
3311 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3312 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3313 le16_to_cpu(p->crc)) {
3319 pr_err("Could not find valid ONFI parameter page; aborting\n");
3324 val = le16_to_cpu(p->revision);
3326 chip->onfi_version = 23;
3327 else if (val & (1 << 4))
3328 chip->onfi_version = 22;
3329 else if (val & (1 << 3))
3330 chip->onfi_version = 21;
3331 else if (val & (1 << 2))
3332 chip->onfi_version = 20;
3333 else if (val & (1 << 1))
3334 chip->onfi_version = 10;
3336 if (!chip->onfi_version) {
3337 pr_info("unsupported ONFI version: %d\n", val);
3341 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3342 sanitize_string(p->model, sizeof(p->model));
3344 mtd->name = p->model;
3346 mtd->writesize = le32_to_cpu(p->byte_per_page);
3349 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3350 * (don't ask me who thought of this...). MTD assumes that these
3351 * dimensions will be power-of-2, so just truncate the remaining area.
3353 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3354 mtd->erasesize *= mtd->writesize;
3356 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3358 /* See erasesize comment */
3359 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3360 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3361 chip->bits_per_cell = p->bits_per_cell;
3363 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3364 *busw = NAND_BUSWIDTH_16;
3368 if (p->ecc_bits != 0xff) {
3369 chip->ecc_strength_ds = p->ecc_bits;
3370 chip->ecc_step_ds = 512;
3371 } else if (chip->onfi_version >= 21 &&
3372 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3375 * The nand_flash_detect_ext_param_page() uses the
3376 * Change Read Column command which maybe not supported
3377 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3378 * now. We do not replace user supplied command function.
3380 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3381 chip->cmdfunc = nand_command_lp;
3383 /* The Extended Parameter Page is supported since ONFI 2.1. */
3384 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3385 pr_warn("Failed to detect ONFI extended param page\n");
3387 pr_warn("Could not retrieve ONFI ECC requirements\n");
3390 if (p->jedec_id == NAND_MFR_MICRON)
3391 nand_onfi_detect_micron(chip, p);
3396 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3404 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3406 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3409 struct nand_jedec_params *p = &chip->jedec_params;
3410 struct jedec_ecc_info *ecc;
3414 /* Try JEDEC for unknown chip or LP */
3415 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3416 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3417 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3418 chip->read_byte(mtd) != 'C')
3421 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3422 for (i = 0; i < 3; i++) {
3423 for (j = 0; j < sizeof(*p); j++)
3424 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3426 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3427 le16_to_cpu(p->crc))
3432 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3437 val = le16_to_cpu(p->revision);
3439 chip->jedec_version = 10;
3440 else if (val & (1 << 1))
3441 chip->jedec_version = 1; /* vendor specific version */
3443 if (!chip->jedec_version) {
3444 pr_info("unsupported JEDEC version: %d\n", val);
3448 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3449 sanitize_string(p->model, sizeof(p->model));
3451 mtd->name = p->model;
3453 mtd->writesize = le32_to_cpu(p->byte_per_page);
3455 /* Please reference to the comment for nand_flash_detect_onfi. */
3456 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3457 mtd->erasesize *= mtd->writesize;
3459 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3461 /* Please reference to the comment for nand_flash_detect_onfi. */
3462 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3463 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3464 chip->bits_per_cell = p->bits_per_cell;
3466 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3467 *busw = NAND_BUSWIDTH_16;
3472 ecc = &p->ecc_info[0];
3474 if (ecc->codeword_size >= 9) {
3475 chip->ecc_strength_ds = ecc->ecc_bits;
3476 chip->ecc_step_ds = 1 << ecc->codeword_size;
3478 pr_warn("Invalid codeword size\n");
3485 * nand_id_has_period - Check if an ID string has a given wraparound period
3486 * @id_data: the ID string
3487 * @arrlen: the length of the @id_data array
3488 * @period: the period of repitition
3490 * Check if an ID string is repeated within a given sequence of bytes at
3491 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3492 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3493 * if the repetition has a period of @period; otherwise, returns zero.
3495 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3498 for (i = 0; i < period; i++)
3499 for (j = i + period; j < arrlen; j += period)
3500 if (id_data[i] != id_data[j])
3506 * nand_id_len - Get the length of an ID string returned by CMD_READID
3507 * @id_data: the ID string
3508 * @arrlen: the length of the @id_data array
3510 * Returns the length of the ID string, according to known wraparound/trailing
3511 * zero patterns. If no pattern exists, returns the length of the array.
3513 static int nand_id_len(u8 *id_data, int arrlen)
3515 int last_nonzero, period;
3517 /* Find last non-zero byte */
3518 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3519 if (id_data[last_nonzero])
3523 if (last_nonzero < 0)
3526 /* Calculate wraparound period */
3527 for (period = 1; period < arrlen; period++)
3528 if (nand_id_has_period(id_data, arrlen, period))
3531 /* There's a repeated pattern */
3532 if (period < arrlen)
3535 /* There are trailing zeros */
3536 if (last_nonzero < arrlen - 1)
3537 return last_nonzero + 1;
3539 /* No pattern detected */
3543 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3544 static int nand_get_bits_per_cell(u8 cellinfo)
3548 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3549 bits >>= NAND_CI_CELLTYPE_SHIFT;
3554 * Many new NAND share similar device ID codes, which represent the size of the
3555 * chip. The rest of the parameters must be decoded according to generic or
3556 * manufacturer-specific "extended ID" decoding patterns.
3558 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3559 u8 id_data[8], int *busw)
3562 /* The 3rd id byte holds MLC / multichip data */
3563 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3564 /* The 4th id byte is the important one */
3567 id_len = nand_id_len(id_data, 8);
3570 * Field definitions are in the following datasheets:
3571 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3572 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3573 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3575 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3576 * ID to decide what to do.
3578 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3579 !nand_is_slc(chip) && id_data[5] != 0x00) {
3581 mtd->writesize = 2048 << (extid & 0x03);
3584 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3604 default: /* Other cases are "reserved" (unknown) */
3605 mtd->oobsize = 1024;
3609 /* Calc blocksize */
3610 mtd->erasesize = (128 * 1024) <<
3611 (((extid >> 1) & 0x04) | (extid & 0x03));
3613 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3614 !nand_is_slc(chip)) {
3618 mtd->writesize = 2048 << (extid & 0x03);
3621 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3645 /* Calc blocksize */
3646 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3648 mtd->erasesize = (128 * 1024) << tmp;
3649 else if (tmp == 0x03)
3650 mtd->erasesize = 768 * 1024;
3652 mtd->erasesize = (64 * 1024) << tmp;
3656 mtd->writesize = 1024 << (extid & 0x03);
3659 mtd->oobsize = (8 << (extid & 0x01)) *
3660 (mtd->writesize >> 9);
3662 /* Calc blocksize. Blocksize is multiples of 64KiB */
3663 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3665 /* Get buswidth information */
3666 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3669 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3670 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3672 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3674 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3676 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3677 nand_is_slc(chip) &&
3678 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3679 !(id_data[4] & 0x80) /* !BENAND */) {
3680 mtd->oobsize = 32 * mtd->writesize >> 9;
3687 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3688 * decodes a matching ID table entry and assigns the MTD size parameters for
3691 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3692 struct nand_flash_dev *type, u8 id_data[8],
3695 int maf_id = id_data[0];
3697 mtd->erasesize = type->erasesize;
3698 mtd->writesize = type->pagesize;
3699 mtd->oobsize = mtd->writesize / 32;
3700 *busw = type->options & NAND_BUSWIDTH_16;
3702 /* All legacy ID NAND are small-page, SLC */
3703 chip->bits_per_cell = 1;
3706 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3707 * some Spansion chips have erasesize that conflicts with size
3708 * listed in nand_ids table.
3709 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3711 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3712 && id_data[6] == 0x00 && id_data[7] == 0x00
3713 && mtd->writesize == 512) {
3714 mtd->erasesize = 128 * 1024;
3715 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3720 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3721 * heuristic patterns using various detected parameters (e.g., manufacturer,
3722 * page size, cell-type information).
3724 static void nand_decode_bbm_options(struct mtd_info *mtd,
3725 struct nand_chip *chip, u8 id_data[8])
3727 int maf_id = id_data[0];
3729 /* Set the bad block position */
3730 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3731 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3733 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3736 * Bad block marker is stored in the last page of each block on Samsung
3737 * and Hynix MLC devices; stored in first two pages of each block on
3738 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3739 * AMD/Spansion, and Macronix. All others scan only the first page.
3741 if (!nand_is_slc(chip) &&
3742 (maf_id == NAND_MFR_SAMSUNG ||
3743 maf_id == NAND_MFR_HYNIX))
3744 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3745 else if ((nand_is_slc(chip) &&
3746 (maf_id == NAND_MFR_SAMSUNG ||
3747 maf_id == NAND_MFR_HYNIX ||
3748 maf_id == NAND_MFR_TOSHIBA ||
3749 maf_id == NAND_MFR_AMD ||
3750 maf_id == NAND_MFR_MACRONIX)) ||
3751 (mtd->writesize == 2048 &&
3752 maf_id == NAND_MFR_MICRON))
3753 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3756 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3758 return type->id_len;
3761 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3762 struct nand_flash_dev *type, u8 *id_data, int *busw)
3765 if (!strncmp(type->id, id_data, type->id_len)) {
3767 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3769 mtd->writesize = type->pagesize;
3770 mtd->erasesize = type->erasesize;
3771 mtd->oobsize = type->oobsize;
3773 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3774 chip->chipsize = (uint64_t)type->chipsize << 20;
3775 chip->options |= type->options;
3776 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3777 chip->ecc_step_ds = NAND_ECC_STEP(type);
3779 *busw = type->options & NAND_BUSWIDTH_16;
3782 mtd->name = type->name;
3790 * Get the flash and manufacturer id and lookup if the type is supported.
3792 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3793 struct nand_chip *chip,
3794 int *maf_id, int *dev_id,
3795 struct nand_flash_dev *type)
3801 /* Select the device */
3802 chip->select_chip(mtd, 0);
3805 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3808 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3810 /* Send the command for reading device ID */
3811 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3813 /* Read manufacturer and device IDs */
3814 *maf_id = chip->read_byte(mtd);
3815 *dev_id = chip->read_byte(mtd);
3818 * Try again to make sure, as some systems the bus-hold or other
3819 * interface concerns can cause random data which looks like a
3820 * possibly credible NAND flash to appear. If the two results do
3821 * not match, ignore the device completely.
3824 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3826 /* Read entire ID string */
3827 for (i = 0; i < 8; i++)
3828 id_data[i] = chip->read_byte(mtd);
3830 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3831 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3832 *maf_id, *dev_id, id_data[0], id_data[1]);
3833 return ERR_PTR(-ENODEV);
3837 type = nand_flash_ids;
3839 for (; type->name != NULL; type++) {
3840 if (is_full_id_nand(type)) {
3841 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3843 } else if (*dev_id == type->dev_id) {
3848 chip->onfi_version = 0;
3849 if (!type->name || !type->pagesize) {
3850 /* Check is chip is ONFI compliant */
3851 if (nand_flash_detect_onfi(mtd, chip, &busw))
3854 /* Check if the chip is JEDEC compliant */
3855 if (nand_flash_detect_jedec(mtd, chip, &busw))
3860 return ERR_PTR(-ENODEV);
3863 mtd->name = type->name;
3865 chip->chipsize = (uint64_t)type->chipsize << 20;
3867 if (!type->pagesize && chip->init_size) {
3868 /* Set the pagesize, oobsize, erasesize by the driver */
3869 busw = chip->init_size(mtd, chip, id_data);
3870 } else if (!type->pagesize) {
3871 /* Decode parameters from extended ID */
3872 nand_decode_ext_id(mtd, chip, id_data, &busw);
3874 nand_decode_id(mtd, chip, type, id_data, &busw);
3876 /* Get chip options */
3877 chip->options |= type->options;
3880 * Check if chip is not a Samsung device. Do not clear the
3881 * options for chips which do not have an extended id.
3883 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3884 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3887 /* Try to identify manufacturer */
3888 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3889 if (nand_manuf_ids[maf_idx].id == *maf_id)
3893 if (chip->options & NAND_BUSWIDTH_AUTO) {
3894 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3895 chip->options |= busw;
3896 nand_set_defaults(chip, busw);
3897 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3899 * Check, if buswidth is correct. Hardware drivers should set
3902 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3904 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3905 pr_warn("bus width %d instead %d bit\n",
3906 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3908 return ERR_PTR(-EINVAL);
3911 nand_decode_bbm_options(mtd, chip, id_data);
3913 /* Calculate the address shift from the page size */
3914 chip->page_shift = ffs(mtd->writesize) - 1;
3915 /* Convert chipsize to number of pages per chip -1 */
3916 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3918 chip->bbt_erase_shift = chip->phys_erase_shift =
3919 ffs(mtd->erasesize) - 1;
3920 if (chip->chipsize & 0xffffffff)
3921 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3923 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3924 chip->chip_shift += 32 - 1;
3927 chip->badblockbits = 8;
3928 chip->erase_cmd = single_erase_cmd;
3930 /* Do not replace user supplied command function! */
3931 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3932 chip->cmdfunc = nand_command_lp;
3934 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3937 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3938 if (chip->onfi_version)
3939 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3940 chip->onfi_params.model);
3941 else if (chip->jedec_version)
3942 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3943 chip->jedec_params.model);
3945 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3948 if (chip->jedec_version)
3949 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3950 chip->jedec_params.model);
3952 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3955 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3959 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3960 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3961 mtd->writesize, mtd->oobsize);
3966 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3967 * @mtd: MTD device structure
3968 * @maxchips: number of chips to scan for
3969 * @table: alternative NAND ID table
3971 * This is the first phase of the normal nand_scan() function. It reads the
3972 * flash ID and sets up MTD fields accordingly.
3974 * The mtd->owner field must be set to the module of the caller.
3976 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3977 struct nand_flash_dev *table)
3979 int i, nand_maf_id, nand_dev_id;
3980 struct nand_chip *chip = mtd->priv;
3981 struct nand_flash_dev *type;
3983 /* Set the default functions */
3984 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3986 /* Read the flash type */
3987 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3988 &nand_dev_id, table);
3991 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3992 pr_warn("No NAND device found\n");
3993 chip->select_chip(mtd, -1);
3994 return PTR_ERR(type);
3997 chip->select_chip(mtd, -1);
3999 /* Check for a chip array */
4000 for (i = 1; i < maxchips; i++) {
4001 chip->select_chip(mtd, i);
4002 /* See comment in nand_get_flash_type for reset */
4003 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4004 /* Send the command for reading device ID */
4005 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4006 /* Read manufacturer and device IDs */
4007 if (nand_maf_id != chip->read_byte(mtd) ||
4008 nand_dev_id != chip->read_byte(mtd)) {
4009 chip->select_chip(mtd, -1);
4012 chip->select_chip(mtd, -1);
4017 pr_info("%d chips detected\n", i);
4020 /* Store the number of chips and calc total size for mtd */
4022 mtd->size = i * chip->chipsize;
4026 EXPORT_SYMBOL(nand_scan_ident);
4030 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4031 * @mtd: MTD device structure
4033 * This is the second phase of the normal nand_scan() function. It fills out
4034 * all the uninitialized function pointers with the defaults and scans for a
4035 * bad block table if appropriate.
4037 int nand_scan_tail(struct mtd_info *mtd)
4040 struct nand_chip *chip = mtd->priv;
4041 struct nand_ecc_ctrl *ecc = &chip->ecc;
4042 struct nand_buffers *nbuf;
4044 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4045 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4046 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4048 if (!(chip->options & NAND_OWN_BUFFERS)) {
4050 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4051 + mtd->oobsize * 3, GFP_KERNEL);
4054 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4055 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4056 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4058 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4061 chip->buffers = nbuf;
4067 /* Set the internal oob buffer location, just after the page data */
4068 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4071 * If no default placement scheme is given, select an appropriate one.
4073 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4074 switch (mtd->oobsize) {
4076 ecc->layout = &nand_oob_8;
4079 ecc->layout = &nand_oob_16;
4082 ecc->layout = &nand_oob_64;
4085 ecc->layout = &nand_oob_128;
4088 pr_warn("No oob scheme defined for oobsize %d\n",
4094 if (!chip->write_page)
4095 chip->write_page = nand_write_page;
4098 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4099 * selected and we have 256 byte pagesize fallback to software ECC
4102 switch (ecc->mode) {
4103 case NAND_ECC_HW_OOB_FIRST:
4104 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4105 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4106 pr_warn("No ECC functions supplied; "
4107 "hardware ECC not possible\n");
4110 if (!ecc->read_page)
4111 ecc->read_page = nand_read_page_hwecc_oob_first;
4114 /* Use standard hwecc read page function? */
4115 if (!ecc->read_page)
4116 ecc->read_page = nand_read_page_hwecc;
4117 if (!ecc->write_page)
4118 ecc->write_page = nand_write_page_hwecc;
4119 if (!ecc->read_page_raw)
4120 ecc->read_page_raw = nand_read_page_raw;
4121 if (!ecc->write_page_raw)
4122 ecc->write_page_raw = nand_write_page_raw;
4124 ecc->read_oob = nand_read_oob_std;
4125 if (!ecc->write_oob)
4126 ecc->write_oob = nand_write_oob_std;
4127 if (!ecc->read_subpage)
4128 ecc->read_subpage = nand_read_subpage;
4129 if (!ecc->write_subpage)
4130 ecc->write_subpage = nand_write_subpage_hwecc;
4132 case NAND_ECC_HW_SYNDROME:
4133 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4135 ecc->read_page == nand_read_page_hwecc ||
4137 ecc->write_page == nand_write_page_hwecc)) {
4138 pr_warn("No ECC functions supplied; "
4139 "hardware ECC not possible\n");
4142 /* Use standard syndrome read/write page function? */
4143 if (!ecc->read_page)
4144 ecc->read_page = nand_read_page_syndrome;
4145 if (!ecc->write_page)
4146 ecc->write_page = nand_write_page_syndrome;
4147 if (!ecc->read_page_raw)
4148 ecc->read_page_raw = nand_read_page_raw_syndrome;
4149 if (!ecc->write_page_raw)
4150 ecc->write_page_raw = nand_write_page_raw_syndrome;
4152 ecc->read_oob = nand_read_oob_syndrome;
4153 if (!ecc->write_oob)
4154 ecc->write_oob = nand_write_oob_syndrome;
4156 if (mtd->writesize >= ecc->size) {
4157 if (!ecc->strength) {
4158 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4163 pr_warn("%d byte HW ECC not possible on "
4164 "%d byte page size, fallback to SW ECC\n",
4165 ecc->size, mtd->writesize);
4166 ecc->mode = NAND_ECC_SOFT;
4169 ecc->calculate = nand_calculate_ecc;
4170 ecc->correct = nand_correct_data;
4171 ecc->read_page = nand_read_page_swecc;
4172 ecc->read_subpage = nand_read_subpage;
4173 ecc->write_page = nand_write_page_swecc;
4174 ecc->read_page_raw = nand_read_page_raw;
4175 ecc->write_page_raw = nand_write_page_raw;
4176 ecc->read_oob = nand_read_oob_std;
4177 ecc->write_oob = nand_write_oob_std;
4184 case NAND_ECC_SOFT_BCH:
4185 if (!mtd_nand_has_bch()) {
4186 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4189 ecc->calculate = nand_bch_calculate_ecc;
4190 ecc->correct = nand_bch_correct_data;
4191 ecc->read_page = nand_read_page_swecc;
4192 ecc->read_subpage = nand_read_subpage;
4193 ecc->write_page = nand_write_page_swecc;
4194 ecc->read_page_raw = nand_read_page_raw;
4195 ecc->write_page_raw = nand_write_page_raw;
4196 ecc->read_oob = nand_read_oob_std;
4197 ecc->write_oob = nand_write_oob_std;
4199 * Board driver should supply ecc.size and ecc.bytes values to
4200 * select how many bits are correctable; see nand_bch_init()
4201 * for details. Otherwise, default to 4 bits for large page
4204 if (!ecc->size && (mtd->oobsize >= 64)) {
4208 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4211 pr_warn("BCH ECC initialization failed!\n");
4214 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
4218 pr_warn("NAND_ECC_NONE selected by board driver. "
4219 "This is not recommended!\n");
4220 ecc->read_page = nand_read_page_raw;
4221 ecc->write_page = nand_write_page_raw;
4222 ecc->read_oob = nand_read_oob_std;
4223 ecc->read_page_raw = nand_read_page_raw;
4224 ecc->write_page_raw = nand_write_page_raw;
4225 ecc->write_oob = nand_write_oob_std;
4226 ecc->size = mtd->writesize;
4232 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4236 /* For many systems, the standard OOB write also works for raw */
4237 if (!ecc->read_oob_raw)
4238 ecc->read_oob_raw = ecc->read_oob;
4239 if (!ecc->write_oob_raw)
4240 ecc->write_oob_raw = ecc->write_oob;
4243 * The number of bytes available for a client to place data into
4244 * the out of band area.
4246 ecc->layout->oobavail = 0;
4247 for (i = 0; ecc->layout->oobfree[i].length
4248 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4249 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4250 mtd->oobavail = ecc->layout->oobavail;
4253 * Set the number of read / write steps for one page depending on ECC
4256 ecc->steps = mtd->writesize / ecc->size;
4257 if (ecc->steps * ecc->size != mtd->writesize) {
4258 pr_warn("Invalid ECC parameters\n");
4261 ecc->total = ecc->steps * ecc->bytes;
4263 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4264 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4265 switch (ecc->steps) {
4267 mtd->subpage_sft = 1;
4272 mtd->subpage_sft = 2;
4276 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4278 /* Initialize state */
4279 chip->state = FL_READY;
4281 /* Invalidate the pagebuffer reference */
4284 /* Large page NAND with SOFT_ECC should support subpage reads */
4285 if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4286 chip->options |= NAND_SUBPAGE_READ;
4288 /* Fill in remaining MTD driver data */
4289 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4290 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4292 mtd->_erase = nand_erase;
4295 mtd->_unpoint = NULL;
4297 mtd->_read = nand_read;
4298 mtd->_write = nand_write;
4299 mtd->_panic_write = panic_nand_write;
4300 mtd->_read_oob = nand_read_oob;
4301 mtd->_write_oob = nand_write_oob;
4302 mtd->_sync = nand_sync;
4304 mtd->_unlock = NULL;
4306 mtd->_suspend = nand_suspend;
4307 mtd->_resume = nand_resume;
4309 mtd->_block_isbad = nand_block_isbad;
4310 mtd->_block_markbad = nand_block_markbad;
4311 mtd->writebufsize = mtd->writesize;
4313 /* propagate ecc info to mtd_info */
4314 mtd->ecclayout = ecc->layout;
4315 mtd->ecc_strength = ecc->strength;
4316 mtd->ecc_step_size = ecc->size;
4318 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4319 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4322 if (!mtd->bitflip_threshold)
4323 mtd->bitflip_threshold = mtd->ecc_strength;
4325 /* Check, if we should skip the bad block table scan */
4326 if (chip->options & NAND_SKIP_BBTSCAN)
4329 /* Build bad block table */
4330 return chip->scan_bbt(mtd);
4332 EXPORT_SYMBOL(nand_scan_tail);
4335 * is_module_text_address() isn't exported, and it's mostly a pointless
4336 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4337 * to call us from in-kernel code if the core NAND support is modular.
4340 #define caller_is_module() (1)
4342 #define caller_is_module() \
4343 is_module_text_address((unsigned long)__builtin_return_address(0))
4347 * nand_scan - [NAND Interface] Scan for the NAND device
4348 * @mtd: MTD device structure
4349 * @maxchips: number of chips to scan for
4351 * This fills out all the uninitialized function pointers with the defaults.
4352 * The flash ID is read and the mtd/chip structures are filled with the
4353 * appropriate values. The mtd->owner field must be set to the module of the
4356 int nand_scan(struct mtd_info *mtd, int maxchips)
4360 /* Many callers got this wrong, so check for it for a while... */
4361 if (!mtd->owner && caller_is_module()) {
4362 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4366 ret = nand_scan_ident(mtd, maxchips, NULL);
4368 ret = nand_scan_tail(mtd);
4371 EXPORT_SYMBOL(nand_scan);
4375 * nand_release - [NAND Interface] Free resources held by the NAND device
4376 * @mtd: MTD device structure
4378 void nand_release(struct mtd_info *mtd)
4380 struct nand_chip *chip = mtd->priv;
4382 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4383 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4385 mtd_device_unregister(mtd);
4387 /* Free bad block table memory */
4389 if (!(chip->options & NAND_OWN_BUFFERS))
4390 kfree(chip->buffers);
4392 /* Free bad block descriptor memory */
4393 if (chip->badblock_pattern && chip->badblock_pattern->options
4394 & NAND_BBT_DYNAMICSTRUCT)
4395 kfree(chip->badblock_pattern);
4397 EXPORT_SYMBOL_GPL(nand_release);
4399 static int __init nand_base_init(void)
4401 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4405 static void __exit nand_base_exit(void)
4407 led_trigger_unregister_simple(nand_led_trigger);
4411 module_init(nand_base_init);
4412 module_exit(nand_base_exit);
4414 MODULE_LICENSE("GPL");
4415 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4416 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4417 MODULE_DESCRIPTION("Generic NAND flash driver code");