5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
37 #include <linux/module.h>
38 #include <linux/delay.h>
39 #include <linux/errno.h>
40 #include <linux/err.h>
41 #include <linux/sched.h>
42 #include <linux/slab.h>
43 #include <linux/types.h>
44 #include <linux/mtd/mtd.h>
45 #include <linux/mtd/nand.h>
46 #include <linux/mtd/nand_ecc.h>
47 #include <linux/mtd/compatmac.h>
48 #include <linux/interrupt.h>
49 #include <linux/bitops.h>
50 #include <linux/leds.h>
53 #ifdef CONFIG_MTD_PARTITIONS
54 #include <linux/mtd/partitions.h>
61 #define ENOTSUPP 524 /* Operation is not supported */
65 #include <linux/err.h>
66 #include <linux/mtd/compat.h>
67 #include <linux/mtd/mtd.h>
68 #include <linux/mtd/nand.h>
69 #include <linux/mtd/nand_ecc.h>
72 #include <asm/errno.h>
74 #ifdef CONFIG_JFFS2_NAND
75 #include <jffs2/jffs2.h>
79 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
80 * a flash. NAND flash is initialized prior to interrupts so standard timers
81 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
82 * which is greater than (max NAND reset time / NAND status read time).
83 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
85 #ifndef CONFIG_SYS_NAND_RESET_CNT
86 #define CONFIG_SYS_NAND_RESET_CNT 200000
89 /* Define default oob placement schemes for large and small page devices */
90 static struct nand_ecclayout nand_oob_8 = {
100 static struct nand_ecclayout nand_oob_16 = {
102 .eccpos = {0, 1, 2, 3, 6, 7},
108 static struct nand_ecclayout nand_oob_64 = {
111 40, 41, 42, 43, 44, 45, 46, 47,
112 48, 49, 50, 51, 52, 53, 54, 55,
113 56, 57, 58, 59, 60, 61, 62, 63},
119 static struct nand_ecclayout nand_oob_128 = {
122 80, 81, 82, 83, 84, 85, 86, 87,
123 88, 89, 90, 91, 92, 93, 94, 95,
124 96, 97, 98, 99, 100, 101, 102, 103,
125 104, 105, 106, 107, 108, 109, 110, 111,
126 112, 113, 114, 115, 116, 117, 118, 119,
127 120, 121, 122, 123, 124, 125, 126, 127},
134 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
137 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
138 struct mtd_oob_ops *ops);
140 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
143 * For devices which display every fart in the system on a separate LED. Is
144 * compiled away when LED support is disabled.
148 DEFINE_LED_TRIGGER(nand_led_trigger);
152 * nand_release_device - [GENERIC] release chip
153 * @mtd: MTD device structure
155 * Deselect, release chip lock and wake up anyone waiting on the device
159 static void nand_release_device(struct mtd_info *mtd)
161 struct nand_chip *chip = mtd->priv;
163 /* De-select the NAND device */
164 chip->select_chip(mtd, -1);
166 /* Release the controller and the chip */
167 spin_lock(&chip->controller->lock);
168 chip->controller->active = NULL;
169 chip->state = FL_READY;
170 wake_up(&chip->controller->wq);
171 spin_unlock(&chip->controller->lock);
174 static void nand_release_device (struct mtd_info *mtd)
176 struct nand_chip *this = mtd->priv;
177 this->select_chip(mtd, -1); /* De-select the NAND device */
182 * nand_read_byte - [DEFAULT] read one byte from the chip
183 * @mtd: MTD device structure
185 * Default read function for 8bit buswith
187 static uint8_t nand_read_byte(struct mtd_info *mtd)
189 struct nand_chip *chip = mtd->priv;
190 return readb(chip->IO_ADDR_R);
194 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
195 * @mtd: MTD device structure
197 * Default read function for 16bit buswith with
198 * endianess conversion
200 static uint8_t nand_read_byte16(struct mtd_info *mtd)
202 struct nand_chip *chip = mtd->priv;
203 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
207 * nand_read_word - [DEFAULT] read one word from the chip
208 * @mtd: MTD device structure
210 * Default read function for 16bit buswith without
211 * endianess conversion
213 static u16 nand_read_word(struct mtd_info *mtd)
215 struct nand_chip *chip = mtd->priv;
216 return readw(chip->IO_ADDR_R);
220 * nand_select_chip - [DEFAULT] control CE line
221 * @mtd: MTD device structure
222 * @chipnr: chipnumber to select, -1 for deselect
224 * Default select function for 1 chip devices.
226 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
228 struct nand_chip *chip = mtd->priv;
232 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
243 * nand_write_buf - [DEFAULT] write buffer to chip
244 * @mtd: MTD device structure
246 * @len: number of bytes to write
248 * Default write function for 8bit buswith
250 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
253 struct nand_chip *chip = mtd->priv;
255 for (i = 0; i < len; i++)
256 writeb(buf[i], chip->IO_ADDR_W);
260 * nand_read_buf - [DEFAULT] read chip data into buffer
261 * @mtd: MTD device structure
262 * @buf: buffer to store date
263 * @len: number of bytes to read
265 * Default read function for 8bit buswith
267 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
270 struct nand_chip *chip = mtd->priv;
272 for (i = 0; i < len; i++)
273 buf[i] = readb(chip->IO_ADDR_R);
277 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
278 * @mtd: MTD device structure
279 * @buf: buffer containing the data to compare
280 * @len: number of bytes to compare
282 * Default verify function for 8bit buswith
284 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
287 struct nand_chip *chip = mtd->priv;
289 for (i = 0; i < len; i++)
290 if (buf[i] != readb(chip->IO_ADDR_R))
296 * nand_write_buf16 - [DEFAULT] write buffer to chip
297 * @mtd: MTD device structure
299 * @len: number of bytes to write
301 * Default write function for 16bit buswith
303 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
306 struct nand_chip *chip = mtd->priv;
307 u16 *p = (u16 *) buf;
310 for (i = 0; i < len; i++)
311 writew(p[i], chip->IO_ADDR_W);
316 * nand_read_buf16 - [DEFAULT] read chip data into buffer
317 * @mtd: MTD device structure
318 * @buf: buffer to store date
319 * @len: number of bytes to read
321 * Default read function for 16bit buswith
323 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
326 struct nand_chip *chip = mtd->priv;
327 u16 *p = (u16 *) buf;
330 for (i = 0; i < len; i++)
331 p[i] = readw(chip->IO_ADDR_R);
335 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
336 * @mtd: MTD device structure
337 * @buf: buffer containing the data to compare
338 * @len: number of bytes to compare
340 * Default verify function for 16bit buswith
342 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
345 struct nand_chip *chip = mtd->priv;
346 u16 *p = (u16 *) buf;
349 for (i = 0; i < len; i++)
350 if (p[i] != readw(chip->IO_ADDR_R))
357 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
358 * @mtd: MTD device structure
359 * @ofs: offset from device start
360 * @getchip: 0, if the chip is already selected
362 * Check, if the block is bad.
364 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
366 int page, chipnr, res = 0;
367 struct nand_chip *chip = mtd->priv;
370 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
373 chipnr = (int)(ofs >> chip->chip_shift);
375 nand_get_device(chip, mtd, FL_READING);
377 /* Select the NAND device */
378 chip->select_chip(mtd, chipnr);
381 if (chip->options & NAND_BUSWIDTH_16) {
382 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
384 bad = cpu_to_le16(chip->read_word(mtd));
385 if (chip->badblockpos & 0x1)
387 if ((bad & 0xFF) != 0xff)
390 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
391 if (chip->read_byte(mtd) != 0xff)
396 nand_release_device(mtd);
402 * nand_default_block_markbad - [DEFAULT] mark a block bad
403 * @mtd: MTD device structure
404 * @ofs: offset from device start
406 * This is the default implementation, which can be overridden by
407 * a hardware specific driver.
409 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
411 struct nand_chip *chip = mtd->priv;
412 uint8_t buf[2] = { 0, 0 };
415 /* Get block number */
416 block = (int)(ofs >> chip->bbt_erase_shift);
418 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
420 /* Do we have a flash based bad block table ? */
421 if (chip->options & NAND_USE_FLASH_BBT)
422 ret = nand_update_bbt(mtd, ofs);
424 /* We write two bytes, so we dont have to mess with 16 bit
427 nand_get_device(chip, mtd, FL_WRITING);
429 chip->ops.len = chip->ops.ooblen = 2;
430 chip->ops.datbuf = NULL;
431 chip->ops.oobbuf = buf;
432 chip->ops.ooboffs = chip->badblockpos & ~0x01;
434 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
435 nand_release_device(mtd);
438 mtd->ecc_stats.badblocks++;
444 * nand_check_wp - [GENERIC] check if the chip is write protected
445 * @mtd: MTD device structure
446 * Check, if the device is write protected
448 * The function expects, that the device is already selected
450 static int nand_check_wp(struct mtd_info *mtd)
452 struct nand_chip *chip = mtd->priv;
453 /* Check the WP bit */
454 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
455 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
459 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
460 * @mtd: MTD device structure
461 * @ofs: offset from device start
462 * @getchip: 0, if the chip is already selected
463 * @allowbbt: 1, if its allowed to access the bbt area
465 * Check, if the block is bad. Either by reading the bad block table or
466 * calling of the scan function.
468 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
471 struct nand_chip *chip = mtd->priv;
473 if (!(chip->options & NAND_BBT_SCANNED)) {
474 chip->options |= NAND_BBT_SCANNED;
479 return chip->block_bad(mtd, ofs, getchip);
481 /* Return info from the table */
482 return nand_isbad_bbt(mtd, ofs, allowbbt);
486 * Wait for the ready pin, after a command
487 * The timeout is catched later.
491 void nand_wait_ready(struct mtd_info *mtd)
493 struct nand_chip *chip = mtd->priv;
494 unsigned long timeo = jiffies + 2;
496 led_trigger_event(nand_led_trigger, LED_FULL);
497 /* wait until command is processed or timeout occures */
499 if (chip->dev_ready(mtd))
501 touch_softlockup_watchdog();
502 } while (time_before(jiffies, timeo));
503 led_trigger_event(nand_led_trigger, LED_OFF);
505 EXPORT_SYMBOL_GPL(nand_wait_ready);
507 void nand_wait_ready(struct mtd_info *mtd)
509 struct nand_chip *chip = mtd->priv;
510 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
514 /* wait until command is processed or timeout occures */
515 while (get_timer(0) < timeo) {
517 if (chip->dev_ready(mtd))
524 * nand_command - [DEFAULT] Send command to NAND device
525 * @mtd: MTD device structure
526 * @command: the command to be sent
527 * @column: the column address for this command, -1 if none
528 * @page_addr: the page address for this command, -1 if none
530 * Send command to NAND device. This function is used for small page
531 * devices (256/512 Bytes per page)
533 static void nand_command(struct mtd_info *mtd, unsigned int command,
534 int column, int page_addr)
536 register struct nand_chip *chip = mtd->priv;
537 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
538 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
541 * Write out the command to the device.
543 if (command == NAND_CMD_SEQIN) {
546 if (column >= mtd->writesize) {
548 column -= mtd->writesize;
549 readcmd = NAND_CMD_READOOB;
550 } else if (column < 256) {
551 /* First 256 bytes --> READ0 */
552 readcmd = NAND_CMD_READ0;
555 readcmd = NAND_CMD_READ1;
557 chip->cmd_ctrl(mtd, readcmd, ctrl);
558 ctrl &= ~NAND_CTRL_CHANGE;
560 chip->cmd_ctrl(mtd, command, ctrl);
563 * Address cycle, when necessary
565 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
566 /* Serially input address */
568 /* Adjust columns for 16 bit buswidth */
569 if (chip->options & NAND_BUSWIDTH_16)
571 chip->cmd_ctrl(mtd, column, ctrl);
572 ctrl &= ~NAND_CTRL_CHANGE;
574 if (page_addr != -1) {
575 chip->cmd_ctrl(mtd, page_addr, ctrl);
576 ctrl &= ~NAND_CTRL_CHANGE;
577 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
578 /* One more address cycle for devices > 32MiB */
579 if (chip->chipsize > (32 << 20))
580 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
582 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
585 * program and erase have their own busy handlers
586 * status and sequential in needs no delay
590 case NAND_CMD_PAGEPROG:
591 case NAND_CMD_ERASE1:
592 case NAND_CMD_ERASE2:
594 case NAND_CMD_STATUS:
600 udelay(chip->chip_delay);
601 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
602 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
604 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
605 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
609 /* This applies to read commands */
612 * If we don't have access to the busy pin, we apply the given
615 if (!chip->dev_ready) {
616 udelay(chip->chip_delay);
620 /* Apply this short delay always to ensure that we do wait tWB in
621 * any case on any machine. */
624 nand_wait_ready(mtd);
628 * nand_command_lp - [DEFAULT] Send command to NAND large page device
629 * @mtd: MTD device structure
630 * @command: the command to be sent
631 * @column: the column address for this command, -1 if none
632 * @page_addr: the page address for this command, -1 if none
634 * Send command to NAND device. This is the version for the new large page
635 * devices We dont have the separate regions as we have in the small page
636 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
638 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
639 int column, int page_addr)
641 register struct nand_chip *chip = mtd->priv;
642 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
644 /* Emulate NAND_CMD_READOOB */
645 if (command == NAND_CMD_READOOB) {
646 column += mtd->writesize;
647 command = NAND_CMD_READ0;
650 /* Command latch cycle */
651 chip->cmd_ctrl(mtd, command & 0xff,
652 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
654 if (column != -1 || page_addr != -1) {
655 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
657 /* Serially input address */
659 /* Adjust columns for 16 bit buswidth */
660 if (chip->options & NAND_BUSWIDTH_16)
662 chip->cmd_ctrl(mtd, column, ctrl);
663 ctrl &= ~NAND_CTRL_CHANGE;
664 chip->cmd_ctrl(mtd, column >> 8, ctrl);
666 if (page_addr != -1) {
667 chip->cmd_ctrl(mtd, page_addr, ctrl);
668 chip->cmd_ctrl(mtd, page_addr >> 8,
669 NAND_NCE | NAND_ALE);
670 /* One more address cycle for devices > 128MiB */
671 if (chip->chipsize > (128 << 20))
672 chip->cmd_ctrl(mtd, page_addr >> 16,
673 NAND_NCE | NAND_ALE);
676 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
679 * program and erase have their own busy handlers
680 * status, sequential in, and deplete1 need no delay
684 case NAND_CMD_CACHEDPROG:
685 case NAND_CMD_PAGEPROG:
686 case NAND_CMD_ERASE1:
687 case NAND_CMD_ERASE2:
690 case NAND_CMD_STATUS:
691 case NAND_CMD_DEPLETE1:
695 * read error status commands require only a short delay
697 case NAND_CMD_STATUS_ERROR:
698 case NAND_CMD_STATUS_ERROR0:
699 case NAND_CMD_STATUS_ERROR1:
700 case NAND_CMD_STATUS_ERROR2:
701 case NAND_CMD_STATUS_ERROR3:
702 udelay(chip->chip_delay);
708 udelay(chip->chip_delay);
709 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
710 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
711 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
712 NAND_NCE | NAND_CTRL_CHANGE);
713 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
717 case NAND_CMD_RNDOUT:
718 /* No ready / busy check necessary */
719 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
720 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
721 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
722 NAND_NCE | NAND_CTRL_CHANGE);
726 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
727 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
728 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
729 NAND_NCE | NAND_CTRL_CHANGE);
731 /* This applies to read commands */
734 * If we don't have access to the busy pin, we apply the given
737 if (!chip->dev_ready) {
738 udelay(chip->chip_delay);
743 /* Apply this short delay always to ensure that we do wait tWB in
744 * any case on any machine. */
747 nand_wait_ready(mtd);
751 * nand_get_device - [GENERIC] Get chip for selected access
752 * @chip: the nand chip descriptor
753 * @mtd: MTD device structure
754 * @new_state: the state which is requested
756 * Get the device and lock it for exclusive access
761 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
763 spinlock_t *lock = &chip->controller->lock;
764 wait_queue_head_t *wq = &chip->controller->wq;
765 DECLARE_WAITQUEUE(wait, current);
769 /* Hardware controller shared among independend devices */
770 /* Hardware controller shared among independend devices */
771 if (!chip->controller->active)
772 chip->controller->active = chip;
774 if (chip->controller->active == chip && chip->state == FL_READY) {
775 chip->state = new_state;
779 if (new_state == FL_PM_SUSPENDED) {
781 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
783 set_current_state(TASK_UNINTERRUPTIBLE);
784 add_wait_queue(wq, &wait);
787 remove_wait_queue(wq, &wait);
791 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
793 this->state = new_state;
799 * nand_wait - [DEFAULT] wait until the command is done
800 * @mtd: MTD device structure
801 * @chip: NAND chip structure
803 * Wait for command done. This applies to erase and program only
804 * Erase can take up to 400ms and program up to 20ms according to
805 * general NAND and SmartMedia specs
809 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
812 unsigned long timeo = jiffies;
813 int status, state = chip->state;
815 if (state == FL_ERASING)
816 timeo += (HZ * 400) / 1000;
818 timeo += (HZ * 20) / 1000;
820 led_trigger_event(nand_led_trigger, LED_FULL);
822 /* Apply this short delay always to ensure that we do wait tWB in
823 * any case on any machine. */
826 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
827 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
829 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
831 while (time_before(jiffies, timeo)) {
832 if (chip->dev_ready) {
833 if (chip->dev_ready(mtd))
836 if (chip->read_byte(mtd) & NAND_STATUS_READY)
841 led_trigger_event(nand_led_trigger, LED_OFF);
843 status = (int)chip->read_byte(mtd);
847 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
850 int state = this->state;
852 if (state == FL_ERASING)
853 timeo = (CONFIG_SYS_HZ * 400) / 1000;
855 timeo = (CONFIG_SYS_HZ * 20) / 1000;
857 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
858 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
860 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
865 if (get_timer(0) > timeo) {
870 if (this->dev_ready) {
871 if (this->dev_ready(mtd))
874 if (this->read_byte(mtd) & NAND_STATUS_READY)
878 #ifdef PPCHAMELON_NAND_TIMER_HACK
880 while (get_timer(0) < 10);
881 #endif /* PPCHAMELON_NAND_TIMER_HACK */
883 return this->read_byte(mtd);
888 * nand_read_page_raw - [Intern] read raw page data without ecc
889 * @mtd: mtd info structure
890 * @chip: nand chip info structure
891 * @buf: buffer to store read data
893 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
896 chip->read_buf(mtd, buf, mtd->writesize);
897 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
902 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
903 * @mtd: mtd info structure
904 * @chip: nand chip info structure
905 * @buf: buffer to store read data
907 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
910 int i, eccsize = chip->ecc.size;
911 int eccbytes = chip->ecc.bytes;
912 int eccsteps = chip->ecc.steps;
914 uint8_t *ecc_calc = chip->buffers->ecccalc;
915 uint8_t *ecc_code = chip->buffers->ecccode;
916 uint32_t *eccpos = chip->ecc.layout->eccpos;
918 chip->ecc.read_page_raw(mtd, chip, buf);
920 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
921 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
923 for (i = 0; i < chip->ecc.total; i++)
924 ecc_code[i] = chip->oob_poi[eccpos[i]];
926 eccsteps = chip->ecc.steps;
929 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
932 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
934 mtd->ecc_stats.failed++;
936 mtd->ecc_stats.corrected += stat;
942 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
943 * @mtd: mtd info structure
944 * @chip: nand chip info structure
945 * @dataofs offset of requested data within the page
946 * @readlen data length
947 * @buf: buffer to store read data
949 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
951 int start_step, end_step, num_steps;
952 uint32_t *eccpos = chip->ecc.layout->eccpos;
954 int data_col_addr, i, gaps = 0;
955 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
956 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
958 /* Column address wihin the page aligned to ECC size (256bytes). */
959 start_step = data_offs / chip->ecc.size;
960 end_step = (data_offs + readlen - 1) / chip->ecc.size;
961 num_steps = end_step - start_step + 1;
963 /* Data size aligned to ECC ecc.size*/
964 datafrag_len = num_steps * chip->ecc.size;
965 eccfrag_len = num_steps * chip->ecc.bytes;
967 data_col_addr = start_step * chip->ecc.size;
968 /* If we read not a page aligned data */
969 if (data_col_addr != 0)
970 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
972 p = bufpoi + data_col_addr;
973 chip->read_buf(mtd, p, datafrag_len);
976 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
977 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
979 /* The performance is faster if to position offsets
980 according to ecc.pos. Let make sure here that
981 there are no gaps in ecc positions */
982 for (i = 0; i < eccfrag_len - 1; i++) {
983 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
984 eccpos[i + start_step * chip->ecc.bytes + 1]) {
990 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
991 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
993 /* send the command to read the particular ecc bytes */
994 /* take care about buswidth alignment in read_buf */
995 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
996 aligned_len = eccfrag_len;
997 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
999 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1002 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1003 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1006 for (i = 0; i < eccfrag_len; i++)
1007 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1009 p = bufpoi + data_col_addr;
1010 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1013 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1015 mtd->ecc_stats.failed++;
1017 mtd->ecc_stats.corrected += stat;
1023 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1024 * @mtd: mtd info structure
1025 * @chip: nand chip info structure
1026 * @buf: buffer to store read data
1028 * Not for syndrome calculating ecc controllers which need a special oob layout
1030 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1033 int i, eccsize = chip->ecc.size;
1034 int eccbytes = chip->ecc.bytes;
1035 int eccsteps = chip->ecc.steps;
1037 uint8_t *ecc_calc = chip->buffers->ecccalc;
1038 uint8_t *ecc_code = chip->buffers->ecccode;
1039 uint32_t *eccpos = chip->ecc.layout->eccpos;
1041 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1042 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1043 chip->read_buf(mtd, p, eccsize);
1044 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1046 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1048 for (i = 0; i < chip->ecc.total; i++)
1049 ecc_code[i] = chip->oob_poi[eccpos[i]];
1051 eccsteps = chip->ecc.steps;
1054 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1057 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1059 mtd->ecc_stats.failed++;
1061 mtd->ecc_stats.corrected += stat;
1067 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1068 * @mtd: mtd info structure
1069 * @chip: nand chip info structure
1070 * @buf: buffer to store read data
1072 * The hw generator calculates the error syndrome automatically. Therefor
1073 * we need a special oob layout and handling.
1075 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1078 int i, eccsize = chip->ecc.size;
1079 int eccbytes = chip->ecc.bytes;
1080 int eccsteps = chip->ecc.steps;
1082 uint8_t *oob = chip->oob_poi;
1084 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1087 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1088 chip->read_buf(mtd, p, eccsize);
1090 if (chip->ecc.prepad) {
1091 chip->read_buf(mtd, oob, chip->ecc.prepad);
1092 oob += chip->ecc.prepad;
1095 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1096 chip->read_buf(mtd, oob, eccbytes);
1097 stat = chip->ecc.correct(mtd, p, oob, NULL);
1100 mtd->ecc_stats.failed++;
1102 mtd->ecc_stats.corrected += stat;
1106 if (chip->ecc.postpad) {
1107 chip->read_buf(mtd, oob, chip->ecc.postpad);
1108 oob += chip->ecc.postpad;
1112 /* Calculate remaining oob bytes */
1113 i = mtd->oobsize - (oob - chip->oob_poi);
1115 chip->read_buf(mtd, oob, i);
1121 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1122 * @chip: nand chip structure
1123 * @oob: oob destination address
1124 * @ops: oob ops structure
1125 * @len: size of oob to transfer
1127 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1128 struct mtd_oob_ops *ops, size_t len)
1134 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1137 case MTD_OOB_AUTO: {
1138 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1139 uint32_t boffs = 0, roffs = ops->ooboffs;
1142 for(; free->length && len; free++, len -= bytes) {
1143 /* Read request not from offset 0 ? */
1144 if (unlikely(roffs)) {
1145 if (roffs >= free->length) {
1146 roffs -= free->length;
1149 boffs = free->offset + roffs;
1150 bytes = min_t(size_t, len,
1151 (free->length - roffs));
1154 bytes = min_t(size_t, len, free->length);
1155 boffs = free->offset;
1157 memcpy(oob, chip->oob_poi + boffs, bytes);
1169 * nand_do_read_ops - [Internal] Read data with ECC
1171 * @mtd: MTD device structure
1172 * @from: offset to read from
1173 * @ops: oob ops structure
1175 * Internal function. Called with chip held.
1177 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1178 struct mtd_oob_ops *ops)
1180 int chipnr, page, realpage, col, bytes, aligned;
1181 struct nand_chip *chip = mtd->priv;
1182 struct mtd_ecc_stats stats;
1183 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1186 uint32_t readlen = ops->len;
1187 uint32_t oobreadlen = ops->ooblen;
1188 uint8_t *bufpoi, *oob, *buf;
1190 stats = mtd->ecc_stats;
1192 chipnr = (int)(from >> chip->chip_shift);
1193 chip->select_chip(mtd, chipnr);
1195 realpage = (int)(from >> chip->page_shift);
1196 page = realpage & chip->pagemask;
1198 col = (int)(from & (mtd->writesize - 1));
1204 bytes = min(mtd->writesize - col, readlen);
1205 aligned = (bytes == mtd->writesize);
1207 /* Is the current page in the buffer ? */
1208 if (realpage != chip->pagebuf || oob) {
1209 bufpoi = aligned ? buf : chip->buffers->databuf;
1211 if (likely(sndcmd)) {
1212 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1216 /* Now read the page into the buffer */
1217 if (unlikely(ops->mode == MTD_OOB_RAW))
1218 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1219 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1220 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1222 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1226 /* Transfer not aligned data */
1228 if (!NAND_SUBPAGE_READ(chip) && !oob)
1229 chip->pagebuf = realpage;
1230 memcpy(buf, chip->buffers->databuf + col, bytes);
1235 if (unlikely(oob)) {
1236 /* Raw mode does data:oob:data:oob */
1237 if (ops->mode != MTD_OOB_RAW) {
1238 int toread = min(oobreadlen,
1239 chip->ecc.layout->oobavail);
1241 oob = nand_transfer_oob(chip,
1243 oobreadlen -= toread;
1246 buf = nand_transfer_oob(chip,
1247 buf, ops, mtd->oobsize);
1250 if (!(chip->options & NAND_NO_READRDY)) {
1252 * Apply delay or wait for ready/busy pin. Do
1253 * this before the AUTOINCR check, so no
1254 * problems arise if a chip which does auto
1255 * increment is marked as NOAUTOINCR by the
1258 if (!chip->dev_ready)
1259 udelay(chip->chip_delay);
1261 nand_wait_ready(mtd);
1264 memcpy(buf, chip->buffers->databuf + col, bytes);
1273 /* For subsequent reads align to page boundary. */
1275 /* Increment page address */
1278 page = realpage & chip->pagemask;
1279 /* Check, if we cross a chip boundary */
1282 chip->select_chip(mtd, -1);
1283 chip->select_chip(mtd, chipnr);
1286 /* Check, if the chip supports auto page increment
1287 * or if we have hit a block boundary.
1289 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1293 ops->retlen = ops->len - (size_t) readlen;
1295 ops->oobretlen = ops->ooblen - oobreadlen;
1300 if (mtd->ecc_stats.failed - stats.failed)
1303 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1307 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1308 * @mtd: MTD device structure
1309 * @from: offset to read from
1310 * @len: number of bytes to read
1311 * @retlen: pointer to variable to store the number of read bytes
1312 * @buf: the databuffer to put data
1314 * Get hold of the chip and call nand_do_read
1316 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1317 size_t *retlen, uint8_t *buf)
1319 struct nand_chip *chip = mtd->priv;
1322 /* Do not allow reads past end of device */
1323 if ((from + len) > mtd->size)
1328 nand_get_device(chip, mtd, FL_READING);
1330 chip->ops.len = len;
1331 chip->ops.datbuf = buf;
1332 chip->ops.oobbuf = NULL;
1334 ret = nand_do_read_ops(mtd, from, &chip->ops);
1336 *retlen = chip->ops.retlen;
1338 nand_release_device(mtd);
1344 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1345 * @mtd: mtd info structure
1346 * @chip: nand chip info structure
1347 * @page: page number to read
1348 * @sndcmd: flag whether to issue read command or not
1350 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1351 int page, int sndcmd)
1354 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1357 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1362 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1364 * @mtd: mtd info structure
1365 * @chip: nand chip info structure
1366 * @page: page number to read
1367 * @sndcmd: flag whether to issue read command or not
1369 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1370 int page, int sndcmd)
1372 uint8_t *buf = chip->oob_poi;
1373 int length = mtd->oobsize;
1374 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1375 int eccsize = chip->ecc.size;
1376 uint8_t *bufpoi = buf;
1377 int i, toread, sndrnd = 0, pos;
1379 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1380 for (i = 0; i < chip->ecc.steps; i++) {
1382 pos = eccsize + i * (eccsize + chunk);
1383 if (mtd->writesize > 512)
1384 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1386 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1389 toread = min_t(int, length, chunk);
1390 chip->read_buf(mtd, bufpoi, toread);
1395 chip->read_buf(mtd, bufpoi, length);
1401 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1402 * @mtd: mtd info structure
1403 * @chip: nand chip info structure
1404 * @page: page number to write
1406 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1410 const uint8_t *buf = chip->oob_poi;
1411 int length = mtd->oobsize;
1413 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1414 chip->write_buf(mtd, buf, length);
1415 /* Send command to program the OOB data */
1416 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1418 status = chip->waitfunc(mtd, chip);
1420 return status & NAND_STATUS_FAIL ? -EIO : 0;
1424 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1425 * with syndrome - only for large page flash !
1426 * @mtd: mtd info structure
1427 * @chip: nand chip info structure
1428 * @page: page number to write
1430 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1431 struct nand_chip *chip, int page)
1433 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1434 int eccsize = chip->ecc.size, length = mtd->oobsize;
1435 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1436 const uint8_t *bufpoi = chip->oob_poi;
1439 * data-ecc-data-ecc ... ecc-oob
1441 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1443 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1444 pos = steps * (eccsize + chunk);
1449 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1450 for (i = 0; i < steps; i++) {
1452 if (mtd->writesize <= 512) {
1453 uint32_t fill = 0xFFFFFFFF;
1457 int num = min_t(int, len, 4);
1458 chip->write_buf(mtd, (uint8_t *)&fill,
1463 pos = eccsize + i * (eccsize + chunk);
1464 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1468 len = min_t(int, length, chunk);
1469 chip->write_buf(mtd, bufpoi, len);
1474 chip->write_buf(mtd, bufpoi, length);
1476 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1477 status = chip->waitfunc(mtd, chip);
1479 return status & NAND_STATUS_FAIL ? -EIO : 0;
1483 * nand_do_read_oob - [Intern] NAND read out-of-band
1484 * @mtd: MTD device structure
1485 * @from: offset to read from
1486 * @ops: oob operations description structure
1488 * NAND read out-of-band data from the spare area
1490 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1491 struct mtd_oob_ops *ops)
1493 int page, realpage, chipnr, sndcmd = 1;
1494 struct nand_chip *chip = mtd->priv;
1495 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1496 int readlen = ops->ooblen;
1498 uint8_t *buf = ops->oobbuf;
1500 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1501 (unsigned long long)from, readlen);
1503 if (ops->mode == MTD_OOB_AUTO)
1504 len = chip->ecc.layout->oobavail;
1508 if (unlikely(ops->ooboffs >= len)) {
1509 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1510 "Attempt to start read outside oob\n");
1514 /* Do not allow reads past end of device */
1515 if (unlikely(from >= mtd->size ||
1516 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1517 (from >> chip->page_shift)) * len)) {
1518 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1519 "Attempt read beyond end of device\n");
1523 chipnr = (int)(from >> chip->chip_shift);
1524 chip->select_chip(mtd, chipnr);
1526 /* Shift to get page */
1527 realpage = (int)(from >> chip->page_shift);
1528 page = realpage & chip->pagemask;
1531 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1533 len = min(len, readlen);
1534 buf = nand_transfer_oob(chip, buf, ops, len);
1536 if (!(chip->options & NAND_NO_READRDY)) {
1538 * Apply delay or wait for ready/busy pin. Do this
1539 * before the AUTOINCR check, so no problems arise if a
1540 * chip which does auto increment is marked as
1541 * NOAUTOINCR by the board driver.
1543 if (!chip->dev_ready)
1544 udelay(chip->chip_delay);
1546 nand_wait_ready(mtd);
1553 /* Increment page address */
1556 page = realpage & chip->pagemask;
1557 /* Check, if we cross a chip boundary */
1560 chip->select_chip(mtd, -1);
1561 chip->select_chip(mtd, chipnr);
1564 /* Check, if the chip supports auto page increment
1565 * or if we have hit a block boundary.
1567 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1571 ops->oobretlen = ops->ooblen;
1576 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1577 * @mtd: MTD device structure
1578 * @from: offset to read from
1579 * @ops: oob operation description structure
1581 * NAND read data and/or out-of-band data
1583 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1584 struct mtd_oob_ops *ops)
1586 struct nand_chip *chip = mtd->priv;
1587 int ret = -ENOTSUPP;
1591 /* Do not allow reads past end of device */
1592 if (ops->datbuf && (from + ops->len) > mtd->size) {
1593 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1594 "Attempt read beyond end of device\n");
1598 nand_get_device(chip, mtd, FL_READING);
1611 ret = nand_do_read_oob(mtd, from, ops);
1613 ret = nand_do_read_ops(mtd, from, ops);
1616 nand_release_device(mtd);
1622 * nand_write_page_raw - [Intern] raw page write function
1623 * @mtd: mtd info structure
1624 * @chip: nand chip info structure
1627 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1630 chip->write_buf(mtd, buf, mtd->writesize);
1631 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1635 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1636 * @mtd: mtd info structure
1637 * @chip: nand chip info structure
1640 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1643 int i, eccsize = chip->ecc.size;
1644 int eccbytes = chip->ecc.bytes;
1645 int eccsteps = chip->ecc.steps;
1646 uint8_t *ecc_calc = chip->buffers->ecccalc;
1647 const uint8_t *p = buf;
1648 uint32_t *eccpos = chip->ecc.layout->eccpos;
1650 /* Software ecc calculation */
1651 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1652 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1654 for (i = 0; i < chip->ecc.total; i++)
1655 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1657 chip->ecc.write_page_raw(mtd, chip, buf);
1661 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1662 * @mtd: mtd info structure
1663 * @chip: nand chip info structure
1666 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1669 int i, eccsize = chip->ecc.size;
1670 int eccbytes = chip->ecc.bytes;
1671 int eccsteps = chip->ecc.steps;
1672 uint8_t *ecc_calc = chip->buffers->ecccalc;
1673 const uint8_t *p = buf;
1674 uint32_t *eccpos = chip->ecc.layout->eccpos;
1676 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1677 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1678 chip->write_buf(mtd, p, eccsize);
1679 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1682 for (i = 0; i < chip->ecc.total; i++)
1683 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1685 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1689 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1690 * @mtd: mtd info structure
1691 * @chip: nand chip info structure
1694 * The hw generator calculates the error syndrome automatically. Therefor
1695 * we need a special oob layout and handling.
1697 static void nand_write_page_syndrome(struct mtd_info *mtd,
1698 struct nand_chip *chip, const uint8_t *buf)
1700 int i, eccsize = chip->ecc.size;
1701 int eccbytes = chip->ecc.bytes;
1702 int eccsteps = chip->ecc.steps;
1703 const uint8_t *p = buf;
1704 uint8_t *oob = chip->oob_poi;
1706 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1708 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1709 chip->write_buf(mtd, p, eccsize);
1711 if (chip->ecc.prepad) {
1712 chip->write_buf(mtd, oob, chip->ecc.prepad);
1713 oob += chip->ecc.prepad;
1716 chip->ecc.calculate(mtd, p, oob);
1717 chip->write_buf(mtd, oob, eccbytes);
1720 if (chip->ecc.postpad) {
1721 chip->write_buf(mtd, oob, chip->ecc.postpad);
1722 oob += chip->ecc.postpad;
1726 /* Calculate remaining oob bytes */
1727 i = mtd->oobsize - (oob - chip->oob_poi);
1729 chip->write_buf(mtd, oob, i);
1733 * nand_write_page - [REPLACEABLE] write one page
1734 * @mtd: MTD device structure
1735 * @chip: NAND chip descriptor
1736 * @buf: the data to write
1737 * @page: page number to write
1738 * @cached: cached programming
1739 * @raw: use _raw version of write_page
1741 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1742 const uint8_t *buf, int page, int cached, int raw)
1746 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1749 chip->ecc.write_page_raw(mtd, chip, buf);
1751 chip->ecc.write_page(mtd, chip, buf);
1754 * Cached progamming disabled for now, Not sure if its worth the
1755 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1759 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1761 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1762 status = chip->waitfunc(mtd, chip);
1764 * See if operation failed and additional status checks are
1767 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1768 status = chip->errstat(mtd, chip, FL_WRITING, status,
1771 if (status & NAND_STATUS_FAIL)
1774 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1775 status = chip->waitfunc(mtd, chip);
1778 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1779 /* Send command to read back the data */
1780 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1782 if (chip->verify_buf(mtd, buf, mtd->writesize))
1789 * nand_fill_oob - [Internal] Transfer client buffer to oob
1790 * @chip: nand chip structure
1791 * @oob: oob data buffer
1792 * @ops: oob ops structure
1794 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1795 struct mtd_oob_ops *ops)
1797 size_t len = ops->ooblen;
1803 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1806 case MTD_OOB_AUTO: {
1807 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1808 uint32_t boffs = 0, woffs = ops->ooboffs;
1811 for(; free->length && len; free++, len -= bytes) {
1812 /* Write request not from offset 0 ? */
1813 if (unlikely(woffs)) {
1814 if (woffs >= free->length) {
1815 woffs -= free->length;
1818 boffs = free->offset + woffs;
1819 bytes = min_t(size_t, len,
1820 (free->length - woffs));
1823 bytes = min_t(size_t, len, free->length);
1824 boffs = free->offset;
1826 memcpy(chip->oob_poi + boffs, oob, bytes);
1837 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1840 * nand_do_write_ops - [Internal] NAND write with ECC
1841 * @mtd: MTD device structure
1842 * @to: offset to write to
1843 * @ops: oob operations description structure
1845 * NAND write with ECC
1847 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1848 struct mtd_oob_ops *ops)
1850 int chipnr, realpage, page, blockmask, column;
1851 struct nand_chip *chip = mtd->priv;
1852 uint32_t writelen = ops->len;
1853 uint8_t *oob = ops->oobbuf;
1854 uint8_t *buf = ops->datbuf;
1861 /* reject writes, which are not page aligned */
1862 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1863 printk(KERN_NOTICE "nand_write: "
1864 "Attempt to write not page aligned data\n");
1868 column = to & (mtd->writesize - 1);
1869 subpage = column || (writelen & (mtd->writesize - 1));
1874 chipnr = (int)(to >> chip->chip_shift);
1875 chip->select_chip(mtd, chipnr);
1877 /* Check, if it is write protected */
1878 if (nand_check_wp(mtd)) {
1879 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1883 realpage = (int)(to >> chip->page_shift);
1884 page = realpage & chip->pagemask;
1885 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1887 /* Invalidate the page cache, when we write to the cached page */
1888 if (to <= (chip->pagebuf << chip->page_shift) &&
1889 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1892 /* If we're not given explicit OOB data, let it be 0xFF */
1894 memset(chip->oob_poi, 0xff, mtd->oobsize);
1897 int bytes = mtd->writesize;
1898 int cached = writelen > bytes && page != blockmask;
1899 uint8_t *wbuf = buf;
1901 /* Partial page write ? */
1902 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1904 bytes = min_t(int, bytes - column, (int) writelen);
1906 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1907 memcpy(&chip->buffers->databuf[column], buf, bytes);
1908 wbuf = chip->buffers->databuf;
1912 oob = nand_fill_oob(chip, oob, ops);
1914 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1915 (ops->mode == MTD_OOB_RAW));
1927 page = realpage & chip->pagemask;
1928 /* Check, if we cross a chip boundary */
1931 chip->select_chip(mtd, -1);
1932 chip->select_chip(mtd, chipnr);
1936 ops->retlen = ops->len - writelen;
1938 ops->oobretlen = ops->ooblen;
1943 * nand_write - [MTD Interface] NAND write with ECC
1944 * @mtd: MTD device structure
1945 * @to: offset to write to
1946 * @len: number of bytes to write
1947 * @retlen: pointer to variable to store the number of written bytes
1948 * @buf: the data to write
1950 * NAND write with ECC
1952 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1953 size_t *retlen, const uint8_t *buf)
1955 struct nand_chip *chip = mtd->priv;
1958 /* Do not allow reads past end of device */
1959 if ((to + len) > mtd->size)
1964 nand_get_device(chip, mtd, FL_WRITING);
1966 chip->ops.len = len;
1967 chip->ops.datbuf = (uint8_t *)buf;
1968 chip->ops.oobbuf = NULL;
1970 ret = nand_do_write_ops(mtd, to, &chip->ops);
1972 *retlen = chip->ops.retlen;
1974 nand_release_device(mtd);
1980 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1981 * @mtd: MTD device structure
1982 * @to: offset to write to
1983 * @ops: oob operation description structure
1985 * NAND write out-of-band
1987 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1988 struct mtd_oob_ops *ops)
1990 int chipnr, page, status, len;
1991 struct nand_chip *chip = mtd->priv;
1993 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1994 (unsigned int)to, (int)ops->ooblen);
1996 if (ops->mode == MTD_OOB_AUTO)
1997 len = chip->ecc.layout->oobavail;
2001 /* Do not allow write past end of page */
2002 if ((ops->ooboffs + ops->ooblen) > len) {
2003 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2004 "Attempt to write past end of page\n");
2008 if (unlikely(ops->ooboffs >= len)) {
2009 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2010 "Attempt to start write outside oob\n");
2014 /* Do not allow reads past end of device */
2015 if (unlikely(to >= mtd->size ||
2016 ops->ooboffs + ops->ooblen >
2017 ((mtd->size >> chip->page_shift) -
2018 (to >> chip->page_shift)) * len)) {
2019 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2020 "Attempt write beyond end of device\n");
2024 chipnr = (int)(to >> chip->chip_shift);
2025 chip->select_chip(mtd, chipnr);
2027 /* Shift to get page */
2028 page = (int)(to >> chip->page_shift);
2031 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2032 * of my DiskOnChip 2000 test units) will clear the whole data page too
2033 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2034 * it in the doc2000 driver in August 1999. dwmw2.
2036 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2038 /* Check, if it is write protected */
2039 if (nand_check_wp(mtd))
2042 /* Invalidate the page cache, if we write to the cached page */
2043 if (page == chip->pagebuf)
2046 memset(chip->oob_poi, 0xff, mtd->oobsize);
2047 nand_fill_oob(chip, ops->oobbuf, ops);
2048 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2049 memset(chip->oob_poi, 0xff, mtd->oobsize);
2054 ops->oobretlen = ops->ooblen;
2060 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2061 * @mtd: MTD device structure
2062 * @to: offset to write to
2063 * @ops: oob operation description structure
2065 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2066 struct mtd_oob_ops *ops)
2068 struct nand_chip *chip = mtd->priv;
2069 int ret = -ENOTSUPP;
2073 /* Do not allow writes past end of device */
2074 if (ops->datbuf && (to + ops->len) > mtd->size) {
2075 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2076 "Attempt read beyond end of device\n");
2080 nand_get_device(chip, mtd, FL_WRITING);
2093 ret = nand_do_write_oob(mtd, to, ops);
2095 ret = nand_do_write_ops(mtd, to, ops);
2098 nand_release_device(mtd);
2103 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2104 * @mtd: MTD device structure
2105 * @page: the page address of the block which will be erased
2107 * Standard erase command for NAND chips
2109 static void single_erase_cmd(struct mtd_info *mtd, int page)
2111 struct nand_chip *chip = mtd->priv;
2112 /* Send commands to erase a block */
2113 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2114 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2118 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2119 * @mtd: MTD device structure
2120 * @page: the page address of the block which will be erased
2122 * AND multi block erase command function
2123 * Erase 4 consecutive blocks
2125 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2127 struct nand_chip *chip = mtd->priv;
2128 /* Send commands to erase a block */
2129 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2130 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2131 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2132 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2133 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2137 * nand_erase - [MTD Interface] erase block(s)
2138 * @mtd: MTD device structure
2139 * @instr: erase instruction
2141 * Erase one ore more blocks
2143 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2145 return nand_erase_nand(mtd, instr, 0);
2148 #define BBT_PAGE_MASK 0xffffff3f
2150 * nand_erase_nand - [Internal] erase block(s)
2151 * @mtd: MTD device structure
2152 * @instr: erase instruction
2153 * @allowbbt: allow erasing the bbt area
2155 * Erase one ore more blocks
2157 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2160 int page, len, status, pages_per_block, ret, chipnr;
2161 struct nand_chip *chip = mtd->priv;
2162 int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0};
2163 unsigned int bbt_masked_page = 0xffffffff;
2165 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2166 (unsigned int) instr->addr, (unsigned int) instr->len);
2168 /* Start address must align on block boundary */
2169 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2170 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2174 /* Length must align on block boundary */
2175 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2176 MTDDEBUG (MTD_DEBUG_LEVEL0,
2177 "nand_erase: Length not block aligned\n");
2181 /* Do not allow erase past end of device */
2182 if ((instr->len + instr->addr) > mtd->size) {
2183 MTDDEBUG (MTD_DEBUG_LEVEL0,
2184 "nand_erase: Erase past end of device\n");
2188 instr->fail_addr = 0xffffffff;
2190 /* Grab the lock and see if the device is available */
2191 nand_get_device(chip, mtd, FL_ERASING);
2193 /* Shift to get first page */
2194 page = (int)(instr->addr >> chip->page_shift);
2195 chipnr = (int)(instr->addr >> chip->chip_shift);
2197 /* Calculate pages in each block */
2198 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2200 /* Select the NAND device */
2201 chip->select_chip(mtd, chipnr);
2203 /* Check, if it is write protected */
2204 if (nand_check_wp(mtd)) {
2205 MTDDEBUG (MTD_DEBUG_LEVEL0,
2206 "nand_erase: Device is write protected!!!\n");
2207 instr->state = MTD_ERASE_FAILED;
2212 * If BBT requires refresh, set the BBT page mask to see if the BBT
2213 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2214 * can not be matched. This is also done when the bbt is actually
2215 * erased to avoid recusrsive updates
2217 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2218 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2220 /* Loop through the pages */
2223 instr->state = MTD_ERASING;
2227 * heck if we have a bad block, we do not erase bad blocks !
2229 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2230 chip->page_shift, 0, allowbbt)) {
2231 printk(KERN_WARNING "nand_erase: attempt to erase a "
2232 "bad block at page 0x%08x\n", page);
2233 instr->state = MTD_ERASE_FAILED;
2238 * Invalidate the page cache, if we erase the block which
2239 * contains the current cached page
2241 if (page <= chip->pagebuf && chip->pagebuf <
2242 (page + pages_per_block))
2245 chip->erase_cmd(mtd, page & chip->pagemask);
2247 status = chip->waitfunc(mtd, chip);
2250 * See if operation failed and additional status checks are
2253 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2254 status = chip->errstat(mtd, chip, FL_ERASING,
2257 /* See if block erase succeeded */
2258 if (status & NAND_STATUS_FAIL) {
2259 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2260 "Failed erase, page 0x%08x\n", page);
2261 instr->state = MTD_ERASE_FAILED;
2262 instr->fail_addr = (page << chip->page_shift);
2267 * If BBT requires refresh, set the BBT rewrite flag to the
2270 if (bbt_masked_page != 0xffffffff &&
2271 (page & BBT_PAGE_MASK) == bbt_masked_page)
2272 rewrite_bbt[chipnr] = (page << chip->page_shift);
2274 /* Increment page address and decrement length */
2275 len -= (1 << chip->phys_erase_shift);
2276 page += pages_per_block;
2278 /* Check, if we cross a chip boundary */
2279 if (len && !(page & chip->pagemask)) {
2281 chip->select_chip(mtd, -1);
2282 chip->select_chip(mtd, chipnr);
2285 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2286 * page mask to see if this BBT should be rewritten
2288 if (bbt_masked_page != 0xffffffff &&
2289 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2290 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2294 instr->state = MTD_ERASE_DONE;
2298 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2300 /* Deselect and wake up anyone waiting on the device */
2301 nand_release_device(mtd);
2303 /* Do call back function */
2305 mtd_erase_callback(instr);
2308 * If BBT requires refresh and erase was successful, rewrite any
2309 * selected bad block tables
2311 if (bbt_masked_page == 0xffffffff || ret)
2314 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2315 if (!rewrite_bbt[chipnr])
2317 /* update the BBT for chip */
2318 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2319 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2320 chip->bbt_td->pages[chipnr]);
2321 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2324 /* Return more or less happy */
2329 * nand_sync - [MTD Interface] sync
2330 * @mtd: MTD device structure
2332 * Sync is actually a wait for chip ready function
2334 static void nand_sync(struct mtd_info *mtd)
2336 struct nand_chip *chip = mtd->priv;
2338 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2340 /* Grab the lock and see if the device is available */
2341 nand_get_device(chip, mtd, FL_SYNCING);
2342 /* Release it and go back */
2343 nand_release_device(mtd);
2347 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2348 * @mtd: MTD device structure
2349 * @offs: offset relative to mtd start
2351 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2353 /* Check for invalid offset */
2354 if (offs > mtd->size)
2357 return nand_block_checkbad(mtd, offs, 1, 0);
2361 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2362 * @mtd: MTD device structure
2363 * @ofs: offset relative to mtd start
2365 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2367 struct nand_chip *chip = mtd->priv;
2370 if ((ret = nand_block_isbad(mtd, ofs))) {
2371 /* If it was bad already, return success and do nothing. */
2377 return chip->block_markbad(mtd, ofs);
2381 * nand_suspend - [MTD Interface] Suspend the NAND flash
2382 * @mtd: MTD device structure
2384 static int nand_suspend(struct mtd_info *mtd)
2386 struct nand_chip *chip = mtd->priv;
2388 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2392 * nand_resume - [MTD Interface] Resume the NAND flash
2393 * @mtd: MTD device structure
2395 static void nand_resume(struct mtd_info *mtd)
2397 struct nand_chip *chip = mtd->priv;
2399 if (chip->state == FL_PM_SUSPENDED)
2400 nand_release_device(mtd);
2402 printk(KERN_ERR "nand_resume() called for a chip which is not "
2403 "in suspended state\n");
2407 * Set default functions
2409 static void nand_set_defaults(struct nand_chip *chip, int busw)
2411 /* check for proper chip_delay setup, set 20us if not */
2412 if (!chip->chip_delay)
2413 chip->chip_delay = 20;
2415 /* check, if a user supplied command function given */
2416 if (chip->cmdfunc == NULL)
2417 chip->cmdfunc = nand_command;
2419 /* check, if a user supplied wait function given */
2420 if (chip->waitfunc == NULL)
2421 chip->waitfunc = nand_wait;
2423 if (!chip->select_chip)
2424 chip->select_chip = nand_select_chip;
2425 if (!chip->read_byte)
2426 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2427 if (!chip->read_word)
2428 chip->read_word = nand_read_word;
2429 if (!chip->block_bad)
2430 chip->block_bad = nand_block_bad;
2431 if (!chip->block_markbad)
2432 chip->block_markbad = nand_default_block_markbad;
2433 if (!chip->write_buf)
2434 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2435 if (!chip->read_buf)
2436 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2437 if (!chip->verify_buf)
2438 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2439 if (!chip->scan_bbt)
2440 chip->scan_bbt = nand_default_bbt;
2442 if (!chip->controller) {
2443 chip->controller = &chip->hwcontrol;
2445 /* XXX U-BOOT XXX */
2447 spin_lock_init(&chip->controller->lock);
2448 init_waitqueue_head(&chip->controller->wq);
2455 * Get the flash and manufacturer id and lookup if the type is supported
2457 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2458 struct nand_chip *chip,
2459 int busw, int *maf_id)
2461 struct nand_flash_dev *type = NULL;
2462 int i, dev_id, maf_idx;
2463 int tmp_id, tmp_manf;
2465 /* Select the device */
2466 chip->select_chip(mtd, 0);
2469 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2472 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2474 /* Send the command for reading device ID */
2475 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2477 /* Read manufacturer and device IDs */
2478 *maf_id = chip->read_byte(mtd);
2479 dev_id = chip->read_byte(mtd);
2481 /* Try again to make sure, as some systems the bus-hold or other
2482 * interface concerns can cause random data which looks like a
2483 * possibly credible NAND flash to appear. If the two results do
2484 * not match, ignore the device completely.
2487 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2489 /* Read manufacturer and device IDs */
2491 tmp_manf = chip->read_byte(mtd);
2492 tmp_id = chip->read_byte(mtd);
2494 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2495 printk(KERN_INFO "%s: second ID read did not match "
2496 "%02x,%02x against %02x,%02x\n", __func__,
2497 *maf_id, dev_id, tmp_manf, tmp_id);
2498 return ERR_PTR(-ENODEV);
2501 /* Lookup the flash id */
2502 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2503 if (dev_id == nand_flash_ids[i].id) {
2504 type = &nand_flash_ids[i];
2510 return ERR_PTR(-ENODEV);
2513 mtd->name = type->name;
2515 chip->chipsize = type->chipsize << 20;
2517 /* Newer devices have all the information in additional id bytes */
2518 if (!type->pagesize) {
2520 /* The 3rd id byte holds MLC / multichip data */
2521 chip->cellinfo = chip->read_byte(mtd);
2522 /* The 4th id byte is the important one */
2523 extid = chip->read_byte(mtd);
2525 mtd->writesize = 1024 << (extid & 0x3);
2528 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2530 /* Calc blocksize. Blocksize is multiples of 64KiB */
2531 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2533 /* Get buswidth information */
2534 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2538 * Old devices have chip data hardcoded in the device id table
2540 mtd->erasesize = type->erasesize;
2541 mtd->writesize = type->pagesize;
2542 mtd->oobsize = mtd->writesize / 32;
2543 busw = type->options & NAND_BUSWIDTH_16;
2546 /* Try to identify manufacturer */
2547 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2548 if (nand_manuf_ids[maf_idx].id == *maf_id)
2553 * Check, if buswidth is correct. Hardware drivers should set
2556 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2557 printk(KERN_INFO "NAND device: Manufacturer ID:"
2558 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2559 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2560 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2561 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2563 return ERR_PTR(-EINVAL);
2566 /* Calculate the address shift from the page size */
2567 chip->page_shift = ffs(mtd->writesize) - 1;
2568 /* Convert chipsize to number of pages per chip -1. */
2569 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2571 chip->bbt_erase_shift = chip->phys_erase_shift =
2572 ffs(mtd->erasesize) - 1;
2573 chip->chip_shift = ffs(chip->chipsize) - 1;
2575 /* Set the bad block position */
2576 chip->badblockpos = mtd->writesize > 512 ?
2577 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2579 /* Get chip options, preserve non chip based options */
2580 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2581 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2584 * Set chip as a default. Board drivers can override it, if necessary
2586 chip->options |= NAND_NO_AUTOINCR;
2588 /* Check if chip is a not a samsung device. Do not clear the
2589 * options for chips which are not having an extended id.
2591 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2592 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2594 /* Check for AND chips with 4 page planes */
2595 if (chip->options & NAND_4PAGE_ARRAY)
2596 chip->erase_cmd = multi_erase_cmd;
2598 chip->erase_cmd = single_erase_cmd;
2600 /* Do not replace user supplied command function ! */
2601 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2602 chip->cmdfunc = nand_command_lp;
2604 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2605 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2606 nand_manuf_ids[maf_idx].name, type->name);
2612 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2613 * @mtd: MTD device structure
2614 * @maxchips: Number of chips to scan for
2616 * This is the first phase of the normal nand_scan() function. It
2617 * reads the flash ID and sets up MTD fields accordingly.
2619 * The mtd->owner field must be set to the module of the caller.
2621 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2623 int i, busw, nand_maf_id;
2624 struct nand_chip *chip = mtd->priv;
2625 struct nand_flash_dev *type;
2627 /* Get buswidth to select the correct functions */
2628 busw = chip->options & NAND_BUSWIDTH_16;
2629 /* Set the default functions */
2630 nand_set_defaults(chip, busw);
2632 /* Read the flash type */
2633 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2636 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2637 printk(KERN_WARNING "No NAND device found!!!\n");
2639 chip->select_chip(mtd, -1);
2640 return PTR_ERR(type);
2643 /* Check for a chip array */
2644 for (i = 1; i < maxchips; i++) {
2645 chip->select_chip(mtd, i);
2646 /* See comment in nand_get_flash_type for reset */
2647 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2648 /* Send the command for reading device ID */
2649 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2650 /* Read manufacturer and device IDs */
2651 if (nand_maf_id != chip->read_byte(mtd) ||
2652 type->id != chip->read_byte(mtd))
2657 printk(KERN_INFO "%d NAND chips detected\n", i);
2660 /* Store the number of chips and calc total size for mtd */
2662 mtd->size = i * chip->chipsize;
2669 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2670 * @mtd: MTD device structure
2671 * @maxchips: Number of chips to scan for
2673 * This is the second phase of the normal nand_scan() function. It
2674 * fills out all the uninitialized function pointers with the defaults
2675 * and scans for a bad block table if appropriate.
2677 int nand_scan_tail(struct mtd_info *mtd)
2680 struct nand_chip *chip = mtd->priv;
2682 if (!(chip->options & NAND_OWN_BUFFERS))
2683 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2687 /* Set the internal oob buffer location, just after the page data */
2688 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2691 * If no default placement scheme is given, select an appropriate one
2693 if (!chip->ecc.layout) {
2694 switch (mtd->oobsize) {
2696 chip->ecc.layout = &nand_oob_8;
2699 chip->ecc.layout = &nand_oob_16;
2702 chip->ecc.layout = &nand_oob_64;
2705 chip->ecc.layout = &nand_oob_128;
2708 printk(KERN_WARNING "No oob scheme defined for "
2709 "oobsize %d\n", mtd->oobsize);
2714 if (!chip->write_page)
2715 chip->write_page = nand_write_page;
2718 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2719 * selected and we have 256 byte pagesize fallback to software ECC
2721 if (!chip->ecc.read_page_raw)
2722 chip->ecc.read_page_raw = nand_read_page_raw;
2723 if (!chip->ecc.write_page_raw)
2724 chip->ecc.write_page_raw = nand_write_page_raw;
2726 switch (chip->ecc.mode) {
2728 /* Use standard hwecc read page function ? */
2729 if (!chip->ecc.read_page)
2730 chip->ecc.read_page = nand_read_page_hwecc;
2731 if (!chip->ecc.write_page)
2732 chip->ecc.write_page = nand_write_page_hwecc;
2733 if (!chip->ecc.read_oob)
2734 chip->ecc.read_oob = nand_read_oob_std;
2735 if (!chip->ecc.write_oob)
2736 chip->ecc.write_oob = nand_write_oob_std;
2738 case NAND_ECC_HW_SYNDROME:
2739 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2740 !chip->ecc.hwctl) &&
2741 (!chip->ecc.read_page ||
2742 chip->ecc.read_page == nand_read_page_hwecc ||
2743 !chip->ecc.write_page ||
2744 chip->ecc.write_page == nand_write_page_hwecc)) {
2745 printk(KERN_WARNING "No ECC functions supplied, "
2746 "Hardware ECC not possible\n");
2749 /* Use standard syndrome read/write page function ? */
2750 if (!chip->ecc.read_page)
2751 chip->ecc.read_page = nand_read_page_syndrome;
2752 if (!chip->ecc.write_page)
2753 chip->ecc.write_page = nand_write_page_syndrome;
2754 if (!chip->ecc.read_oob)
2755 chip->ecc.read_oob = nand_read_oob_syndrome;
2756 if (!chip->ecc.write_oob)
2757 chip->ecc.write_oob = nand_write_oob_syndrome;
2759 if (mtd->writesize >= chip->ecc.size)
2761 printk(KERN_WARNING "%d byte HW ECC not possible on "
2762 "%d byte page size, fallback to SW ECC\n",
2763 chip->ecc.size, mtd->writesize);
2764 chip->ecc.mode = NAND_ECC_SOFT;
2767 chip->ecc.calculate = nand_calculate_ecc;
2768 chip->ecc.correct = nand_correct_data;
2769 chip->ecc.read_page = nand_read_page_swecc;
2770 chip->ecc.read_subpage = nand_read_subpage;
2771 chip->ecc.write_page = nand_write_page_swecc;
2772 chip->ecc.read_oob = nand_read_oob_std;
2773 chip->ecc.write_oob = nand_write_oob_std;
2774 chip->ecc.size = 256;
2775 chip->ecc.bytes = 3;
2779 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2780 "This is not recommended !!\n");
2781 chip->ecc.read_page = nand_read_page_raw;
2782 chip->ecc.write_page = nand_write_page_raw;
2783 chip->ecc.read_oob = nand_read_oob_std;
2784 chip->ecc.write_oob = nand_write_oob_std;
2785 chip->ecc.size = mtd->writesize;
2786 chip->ecc.bytes = 0;
2790 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2796 * The number of bytes available for a client to place data into
2797 * the out of band area
2799 chip->ecc.layout->oobavail = 0;
2800 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2801 chip->ecc.layout->oobavail +=
2802 chip->ecc.layout->oobfree[i].length;
2803 mtd->oobavail = chip->ecc.layout->oobavail;
2806 * Set the number of read / write steps for one page depending on ECC
2809 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2810 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2811 printk(KERN_WARNING "Invalid ecc parameters\n");
2814 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2817 * Allow subpage writes up to ecc.steps. Not possible for MLC
2820 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2821 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2822 switch(chip->ecc.steps) {
2824 mtd->subpage_sft = 1;
2828 mtd->subpage_sft = 2;
2832 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2834 /* Initialize state */
2835 chip->state = FL_READY;
2837 /* De-select the device */
2838 chip->select_chip(mtd, -1);
2840 /* Invalidate the pagebuffer reference */
2843 /* Fill in remaining MTD driver data */
2844 mtd->type = MTD_NANDFLASH;
2845 mtd->flags = MTD_CAP_NANDFLASH;
2846 mtd->erase = nand_erase;
2848 mtd->unpoint = NULL;
2849 mtd->read = nand_read;
2850 mtd->write = nand_write;
2851 mtd->read_oob = nand_read_oob;
2852 mtd->write_oob = nand_write_oob;
2853 mtd->sync = nand_sync;
2856 mtd->suspend = nand_suspend;
2857 mtd->resume = nand_resume;
2858 mtd->block_isbad = nand_block_isbad;
2859 mtd->block_markbad = nand_block_markbad;
2861 /* propagate ecc.layout to mtd_info */
2862 mtd->ecclayout = chip->ecc.layout;
2864 /* Check, if we should skip the bad block table scan */
2865 if (chip->options & NAND_SKIP_BBTSCAN)
2866 chip->options |= NAND_BBT_SCANNED;
2871 /* module_text_address() isn't exported, and it's mostly a pointless
2872 test if this is a module _anyway_ -- they'd have to try _really_ hard
2873 to call us from in-kernel code if the core NAND support is modular. */
2875 #define caller_is_module() (1)
2877 #define caller_is_module() \
2878 module_text_address((unsigned long)__builtin_return_address(0))
2882 * nand_scan - [NAND Interface] Scan for the NAND device
2883 * @mtd: MTD device structure
2884 * @maxchips: Number of chips to scan for
2886 * This fills out all the uninitialized function pointers
2887 * with the defaults.
2888 * The flash ID is read and the mtd/chip structures are
2889 * filled with the appropriate values.
2890 * The mtd->owner field must be set to the module of the caller
2893 int nand_scan(struct mtd_info *mtd, int maxchips)
2897 /* Many callers got this wrong, so check for it for a while... */
2898 /* XXX U-BOOT XXX */
2900 if (!mtd->owner && caller_is_module()) {
2901 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2906 ret = nand_scan_ident(mtd, maxchips);
2908 ret = nand_scan_tail(mtd);
2913 * nand_release - [NAND Interface] Free resources held by the NAND device
2914 * @mtd: MTD device structure
2916 void nand_release(struct mtd_info *mtd)
2918 struct nand_chip *chip = mtd->priv;
2920 #ifdef CONFIG_MTD_PARTITIONS
2921 /* Deregister partitions */
2922 del_mtd_partitions(mtd);
2924 /* Deregister the device */
2925 /* XXX U-BOOT XXX */
2927 del_mtd_device(mtd);
2930 /* Free bad block table memory */
2932 if (!(chip->options & NAND_OWN_BUFFERS))
2933 kfree(chip->buffers);
2936 /* XXX U-BOOT XXX */
2938 EXPORT_SYMBOL_GPL(nand_scan);
2939 EXPORT_SYMBOL_GPL(nand_scan_ident);
2940 EXPORT_SYMBOL_GPL(nand_scan_tail);
2941 EXPORT_SYMBOL_GPL(nand_release);
2943 static int __init nand_base_init(void)
2945 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2949 static void __exit nand_base_exit(void)
2951 led_trigger_unregister_simple(nand_led_trigger);
2954 module_init(nand_base_init);
2955 module_exit(nand_base_exit);
2957 MODULE_LICENSE("GPL");
2958 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2959 MODULE_DESCRIPTION("Generic NAND flash driver code");