5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
34 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/errno.h>
39 #include <linux/err.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/types.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/nand_bch.h>
47 #include <linux/interrupt.h>
48 #include <linux/bitops.h>
49 #include <linux/leds.h>
51 #include <linux/mtd/partitions.h>
53 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
57 #include <linux/err.h>
58 #include <linux/compat.h>
59 #include <linux/mtd/mtd.h>
60 #include <linux/mtd/nand.h>
61 #include <linux/mtd/nand_ecc.h>
62 #include <linux/mtd/nand_bch.h>
63 #ifdef CONFIG_MTD_PARTITIONS
64 #include <linux/mtd/partitions.h>
67 #include <asm/errno.h>
70 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
71 * a flash. NAND flash is initialized prior to interrupts so standard timers
72 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
73 * which is greater than (max NAND reset time / NAND status read time).
74 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
76 #ifndef CONFIG_SYS_NAND_RESET_CNT
77 #define CONFIG_SYS_NAND_RESET_CNT 200000
80 static bool is_module_text_address(unsigned long addr) {return 0;}
83 /* Define default oob placement schemes for large and small page devices */
84 static struct nand_ecclayout nand_oob_8 = {
94 static struct nand_ecclayout nand_oob_16 = {
96 .eccpos = {0, 1, 2, 3, 6, 7},
102 static struct nand_ecclayout nand_oob_64 = {
105 40, 41, 42, 43, 44, 45, 46, 47,
106 48, 49, 50, 51, 52, 53, 54, 55,
107 56, 57, 58, 59, 60, 61, 62, 63},
113 static struct nand_ecclayout nand_oob_128 = {
116 80, 81, 82, 83, 84, 85, 86, 87,
117 88, 89, 90, 91, 92, 93, 94, 95,
118 96, 97, 98, 99, 100, 101, 102, 103,
119 104, 105, 106, 107, 108, 109, 110, 111,
120 112, 113, 114, 115, 116, 117, 118, 119,
121 120, 121, 122, 123, 124, 125, 126, 127},
127 static int nand_get_device(struct mtd_info *mtd, int new_state);
129 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
130 struct mtd_oob_ops *ops);
133 * For devices which display every fart in the system on a separate LED. Is
134 * compiled away when LED support is disabled.
136 DEFINE_LED_TRIGGER(nand_led_trigger);
138 static int check_offs_len(struct mtd_info *mtd,
139 loff_t ofs, uint64_t len)
141 struct nand_chip *chip = mtd->priv;
144 /* Start address must align on block boundary */
145 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
146 pr_debug("%s: unaligned address\n", __func__);
150 /* Length must align on block boundary */
151 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
152 pr_debug("%s: length not block aligned\n", __func__);
160 * nand_release_device - [GENERIC] release chip
161 * @mtd: MTD device structure
163 * Release chip lock and wake up anyone waiting on the device.
165 static void nand_release_device(struct mtd_info *mtd)
167 struct nand_chip *chip = mtd->priv;
170 /* Release the controller and the chip */
171 spin_lock(&chip->controller->lock);
172 chip->controller->active = NULL;
173 chip->state = FL_READY;
174 wake_up(&chip->controller->wq);
175 spin_unlock(&chip->controller->lock);
177 /* De-select the NAND device */
178 chip->select_chip(mtd, -1);
183 * nand_read_byte - [DEFAULT] read one byte from the chip
184 * @mtd: MTD device structure
186 * Default read function for 8bit buswidth
189 static uint8_t nand_read_byte(struct mtd_info *mtd)
191 uint8_t nand_read_byte(struct mtd_info *mtd)
194 struct nand_chip *chip = mtd->priv;
195 return readb(chip->IO_ADDR_R);
199 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
200 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
201 * @mtd: MTD device structure
203 * Default read function for 16bit buswidth with endianness conversion.
206 static uint8_t nand_read_byte16(struct mtd_info *mtd)
208 struct nand_chip *chip = mtd->priv;
209 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
213 * nand_read_word - [DEFAULT] read one word from the chip
214 * @mtd: MTD device structure
216 * Default read function for 16bit buswidth without endianness conversion.
218 static u16 nand_read_word(struct mtd_info *mtd)
220 struct nand_chip *chip = mtd->priv;
221 return readw(chip->IO_ADDR_R);
225 * nand_select_chip - [DEFAULT] control CE line
226 * @mtd: MTD device structure
227 * @chipnr: chipnumber to select, -1 for deselect
229 * Default select function for 1 chip devices.
231 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
233 struct nand_chip *chip = mtd->priv;
237 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
248 * nand_write_byte - [DEFAULT] write single byte to chip
249 * @mtd: MTD device structure
250 * @byte: value to write
252 * Default function to write a byte to I/O[7:0]
254 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
256 struct nand_chip *chip = mtd->priv;
258 chip->write_buf(mtd, &byte, 1);
262 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
263 * @mtd: MTD device structure
264 * @byte: value to write
266 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
268 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
270 struct nand_chip *chip = mtd->priv;
271 uint16_t word = byte;
274 * It's not entirely clear what should happen to I/O[15:8] when writing
275 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
277 * When the host supports a 16-bit bus width, only data is
278 * transferred at the 16-bit width. All address and command line
279 * transfers shall use only the lower 8-bits of the data bus. During
280 * command transfers, the host may place any value on the upper
281 * 8-bits of the data bus. During address transfers, the host shall
282 * set the upper 8-bits of the data bus to 00h.
284 * One user of the write_byte callback is nand_onfi_set_features. The
285 * four parameters are specified to be written to I/O[7:0], but this is
286 * neither an address nor a command transfer. Let's assume a 0 on the
287 * upper I/O lines is OK.
289 chip->write_buf(mtd, (uint8_t *)&word, 2);
292 #if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN)
293 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
297 for (i = 0; i < len; i++)
298 writeb(buf[i], addr);
300 static void ioread8_rep(void *addr, uint8_t *buf, int len)
304 for (i = 0; i < len; i++)
305 buf[i] = readb(addr);
308 static void ioread16_rep(void *addr, void *buf, int len)
311 u16 *p = (u16 *) buf;
314 for (i = 0; i < len; i++)
318 static void iowrite16_rep(void *addr, void *buf, int len)
321 u16 *p = (u16 *) buf;
324 for (i = 0; i < len; i++)
330 * nand_write_buf - [DEFAULT] write buffer to chip
331 * @mtd: MTD device structure
333 * @len: number of bytes to write
335 * Default write function for 8bit buswidth.
338 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
340 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
343 struct nand_chip *chip = mtd->priv;
345 iowrite8_rep(chip->IO_ADDR_W, buf, len);
349 * nand_read_buf - [DEFAULT] read chip data into buffer
350 * @mtd: MTD device structure
351 * @buf: buffer to store date
352 * @len: number of bytes to read
354 * Default read function for 8bit buswidth.
357 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
359 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
362 struct nand_chip *chip = mtd->priv;
364 ioread8_rep(chip->IO_ADDR_R, buf, len);
368 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
370 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
371 * @mtd: MTD device structure
372 * @buf: buffer containing the data to compare
373 * @len: number of bytes to compare
375 * Default verify function for 8bit buswidth.
377 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
380 struct nand_chip *chip = mtd->priv;
382 for (i = 0; i < len; i++)
383 if (buf[i] != readb(chip->IO_ADDR_R))
389 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
390 * @mtd: MTD device structure
391 * @buf: buffer containing the data to compare
392 * @len: number of bytes to compare
394 * Default verify function for 16bit buswidth.
396 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
399 struct nand_chip *chip = mtd->priv;
400 u16 *p = (u16 *) buf;
403 for (i = 0; i < len; i++)
404 if (p[i] != readw(chip->IO_ADDR_R))
413 * nand_write_buf16 - [DEFAULT] write buffer to chip
414 * @mtd: MTD device structure
416 * @len: number of bytes to write
418 * Default write function for 16bit buswidth.
421 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
423 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
426 struct nand_chip *chip = mtd->priv;
427 u16 *p = (u16 *) buf;
429 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
433 * nand_read_buf16 - [DEFAULT] read chip data into buffer
434 * @mtd: MTD device structure
435 * @buf: buffer to store date
436 * @len: number of bytes to read
438 * Default read function for 16bit buswidth.
441 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
443 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
446 struct nand_chip *chip = mtd->priv;
447 u16 *p = (u16 *) buf;
449 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
453 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
454 * @mtd: MTD device structure
455 * @ofs: offset from device start
456 * @getchip: 0, if the chip is already selected
458 * Check, if the block is bad.
460 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
462 int page, chipnr, res = 0, i = 0;
463 struct nand_chip *chip = mtd->priv;
466 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
467 ofs += mtd->erasesize - mtd->writesize;
469 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
472 chipnr = (int)(ofs >> chip->chip_shift);
474 nand_get_device(mtd, FL_READING);
476 /* Select the NAND device */
477 chip->select_chip(mtd, chipnr);
481 if (chip->options & NAND_BUSWIDTH_16) {
482 chip->cmdfunc(mtd, NAND_CMD_READOOB,
483 chip->badblockpos & 0xFE, page);
484 bad = cpu_to_le16(chip->read_word(mtd));
485 if (chip->badblockpos & 0x1)
490 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
492 bad = chip->read_byte(mtd);
495 if (likely(chip->badblockbits == 8))
498 res = hweight8(bad) < chip->badblockbits;
499 ofs += mtd->writesize;
500 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
502 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
505 chip->select_chip(mtd, -1);
506 nand_release_device(mtd);
513 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
514 * @mtd: MTD device structure
515 * @ofs: offset from device start
517 * This is the default implementation, which can be overridden by a hardware
518 * specific driver. It provides the details for writing a bad block marker to a
521 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
523 struct nand_chip *chip = mtd->priv;
524 struct mtd_oob_ops ops;
525 uint8_t buf[2] = { 0, 0 };
526 int ret = 0, res, i = 0;
530 ops.ooboffs = chip->badblockpos;
531 if (chip->options & NAND_BUSWIDTH_16) {
532 ops.ooboffs &= ~0x01;
533 ops.len = ops.ooblen = 2;
535 ops.len = ops.ooblen = 1;
537 ops.mode = MTD_OPS_PLACE_OOB;
539 /* Write to first/last page(s) if necessary */
540 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
541 ofs += mtd->erasesize - mtd->writesize;
543 res = nand_do_write_oob(mtd, ofs, &ops);
548 ofs += mtd->writesize;
549 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
555 * nand_block_markbad_lowlevel - mark a block bad
556 * @mtd: MTD device structure
557 * @ofs: offset from device start
559 * This function performs the generic NAND bad block marking steps (i.e., bad
560 * block table(s) and/or marker(s)). We only allow the hardware driver to
561 * specify how to write bad block markers to OOB (chip->block_markbad).
563 * We try operations in the following order:
564 * (1) erase the affected block, to allow OOB marker to be written cleanly
565 * (2) write bad block marker to OOB area of affected block (unless flag
566 * NAND_BBT_NO_OOB_BBM is present)
568 * Note that we retain the first error encountered in (2) or (3), finish the
569 * procedures, and dump the error in the end.
571 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
573 struct nand_chip *chip = mtd->priv;
576 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
577 struct erase_info einfo;
579 /* Attempt erase before marking OOB */
580 memset(&einfo, 0, sizeof(einfo));
583 einfo.len = 1ULL << chip->phys_erase_shift;
584 nand_erase_nand(mtd, &einfo, 0);
586 /* Write bad block marker to OOB */
587 nand_get_device(mtd, FL_WRITING);
588 ret = chip->block_markbad(mtd, ofs);
589 nand_release_device(mtd);
592 /* Mark block bad in BBT */
594 res = nand_markbad_bbt(mtd, ofs);
600 mtd->ecc_stats.badblocks++;
606 * nand_check_wp - [GENERIC] check if the chip is write protected
607 * @mtd: MTD device structure
609 * Check, if the device is write protected. The function expects, that the
610 * device is already selected.
612 static int nand_check_wp(struct mtd_info *mtd)
614 struct nand_chip *chip = mtd->priv;
616 /* Broken xD cards report WP despite being writable */
617 if (chip->options & NAND_BROKEN_XD)
620 /* Check the WP bit */
621 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
622 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
626 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
627 * @mtd: MTD device structure
628 * @ofs: offset from device start
629 * @getchip: 0, if the chip is already selected
630 * @allowbbt: 1, if its allowed to access the bbt area
632 * Check, if the block is bad. Either by reading the bad block table or
633 * calling of the scan function.
635 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
638 struct nand_chip *chip = mtd->priv;
641 return chip->block_bad(mtd, ofs, getchip);
643 /* Return info from the table */
644 return nand_isbad_bbt(mtd, ofs, allowbbt);
649 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
650 * @mtd: MTD device structure
653 * Helper function for nand_wait_ready used when needing to wait in interrupt
656 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
658 struct nand_chip *chip = mtd->priv;
661 /* Wait for the device to get ready */
662 for (i = 0; i < timeo; i++) {
663 if (chip->dev_ready(mtd))
665 touch_softlockup_watchdog();
671 /* Wait for the ready pin, after a command. The timeout is caught later. */
672 void nand_wait_ready(struct mtd_info *mtd)
674 struct nand_chip *chip = mtd->priv;
676 unsigned long timeo = jiffies + msecs_to_jiffies(20);
679 if (in_interrupt() || oops_in_progress)
680 return panic_nand_wait_ready(mtd, 400);
682 led_trigger_event(nand_led_trigger, LED_FULL);
683 /* Wait until command is processed or timeout occurs */
685 if (chip->dev_ready(mtd))
687 touch_softlockup_watchdog();
688 } while (time_before(jiffies, timeo));
689 led_trigger_event(nand_led_trigger, LED_OFF);
691 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
694 time_start = get_timer(0);
695 /* Wait until command is processed or timeout occurs */
696 while (get_timer(time_start) < timeo) {
698 if (chip->dev_ready(mtd))
703 EXPORT_SYMBOL_GPL(nand_wait_ready);
706 * nand_command - [DEFAULT] Send command to NAND device
707 * @mtd: MTD device structure
708 * @command: the command to be sent
709 * @column: the column address for this command, -1 if none
710 * @page_addr: the page address for this command, -1 if none
712 * Send command to NAND device. This function is used for small page devices
713 * (512 Bytes per page).
715 static void nand_command(struct mtd_info *mtd, unsigned int command,
716 int column, int page_addr)
718 register struct nand_chip *chip = mtd->priv;
719 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
720 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
722 /* Write out the command to the device */
723 if (command == NAND_CMD_SEQIN) {
726 if (column >= mtd->writesize) {
728 column -= mtd->writesize;
729 readcmd = NAND_CMD_READOOB;
730 } else if (column < 256) {
731 /* First 256 bytes --> READ0 */
732 readcmd = NAND_CMD_READ0;
735 readcmd = NAND_CMD_READ1;
737 chip->cmd_ctrl(mtd, readcmd, ctrl);
738 ctrl &= ~NAND_CTRL_CHANGE;
740 chip->cmd_ctrl(mtd, command, ctrl);
742 /* Address cycle, when necessary */
743 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
744 /* Serially input address */
746 /* Adjust columns for 16 bit buswidth */
747 if (chip->options & NAND_BUSWIDTH_16 &&
748 !nand_opcode_8bits(command))
750 chip->cmd_ctrl(mtd, column, ctrl);
751 ctrl &= ~NAND_CTRL_CHANGE;
753 if (page_addr != -1) {
754 chip->cmd_ctrl(mtd, page_addr, ctrl);
755 ctrl &= ~NAND_CTRL_CHANGE;
756 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
757 /* One more address cycle for devices > 32MiB */
758 if (chip->chipsize > (32 << 20))
759 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
761 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
764 * Program and erase have their own busy handlers status and sequential
769 case NAND_CMD_PAGEPROG:
770 case NAND_CMD_ERASE1:
771 case NAND_CMD_ERASE2:
773 case NAND_CMD_STATUS:
779 udelay(chip->chip_delay);
780 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
781 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
783 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
784 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
788 /* This applies to read commands */
791 * If we don't have access to the busy pin, we apply the given
794 if (!chip->dev_ready) {
795 udelay(chip->chip_delay);
800 * Apply this short delay always to ensure that we do wait tWB in
801 * any case on any machine.
805 nand_wait_ready(mtd);
809 * nand_command_lp - [DEFAULT] Send command to NAND large page device
810 * @mtd: MTD device structure
811 * @command: the command to be sent
812 * @column: the column address for this command, -1 if none
813 * @page_addr: the page address for this command, -1 if none
815 * Send command to NAND device. This is the version for the new large page
816 * devices. We don't have the separate regions as we have in the small page
817 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
819 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
820 int column, int page_addr)
822 register struct nand_chip *chip = mtd->priv;
823 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
825 /* Emulate NAND_CMD_READOOB */
826 if (command == NAND_CMD_READOOB) {
827 column += mtd->writesize;
828 command = NAND_CMD_READ0;
831 /* Command latch cycle */
832 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
834 if (column != -1 || page_addr != -1) {
835 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
837 /* Serially input address */
839 /* Adjust columns for 16 bit buswidth */
840 if (chip->options & NAND_BUSWIDTH_16 &&
841 !nand_opcode_8bits(command))
843 chip->cmd_ctrl(mtd, column, ctrl);
844 ctrl &= ~NAND_CTRL_CHANGE;
845 chip->cmd_ctrl(mtd, column >> 8, ctrl);
847 if (page_addr != -1) {
848 chip->cmd_ctrl(mtd, page_addr, ctrl);
849 chip->cmd_ctrl(mtd, page_addr >> 8,
850 NAND_NCE | NAND_ALE);
851 /* One more address cycle for devices > 128MiB */
852 if (chip->chipsize > (128 << 20))
853 chip->cmd_ctrl(mtd, page_addr >> 16,
854 NAND_NCE | NAND_ALE);
857 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
860 * Program and erase have their own busy handlers status, sequential
861 * in, and deplete1 need no delay.
865 case NAND_CMD_CACHEDPROG:
866 case NAND_CMD_PAGEPROG:
867 case NAND_CMD_ERASE1:
868 case NAND_CMD_ERASE2:
871 case NAND_CMD_STATUS:
877 udelay(chip->chip_delay);
878 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
879 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
880 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
881 NAND_NCE | NAND_CTRL_CHANGE);
882 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
886 case NAND_CMD_RNDOUT:
887 /* No ready / busy check necessary */
888 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
889 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
890 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
891 NAND_NCE | NAND_CTRL_CHANGE);
895 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
896 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
897 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
898 NAND_NCE | NAND_CTRL_CHANGE);
900 /* This applies to read commands */
903 * If we don't have access to the busy pin, we apply the given
906 if (!chip->dev_ready) {
907 udelay(chip->chip_delay);
913 * Apply this short delay always to ensure that we do wait tWB in
914 * any case on any machine.
918 nand_wait_ready(mtd);
922 * panic_nand_get_device - [GENERIC] Get chip for selected access
923 * @chip: the nand chip descriptor
924 * @mtd: MTD device structure
925 * @new_state: the state which is requested
927 * Used when in panic, no locks are taken.
929 static void panic_nand_get_device(struct nand_chip *chip,
930 struct mtd_info *mtd, int new_state)
932 /* Hardware controller shared among independent devices */
933 chip->controller->active = chip;
934 chip->state = new_state;
938 * nand_get_device - [GENERIC] Get chip for selected access
939 * @mtd: MTD device structure
940 * @new_state: the state which is requested
942 * Get the device and lock it for exclusive access
945 nand_get_device(struct mtd_info *mtd, int new_state)
947 struct nand_chip *chip = mtd->priv;
949 spinlock_t *lock = &chip->controller->lock;
950 wait_queue_head_t *wq = &chip->controller->wq;
951 DECLARE_WAITQUEUE(wait, current);
955 /* Hardware controller shared among independent devices */
956 if (!chip->controller->active)
957 chip->controller->active = chip;
959 if (chip->controller->active == chip && chip->state == FL_READY) {
960 chip->state = new_state;
964 if (new_state == FL_PM_SUSPENDED) {
965 if (chip->controller->active->state == FL_PM_SUSPENDED) {
966 chip->state = FL_PM_SUSPENDED;
971 set_current_state(TASK_UNINTERRUPTIBLE);
972 add_wait_queue(wq, &wait);
975 remove_wait_queue(wq, &wait);
978 chip->state = new_state;
984 * panic_nand_wait - [GENERIC] wait until the command is done
985 * @mtd: MTD device structure
986 * @chip: NAND chip structure
989 * Wait for command done. This is a helper function for nand_wait used when
990 * we are in interrupt context. May happen when in panic and trying to write
991 * an oops through mtdoops.
993 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
997 for (i = 0; i < timeo; i++) {
998 if (chip->dev_ready) {
999 if (chip->dev_ready(mtd))
1002 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1010 * nand_wait - [DEFAULT] wait until the command is done
1011 * @mtd: MTD device structure
1012 * @chip: NAND chip structure
1014 * Wait for command done. This applies to erase and program only. Erase can
1015 * take up to 400ms and program up to 20ms according to general NAND and
1018 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1021 int status, state = chip->state;
1022 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1024 led_trigger_event(nand_led_trigger, LED_FULL);
1027 * Apply this short delay always to ensure that we do wait tWB in any
1028 * case on any machine.
1032 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1035 if (in_interrupt() || oops_in_progress)
1036 panic_nand_wait(mtd, chip, timeo);
1038 timeo = jiffies + msecs_to_jiffies(timeo);
1039 while (time_before(jiffies, timeo)) {
1040 if (chip->dev_ready) {
1041 if (chip->dev_ready(mtd))
1044 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1051 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
1054 time_start = get_timer(0);
1055 while (get_timer(time_start) < timer) {
1056 if (chip->dev_ready) {
1057 if (chip->dev_ready(mtd))
1060 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1065 #ifdef PPCHAMELON_NAND_TIMER_HACK
1066 time_start = get_timer(0);
1067 while (get_timer(time_start) < 10)
1069 #endif /* PPCHAMELON_NAND_TIMER_HACK */
1070 led_trigger_event(nand_led_trigger, LED_OFF);
1072 status = (int)chip->read_byte(mtd);
1073 /* This can happen if in case of timeout or buggy dev_ready */
1074 WARN_ON(!(status & NAND_STATUS_READY));
1080 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1082 * @ofs: offset to start unlock from
1083 * @len: length to unlock
1084 * @invert: when = 0, unlock the range of blocks within the lower and
1085 * upper boundary address
1086 * when = 1, unlock the range of blocks outside the boundaries
1087 * of the lower and upper boundary address
1089 * Returs unlock status.
1091 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1092 uint64_t len, int invert)
1096 struct nand_chip *chip = mtd->priv;
1098 /* Submit address of first page to unlock */
1099 page = ofs >> chip->page_shift;
1100 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1102 /* Submit address of last page to unlock */
1103 page = (ofs + len) >> chip->page_shift;
1104 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1105 (page | invert) & chip->pagemask);
1107 /* Call wait ready function */
1108 status = chip->waitfunc(mtd, chip);
1109 /* See if device thinks it succeeded */
1110 if (status & NAND_STATUS_FAIL) {
1111 pr_debug("%s: error status = 0x%08x\n",
1120 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1122 * @ofs: offset to start unlock from
1123 * @len: length to unlock
1125 * Returns unlock status.
1127 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1131 struct nand_chip *chip = mtd->priv;
1133 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1134 __func__, (unsigned long long)ofs, len);
1136 if (check_offs_len(mtd, ofs, len))
1139 /* Align to last block address if size addresses end of the device */
1140 if (ofs + len == mtd->size)
1141 len -= mtd->erasesize;
1143 nand_get_device(mtd, FL_UNLOCKING);
1145 /* Shift to get chip number */
1146 chipnr = ofs >> chip->chip_shift;
1148 chip->select_chip(mtd, chipnr);
1150 /* Check, if it is write protected */
1151 if (nand_check_wp(mtd)) {
1152 pr_debug("%s: device is write protected!\n",
1158 ret = __nand_unlock(mtd, ofs, len, 0);
1161 chip->select_chip(mtd, -1);
1162 nand_release_device(mtd);
1166 EXPORT_SYMBOL(nand_unlock);
1169 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1171 * @ofs: offset to start unlock from
1172 * @len: length to unlock
1174 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1175 * have this feature, but it allows only to lock all blocks, not for specified
1176 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1179 * Returns lock status.
1181 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1184 int chipnr, status, page;
1185 struct nand_chip *chip = mtd->priv;
1187 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1188 __func__, (unsigned long long)ofs, len);
1190 if (check_offs_len(mtd, ofs, len))
1193 nand_get_device(mtd, FL_LOCKING);
1195 /* Shift to get chip number */
1196 chipnr = ofs >> chip->chip_shift;
1198 chip->select_chip(mtd, chipnr);
1200 /* Check, if it is write protected */
1201 if (nand_check_wp(mtd)) {
1202 pr_debug("%s: device is write protected!\n",
1204 status = MTD_ERASE_FAILED;
1209 /* Submit address of first page to lock */
1210 page = ofs >> chip->page_shift;
1211 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1213 /* Call wait ready function */
1214 status = chip->waitfunc(mtd, chip);
1215 /* See if device thinks it succeeded */
1216 if (status & NAND_STATUS_FAIL) {
1217 pr_debug("%s: error status = 0x%08x\n",
1223 ret = __nand_unlock(mtd, ofs, len, 0x1);
1226 chip->select_chip(mtd, -1);
1227 nand_release_device(mtd);
1231 EXPORT_SYMBOL(nand_lock);
1235 * nand_read_page_raw - [INTERN] read raw page data without ecc
1236 * @mtd: mtd info structure
1237 * @chip: nand chip info structure
1238 * @buf: buffer to store read data
1239 * @oob_required: caller requires OOB data read to chip->oob_poi
1240 * @page: page number to read
1242 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1244 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1245 uint8_t *buf, int oob_required, int page)
1247 chip->read_buf(mtd, buf, mtd->writesize);
1249 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1254 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1255 * @mtd: mtd info structure
1256 * @chip: nand chip info structure
1257 * @buf: buffer to store read data
1258 * @oob_required: caller requires OOB data read to chip->oob_poi
1259 * @page: page number to read
1261 * We need a special oob layout and handling even when OOB isn't used.
1263 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1264 struct nand_chip *chip, uint8_t *buf,
1265 int oob_required, int page)
1267 int eccsize = chip->ecc.size;
1268 int eccbytes = chip->ecc.bytes;
1269 uint8_t *oob = chip->oob_poi;
1272 for (steps = chip->ecc.steps; steps > 0; steps--) {
1273 chip->read_buf(mtd, buf, eccsize);
1276 if (chip->ecc.prepad) {
1277 chip->read_buf(mtd, oob, chip->ecc.prepad);
1278 oob += chip->ecc.prepad;
1281 chip->read_buf(mtd, oob, eccbytes);
1284 if (chip->ecc.postpad) {
1285 chip->read_buf(mtd, oob, chip->ecc.postpad);
1286 oob += chip->ecc.postpad;
1290 size = mtd->oobsize - (oob - chip->oob_poi);
1292 chip->read_buf(mtd, oob, size);
1298 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1299 * @mtd: mtd info structure
1300 * @chip: nand chip info structure
1301 * @buf: buffer to store read data
1302 * @oob_required: caller requires OOB data read to chip->oob_poi
1303 * @page: page number to read
1305 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1306 uint8_t *buf, int oob_required, int page)
1308 int i, eccsize = chip->ecc.size;
1309 int eccbytes = chip->ecc.bytes;
1310 int eccsteps = chip->ecc.steps;
1312 uint8_t *ecc_calc = chip->buffers->ecccalc;
1313 uint8_t *ecc_code = chip->buffers->ecccode;
1314 uint32_t *eccpos = chip->ecc.layout->eccpos;
1315 unsigned int max_bitflips = 0;
1317 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1319 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1320 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1322 for (i = 0; i < chip->ecc.total; i++)
1323 ecc_code[i] = chip->oob_poi[eccpos[i]];
1325 eccsteps = chip->ecc.steps;
1328 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1331 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1333 mtd->ecc_stats.failed++;
1335 mtd->ecc_stats.corrected += stat;
1336 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1339 return max_bitflips;
1343 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1344 * @mtd: mtd info structure
1345 * @chip: nand chip info structure
1346 * @data_offs: offset of requested data within the page
1347 * @readlen: data length
1348 * @bufpoi: buffer to store read data
1349 * @page: page number to read
1351 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1352 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1355 int start_step, end_step, num_steps;
1356 uint32_t *eccpos = chip->ecc.layout->eccpos;
1358 int data_col_addr, i, gaps = 0;
1359 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1360 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1362 unsigned int max_bitflips = 0;
1364 /* Column address within the page aligned to ECC size (256bytes) */
1365 start_step = data_offs / chip->ecc.size;
1366 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1367 num_steps = end_step - start_step + 1;
1368 index = start_step * chip->ecc.bytes;
1370 /* Data size aligned to ECC ecc.size */
1371 datafrag_len = num_steps * chip->ecc.size;
1372 eccfrag_len = num_steps * chip->ecc.bytes;
1374 data_col_addr = start_step * chip->ecc.size;
1375 /* If we read not a page aligned data */
1376 if (data_col_addr != 0)
1377 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1379 p = bufpoi + data_col_addr;
1380 chip->read_buf(mtd, p, datafrag_len);
1383 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1384 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1387 * The performance is faster if we position offsets according to
1388 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1390 for (i = 0; i < eccfrag_len - 1; i++) {
1391 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1392 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1398 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1399 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1402 * Send the command to read the particular ECC bytes take care
1403 * about buswidth alignment in read_buf.
1405 aligned_pos = eccpos[index] & ~(busw - 1);
1406 aligned_len = eccfrag_len;
1407 if (eccpos[index] & (busw - 1))
1409 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1412 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1413 mtd->writesize + aligned_pos, -1);
1414 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1417 for (i = 0; i < eccfrag_len; i++)
1418 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1420 p = bufpoi + data_col_addr;
1421 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1424 stat = chip->ecc.correct(mtd, p,
1425 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1427 mtd->ecc_stats.failed++;
1429 mtd->ecc_stats.corrected += stat;
1430 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1433 return max_bitflips;
1437 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1438 * @mtd: mtd info structure
1439 * @chip: nand chip info structure
1440 * @buf: buffer to store read data
1441 * @oob_required: caller requires OOB data read to chip->oob_poi
1442 * @page: page number to read
1444 * Not for syndrome calculating ECC controllers which need a special oob layout.
1446 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1447 uint8_t *buf, int oob_required, int page)
1449 int i, eccsize = chip->ecc.size;
1450 int eccbytes = chip->ecc.bytes;
1451 int eccsteps = chip->ecc.steps;
1453 uint8_t *ecc_calc = chip->buffers->ecccalc;
1454 uint8_t *ecc_code = chip->buffers->ecccode;
1455 uint32_t *eccpos = chip->ecc.layout->eccpos;
1456 unsigned int max_bitflips = 0;
1458 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1459 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1460 chip->read_buf(mtd, p, eccsize);
1461 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1463 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1465 for (i = 0; i < chip->ecc.total; i++)
1466 ecc_code[i] = chip->oob_poi[eccpos[i]];
1468 eccsteps = chip->ecc.steps;
1471 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1474 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1476 mtd->ecc_stats.failed++;
1478 mtd->ecc_stats.corrected += stat;
1479 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1482 return max_bitflips;
1486 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1487 * @mtd: mtd info structure
1488 * @chip: nand chip info structure
1489 * @buf: buffer to store read data
1490 * @oob_required: caller requires OOB data read to chip->oob_poi
1491 * @page: page number to read
1493 * Hardware ECC for large page chips, require OOB to be read first. For this
1494 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1495 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1496 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1497 * the data area, by overwriting the NAND manufacturer bad block markings.
1499 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1500 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1502 int i, eccsize = chip->ecc.size;
1503 int eccbytes = chip->ecc.bytes;
1504 int eccsteps = chip->ecc.steps;
1506 uint8_t *ecc_code = chip->buffers->ecccode;
1507 uint32_t *eccpos = chip->ecc.layout->eccpos;
1508 uint8_t *ecc_calc = chip->buffers->ecccalc;
1509 unsigned int max_bitflips = 0;
1511 /* Read the OOB area first */
1512 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1513 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1514 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1516 for (i = 0; i < chip->ecc.total; i++)
1517 ecc_code[i] = chip->oob_poi[eccpos[i]];
1519 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1522 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1523 chip->read_buf(mtd, p, eccsize);
1524 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1526 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1528 mtd->ecc_stats.failed++;
1530 mtd->ecc_stats.corrected += stat;
1531 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1534 return max_bitflips;
1538 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1539 * @mtd: mtd info structure
1540 * @chip: nand chip info structure
1541 * @buf: buffer to store read data
1542 * @oob_required: caller requires OOB data read to chip->oob_poi
1543 * @page: page number to read
1545 * The hw generator calculates the error syndrome automatically. Therefore we
1546 * need a special oob layout and handling.
1548 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1549 uint8_t *buf, int oob_required, int page)
1551 int i, eccsize = chip->ecc.size;
1552 int eccbytes = chip->ecc.bytes;
1553 int eccsteps = chip->ecc.steps;
1555 uint8_t *oob = chip->oob_poi;
1556 unsigned int max_bitflips = 0;
1558 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1561 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1562 chip->read_buf(mtd, p, eccsize);
1564 if (chip->ecc.prepad) {
1565 chip->read_buf(mtd, oob, chip->ecc.prepad);
1566 oob += chip->ecc.prepad;
1569 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1570 chip->read_buf(mtd, oob, eccbytes);
1571 stat = chip->ecc.correct(mtd, p, oob, NULL);
1574 mtd->ecc_stats.failed++;
1576 mtd->ecc_stats.corrected += stat;
1577 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1582 if (chip->ecc.postpad) {
1583 chip->read_buf(mtd, oob, chip->ecc.postpad);
1584 oob += chip->ecc.postpad;
1588 /* Calculate remaining oob bytes */
1589 i = mtd->oobsize - (oob - chip->oob_poi);
1591 chip->read_buf(mtd, oob, i);
1593 return max_bitflips;
1597 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1598 * @chip: nand chip structure
1599 * @oob: oob destination address
1600 * @ops: oob ops structure
1601 * @len: size of oob to transfer
1603 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1604 struct mtd_oob_ops *ops, size_t len)
1606 switch (ops->mode) {
1608 case MTD_OPS_PLACE_OOB:
1610 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1613 case MTD_OPS_AUTO_OOB: {
1614 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1615 uint32_t boffs = 0, roffs = ops->ooboffs;
1618 for (; free->length && len; free++, len -= bytes) {
1619 /* Read request not from offset 0? */
1620 if (unlikely(roffs)) {
1621 if (roffs >= free->length) {
1622 roffs -= free->length;
1625 boffs = free->offset + roffs;
1626 bytes = min_t(size_t, len,
1627 (free->length - roffs));
1630 bytes = min_t(size_t, len, free->length);
1631 boffs = free->offset;
1633 memcpy(oob, chip->oob_poi + boffs, bytes);
1645 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1646 * @mtd: MTD device structure
1647 * @retry_mode: the retry mode to use
1649 * Some vendors supply a special command to shift the Vt threshold, to be used
1650 * when there are too many bitflips in a page (i.e., ECC error). After setting
1651 * a new threshold, the host should retry reading the page.
1653 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1655 struct nand_chip *chip = mtd->priv;
1657 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1659 if (retry_mode >= chip->read_retries)
1662 if (!chip->setup_read_retry)
1665 return chip->setup_read_retry(mtd, retry_mode);
1669 * nand_do_read_ops - [INTERN] Read data with ECC
1670 * @mtd: MTD device structure
1671 * @from: offset to read from
1672 * @ops: oob ops structure
1674 * Internal function. Called with chip held.
1676 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1677 struct mtd_oob_ops *ops)
1679 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1680 struct nand_chip *chip = mtd->priv;
1682 uint32_t readlen = ops->len;
1683 uint32_t oobreadlen = ops->ooblen;
1684 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1685 mtd->oobavail : mtd->oobsize;
1687 uint8_t *bufpoi, *oob, *buf;
1688 unsigned int max_bitflips = 0;
1690 bool ecc_fail = false;
1692 chipnr = (int)(from >> chip->chip_shift);
1693 chip->select_chip(mtd, chipnr);
1695 realpage = (int)(from >> chip->page_shift);
1696 page = realpage & chip->pagemask;
1698 col = (int)(from & (mtd->writesize - 1));
1702 oob_required = oob ? 1 : 0;
1705 unsigned int ecc_failures = mtd->ecc_stats.failed;
1708 bytes = min(mtd->writesize - col, readlen);
1709 aligned = (bytes == mtd->writesize);
1711 /* Is the current page in the buffer? */
1712 if (realpage != chip->pagebuf || oob) {
1713 bufpoi = aligned ? buf : chip->buffers->databuf;
1716 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1719 * Now read the page into the buffer. Absent an error,
1720 * the read methods return max bitflips per ecc step.
1722 if (unlikely(ops->mode == MTD_OPS_RAW))
1723 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1726 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1728 ret = chip->ecc.read_subpage(mtd, chip,
1732 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1733 oob_required, page);
1736 /* Invalidate page cache */
1741 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1743 /* Transfer not aligned data */
1745 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1746 !(mtd->ecc_stats.failed - ecc_failures) &&
1747 (ops->mode != MTD_OPS_RAW)) {
1748 chip->pagebuf = realpage;
1749 chip->pagebuf_bitflips = ret;
1751 /* Invalidate page cache */
1754 memcpy(buf, chip->buffers->databuf + col, bytes);
1757 if (unlikely(oob)) {
1758 int toread = min(oobreadlen, max_oobsize);
1761 oob = nand_transfer_oob(chip,
1763 oobreadlen -= toread;
1767 if (chip->options & NAND_NEED_READRDY) {
1768 /* Apply delay or wait for ready/busy pin */
1769 if (!chip->dev_ready)
1770 udelay(chip->chip_delay);
1772 nand_wait_ready(mtd);
1775 if (mtd->ecc_stats.failed - ecc_failures) {
1776 if (retry_mode + 1 < chip->read_retries) {
1778 ret = nand_setup_read_retry(mtd,
1783 /* Reset failures; retry */
1784 mtd->ecc_stats.failed = ecc_failures;
1787 /* No more retry modes; real failure */
1794 memcpy(buf, chip->buffers->databuf + col, bytes);
1796 max_bitflips = max_t(unsigned int, max_bitflips,
1797 chip->pagebuf_bitflips);
1802 /* Reset to retry mode 0 */
1804 ret = nand_setup_read_retry(mtd, 0);
1813 /* For subsequent reads align to page boundary */
1815 /* Increment page address */
1818 page = realpage & chip->pagemask;
1819 /* Check, if we cross a chip boundary */
1822 chip->select_chip(mtd, -1);
1823 chip->select_chip(mtd, chipnr);
1826 chip->select_chip(mtd, -1);
1828 ops->retlen = ops->len - (size_t) readlen;
1830 ops->oobretlen = ops->ooblen - oobreadlen;
1838 return max_bitflips;
1842 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1843 * @mtd: MTD device structure
1844 * @from: offset to read from
1845 * @len: number of bytes to read
1846 * @retlen: pointer to variable to store the number of read bytes
1847 * @buf: the databuffer to put data
1849 * Get hold of the chip and call nand_do_read.
1851 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1852 size_t *retlen, uint8_t *buf)
1854 struct mtd_oob_ops ops;
1857 nand_get_device(mtd, FL_READING);
1861 ops.mode = MTD_OPS_PLACE_OOB;
1862 ret = nand_do_read_ops(mtd, from, &ops);
1863 *retlen = ops.retlen;
1864 nand_release_device(mtd);
1869 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1870 * @mtd: mtd info structure
1871 * @chip: nand chip info structure
1872 * @page: page number to read
1874 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1877 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1878 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1883 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1885 * @mtd: mtd info structure
1886 * @chip: nand chip info structure
1887 * @page: page number to read
1889 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1892 uint8_t *buf = chip->oob_poi;
1893 int length = mtd->oobsize;
1894 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1895 int eccsize = chip->ecc.size;
1896 uint8_t *bufpoi = buf;
1897 int i, toread, sndrnd = 0, pos;
1899 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1900 for (i = 0; i < chip->ecc.steps; i++) {
1902 pos = eccsize + i * (eccsize + chunk);
1903 if (mtd->writesize > 512)
1904 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1906 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1909 toread = min_t(int, length, chunk);
1910 chip->read_buf(mtd, bufpoi, toread);
1915 chip->read_buf(mtd, bufpoi, length);
1921 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1922 * @mtd: mtd info structure
1923 * @chip: nand chip info structure
1924 * @page: page number to write
1926 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1930 const uint8_t *buf = chip->oob_poi;
1931 int length = mtd->oobsize;
1933 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1934 chip->write_buf(mtd, buf, length);
1935 /* Send command to program the OOB data */
1936 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1938 status = chip->waitfunc(mtd, chip);
1940 return status & NAND_STATUS_FAIL ? -EIO : 0;
1944 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1945 * with syndrome - only for large page flash
1946 * @mtd: mtd info structure
1947 * @chip: nand chip info structure
1948 * @page: page number to write
1950 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1951 struct nand_chip *chip, int page)
1953 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1954 int eccsize = chip->ecc.size, length = mtd->oobsize;
1955 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1956 const uint8_t *bufpoi = chip->oob_poi;
1959 * data-ecc-data-ecc ... ecc-oob
1961 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1963 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1964 pos = steps * (eccsize + chunk);
1969 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1970 for (i = 0; i < steps; i++) {
1972 if (mtd->writesize <= 512) {
1973 uint32_t fill = 0xFFFFFFFF;
1977 int num = min_t(int, len, 4);
1978 chip->write_buf(mtd, (uint8_t *)&fill,
1983 pos = eccsize + i * (eccsize + chunk);
1984 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1988 len = min_t(int, length, chunk);
1989 chip->write_buf(mtd, bufpoi, len);
1994 chip->write_buf(mtd, bufpoi, length);
1996 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1997 status = chip->waitfunc(mtd, chip);
1999 return status & NAND_STATUS_FAIL ? -EIO : 0;
2003 * nand_do_read_oob - [INTERN] NAND read out-of-band
2004 * @mtd: MTD device structure
2005 * @from: offset to read from
2006 * @ops: oob operations description structure
2008 * NAND read out-of-band data from the spare area.
2010 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2011 struct mtd_oob_ops *ops)
2013 int page, realpage, chipnr;
2014 struct nand_chip *chip = mtd->priv;
2015 struct mtd_ecc_stats stats;
2016 int readlen = ops->ooblen;
2018 uint8_t *buf = ops->oobbuf;
2021 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2022 __func__, (unsigned long long)from, readlen);
2024 stats = mtd->ecc_stats;
2026 if (ops->mode == MTD_OPS_AUTO_OOB)
2027 len = chip->ecc.layout->oobavail;
2031 if (unlikely(ops->ooboffs >= len)) {
2032 pr_debug("%s: attempt to start read outside oob\n",
2037 /* Do not allow reads past end of device */
2038 if (unlikely(from >= mtd->size ||
2039 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2040 (from >> chip->page_shift)) * len)) {
2041 pr_debug("%s: attempt to read beyond end of device\n",
2046 chipnr = (int)(from >> chip->chip_shift);
2047 chip->select_chip(mtd, chipnr);
2049 /* Shift to get page */
2050 realpage = (int)(from >> chip->page_shift);
2051 page = realpage & chip->pagemask;
2056 if (ops->mode == MTD_OPS_RAW)
2057 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2059 ret = chip->ecc.read_oob(mtd, chip, page);
2064 len = min(len, readlen);
2065 buf = nand_transfer_oob(chip, buf, ops, len);
2067 if (chip->options & NAND_NEED_READRDY) {
2068 /* Apply delay or wait for ready/busy pin */
2069 if (!chip->dev_ready)
2070 udelay(chip->chip_delay);
2072 nand_wait_ready(mtd);
2079 /* Increment page address */
2082 page = realpage & chip->pagemask;
2083 /* Check, if we cross a chip boundary */
2086 chip->select_chip(mtd, -1);
2087 chip->select_chip(mtd, chipnr);
2090 chip->select_chip(mtd, -1);
2092 ops->oobretlen = ops->ooblen - readlen;
2097 if (mtd->ecc_stats.failed - stats.failed)
2100 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2104 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2105 * @mtd: MTD device structure
2106 * @from: offset to read from
2107 * @ops: oob operation description structure
2109 * NAND read data and/or out-of-band data.
2111 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2112 struct mtd_oob_ops *ops)
2114 int ret = -ENOTSUPP;
2118 /* Do not allow reads past end of device */
2119 if (ops->datbuf && (from + ops->len) > mtd->size) {
2120 pr_debug("%s: attempt to read beyond end of device\n",
2125 nand_get_device(mtd, FL_READING);
2127 switch (ops->mode) {
2128 case MTD_OPS_PLACE_OOB:
2129 case MTD_OPS_AUTO_OOB:
2138 ret = nand_do_read_oob(mtd, from, ops);
2140 ret = nand_do_read_ops(mtd, from, ops);
2143 nand_release_device(mtd);
2149 * nand_write_page_raw - [INTERN] raw page write function
2150 * @mtd: mtd info structure
2151 * @chip: nand chip info structure
2153 * @oob_required: must write chip->oob_poi to OOB
2155 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2157 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2158 const uint8_t *buf, int oob_required)
2160 chip->write_buf(mtd, buf, mtd->writesize);
2162 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2168 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2169 * @mtd: mtd info structure
2170 * @chip: nand chip info structure
2172 * @oob_required: must write chip->oob_poi to OOB
2174 * We need a special oob layout and handling even when ECC isn't checked.
2176 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2177 struct nand_chip *chip,
2178 const uint8_t *buf, int oob_required)
2180 int eccsize = chip->ecc.size;
2181 int eccbytes = chip->ecc.bytes;
2182 uint8_t *oob = chip->oob_poi;
2185 for (steps = chip->ecc.steps; steps > 0; steps--) {
2186 chip->write_buf(mtd, buf, eccsize);
2189 if (chip->ecc.prepad) {
2190 chip->write_buf(mtd, oob, chip->ecc.prepad);
2191 oob += chip->ecc.prepad;
2194 chip->write_buf(mtd, oob, eccbytes);
2197 if (chip->ecc.postpad) {
2198 chip->write_buf(mtd, oob, chip->ecc.postpad);
2199 oob += chip->ecc.postpad;
2203 size = mtd->oobsize - (oob - chip->oob_poi);
2205 chip->write_buf(mtd, oob, size);
2210 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2211 * @mtd: mtd info structure
2212 * @chip: nand chip info structure
2214 * @oob_required: must write chip->oob_poi to OOB
2216 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2217 const uint8_t *buf, int oob_required)
2219 int i, eccsize = chip->ecc.size;
2220 int eccbytes = chip->ecc.bytes;
2221 int eccsteps = chip->ecc.steps;
2222 uint8_t *ecc_calc = chip->buffers->ecccalc;
2223 const uint8_t *p = buf;
2224 uint32_t *eccpos = chip->ecc.layout->eccpos;
2226 /* Software ECC calculation */
2227 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2228 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2230 for (i = 0; i < chip->ecc.total; i++)
2231 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2233 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2237 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2238 * @mtd: mtd info structure
2239 * @chip: nand chip info structure
2241 * @oob_required: must write chip->oob_poi to OOB
2243 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2244 const uint8_t *buf, int oob_required)
2246 int i, eccsize = chip->ecc.size;
2247 int eccbytes = chip->ecc.bytes;
2248 int eccsteps = chip->ecc.steps;
2249 uint8_t *ecc_calc = chip->buffers->ecccalc;
2250 const uint8_t *p = buf;
2251 uint32_t *eccpos = chip->ecc.layout->eccpos;
2253 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2254 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2255 chip->write_buf(mtd, p, eccsize);
2256 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2259 for (i = 0; i < chip->ecc.total; i++)
2260 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2262 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2269 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2270 * @mtd: mtd info structure
2271 * @chip: nand chip info structure
2272 * @offset: column address of subpage within the page
2273 * @data_len: data length
2275 * @oob_required: must write chip->oob_poi to OOB
2277 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2278 struct nand_chip *chip, uint32_t offset,
2279 uint32_t data_len, const uint8_t *buf,
2282 uint8_t *oob_buf = chip->oob_poi;
2283 uint8_t *ecc_calc = chip->buffers->ecccalc;
2284 int ecc_size = chip->ecc.size;
2285 int ecc_bytes = chip->ecc.bytes;
2286 int ecc_steps = chip->ecc.steps;
2287 uint32_t *eccpos = chip->ecc.layout->eccpos;
2288 uint32_t start_step = offset / ecc_size;
2289 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2290 int oob_bytes = mtd->oobsize / ecc_steps;
2293 for (step = 0; step < ecc_steps; step++) {
2294 /* configure controller for WRITE access */
2295 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2297 /* write data (untouched subpages already masked by 0xFF) */
2298 chip->write_buf(mtd, buf, ecc_size);
2300 /* mask ECC of un-touched subpages by padding 0xFF */
2301 if ((step < start_step) || (step > end_step))
2302 memset(ecc_calc, 0xff, ecc_bytes);
2304 chip->ecc.calculate(mtd, buf, ecc_calc);
2306 /* mask OOB of un-touched subpages by padding 0xFF */
2307 /* if oob_required, preserve OOB metadata of written subpage */
2308 if (!oob_required || (step < start_step) || (step > end_step))
2309 memset(oob_buf, 0xff, oob_bytes);
2312 ecc_calc += ecc_bytes;
2313 oob_buf += oob_bytes;
2316 /* copy calculated ECC for whole page to chip->buffer->oob */
2317 /* this include masked-value(0xFF) for unwritten subpages */
2318 ecc_calc = chip->buffers->ecccalc;
2319 for (i = 0; i < chip->ecc.total; i++)
2320 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2322 /* write OOB buffer to NAND device */
2323 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2330 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2331 * @mtd: mtd info structure
2332 * @chip: nand chip info structure
2334 * @oob_required: must write chip->oob_poi to OOB
2336 * The hw generator calculates the error syndrome automatically. Therefore we
2337 * need a special oob layout and handling.
2339 static int nand_write_page_syndrome(struct mtd_info *mtd,
2340 struct nand_chip *chip,
2341 const uint8_t *buf, int oob_required)
2343 int i, eccsize = chip->ecc.size;
2344 int eccbytes = chip->ecc.bytes;
2345 int eccsteps = chip->ecc.steps;
2346 const uint8_t *p = buf;
2347 uint8_t *oob = chip->oob_poi;
2349 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2351 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2352 chip->write_buf(mtd, p, eccsize);
2354 if (chip->ecc.prepad) {
2355 chip->write_buf(mtd, oob, chip->ecc.prepad);
2356 oob += chip->ecc.prepad;
2359 chip->ecc.calculate(mtd, p, oob);
2360 chip->write_buf(mtd, oob, eccbytes);
2363 if (chip->ecc.postpad) {
2364 chip->write_buf(mtd, oob, chip->ecc.postpad);
2365 oob += chip->ecc.postpad;
2369 /* Calculate remaining oob bytes */
2370 i = mtd->oobsize - (oob - chip->oob_poi);
2372 chip->write_buf(mtd, oob, i);
2378 * nand_write_page - [REPLACEABLE] write one page
2379 * @mtd: MTD device structure
2380 * @chip: NAND chip descriptor
2381 * @offset: address offset within the page
2382 * @data_len: length of actual data to be written
2383 * @buf: the data to write
2384 * @oob_required: must write chip->oob_poi to OOB
2385 * @page: page number to write
2386 * @cached: cached programming
2387 * @raw: use _raw version of write_page
2389 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2390 uint32_t offset, int data_len, const uint8_t *buf,
2391 int oob_required, int page, int cached, int raw)
2393 int status, subpage;
2395 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2396 chip->ecc.write_subpage)
2397 subpage = offset || (data_len < mtd->writesize);
2401 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2404 status = chip->ecc.write_page_raw(mtd, chip, buf,
2407 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2410 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2416 * Cached progamming disabled for now. Not sure if it's worth the
2417 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2421 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2423 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2424 status = chip->waitfunc(mtd, chip);
2426 * See if operation failed and additional status checks are
2429 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2430 status = chip->errstat(mtd, chip, FL_WRITING, status,
2433 if (status & NAND_STATUS_FAIL)
2436 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2437 status = chip->waitfunc(mtd, chip);
2442 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
2443 /* Send command to read back the data */
2444 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2446 if (chip->verify_buf(mtd, buf, mtd->writesize))
2449 /* Make sure the next page prog is preceded by a status read */
2450 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2458 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2459 * @mtd: MTD device structure
2460 * @oob: oob data buffer
2461 * @len: oob data write length
2462 * @ops: oob ops structure
2464 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2465 struct mtd_oob_ops *ops)
2467 struct nand_chip *chip = mtd->priv;
2470 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2471 * data from a previous OOB read.
2473 memset(chip->oob_poi, 0xff, mtd->oobsize);
2475 switch (ops->mode) {
2477 case MTD_OPS_PLACE_OOB:
2479 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2482 case MTD_OPS_AUTO_OOB: {
2483 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2484 uint32_t boffs = 0, woffs = ops->ooboffs;
2487 for (; free->length && len; free++, len -= bytes) {
2488 /* Write request not from offset 0? */
2489 if (unlikely(woffs)) {
2490 if (woffs >= free->length) {
2491 woffs -= free->length;
2494 boffs = free->offset + woffs;
2495 bytes = min_t(size_t, len,
2496 (free->length - woffs));
2499 bytes = min_t(size_t, len, free->length);
2500 boffs = free->offset;
2502 memcpy(chip->oob_poi + boffs, oob, bytes);
2513 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2516 * nand_do_write_ops - [INTERN] NAND write with ECC
2517 * @mtd: MTD device structure
2518 * @to: offset to write to
2519 * @ops: oob operations description structure
2521 * NAND write with ECC.
2523 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2524 struct mtd_oob_ops *ops)
2526 int chipnr, realpage, page, blockmask, column;
2527 struct nand_chip *chip = mtd->priv;
2528 uint32_t writelen = ops->len;
2530 uint32_t oobwritelen = ops->ooblen;
2531 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2532 mtd->oobavail : mtd->oobsize;
2534 uint8_t *oob = ops->oobbuf;
2535 uint8_t *buf = ops->datbuf;
2537 int oob_required = oob ? 1 : 0;
2544 /* Reject writes, which are not page aligned */
2545 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2547 /* Reject writes, which are not page aligned */
2548 if (NOTALIGNED(to)) {
2550 pr_notice("%s: attempt to write non page aligned data\n",
2555 column = to & (mtd->writesize - 1);
2557 chipnr = (int)(to >> chip->chip_shift);
2558 chip->select_chip(mtd, chipnr);
2560 /* Check, if it is write protected */
2561 if (nand_check_wp(mtd)) {
2566 realpage = (int)(to >> chip->page_shift);
2567 page = realpage & chip->pagemask;
2568 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2570 /* Invalidate the page cache, when we write to the cached page */
2571 if (to <= (chip->pagebuf << chip->page_shift) &&
2572 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2575 /* Don't allow multipage oob writes with offset */
2576 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2582 int bytes = mtd->writesize;
2583 int cached = writelen > bytes && page != blockmask;
2584 uint8_t *wbuf = buf;
2587 /* Partial page write? */
2588 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2590 bytes = min_t(int, bytes - column, (int) writelen);
2592 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2593 memcpy(&chip->buffers->databuf[column], buf, bytes);
2594 wbuf = chip->buffers->databuf;
2597 if (unlikely(oob)) {
2598 size_t len = min(oobwritelen, oobmaxlen);
2599 oob = nand_fill_oob(mtd, oob, len, ops);
2602 /* We still need to erase leftover OOB data */
2603 memset(chip->oob_poi, 0xff, mtd->oobsize);
2605 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2606 oob_required, page, cached,
2607 (ops->mode == MTD_OPS_RAW));
2619 page = realpage & chip->pagemask;
2620 /* Check, if we cross a chip boundary */
2623 chip->select_chip(mtd, -1);
2624 chip->select_chip(mtd, chipnr);
2628 ops->retlen = ops->len - writelen;
2630 ops->oobretlen = ops->ooblen;
2633 chip->select_chip(mtd, -1);
2638 * panic_nand_write - [MTD Interface] NAND write with ECC
2639 * @mtd: MTD device structure
2640 * @to: offset to write to
2641 * @len: number of bytes to write
2642 * @retlen: pointer to variable to store the number of written bytes
2643 * @buf: the data to write
2645 * NAND write with ECC. Used when performing writes in interrupt context, this
2646 * may for example be called by mtdoops when writing an oops while in panic.
2648 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2649 size_t *retlen, const uint8_t *buf)
2651 struct nand_chip *chip = mtd->priv;
2652 struct mtd_oob_ops ops;
2655 /* Wait for the device to get ready */
2656 panic_nand_wait(mtd, chip, 400);
2658 /* Grab the device */
2659 panic_nand_get_device(chip, mtd, FL_WRITING);
2662 ops.datbuf = (uint8_t *)buf;
2664 ops.mode = MTD_OPS_PLACE_OOB;
2666 ret = nand_do_write_ops(mtd, to, &ops);
2668 *retlen = ops.retlen;
2673 * nand_write - [MTD Interface] NAND write with ECC
2674 * @mtd: MTD device structure
2675 * @to: offset to write to
2676 * @len: number of bytes to write
2677 * @retlen: pointer to variable to store the number of written bytes
2678 * @buf: the data to write
2680 * NAND write with ECC.
2682 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2683 size_t *retlen, const uint8_t *buf)
2685 struct mtd_oob_ops ops;
2688 nand_get_device(mtd, FL_WRITING);
2690 ops.datbuf = (uint8_t *)buf;
2692 ops.mode = MTD_OPS_PLACE_OOB;
2693 ret = nand_do_write_ops(mtd, to, &ops);
2694 *retlen = ops.retlen;
2695 nand_release_device(mtd);
2700 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2701 * @mtd: MTD device structure
2702 * @to: offset to write to
2703 * @ops: oob operation description structure
2705 * NAND write out-of-band.
2707 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2708 struct mtd_oob_ops *ops)
2710 int chipnr, page, status, len;
2711 struct nand_chip *chip = mtd->priv;
2713 pr_debug("%s: to = 0x%08x, len = %i\n",
2714 __func__, (unsigned int)to, (int)ops->ooblen);
2716 if (ops->mode == MTD_OPS_AUTO_OOB)
2717 len = chip->ecc.layout->oobavail;
2721 /* Do not allow write past end of page */
2722 if ((ops->ooboffs + ops->ooblen) > len) {
2723 pr_debug("%s: attempt to write past end of page\n",
2728 if (unlikely(ops->ooboffs >= len)) {
2729 pr_debug("%s: attempt to start write outside oob\n",
2734 /* Do not allow write past end of device */
2735 if (unlikely(to >= mtd->size ||
2736 ops->ooboffs + ops->ooblen >
2737 ((mtd->size >> chip->page_shift) -
2738 (to >> chip->page_shift)) * len)) {
2739 pr_debug("%s: attempt to write beyond end of device\n",
2744 chipnr = (int)(to >> chip->chip_shift);
2745 chip->select_chip(mtd, chipnr);
2747 /* Shift to get page */
2748 page = (int)(to >> chip->page_shift);
2751 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2752 * of my DiskOnChip 2000 test units) will clear the whole data page too
2753 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2754 * it in the doc2000 driver in August 1999. dwmw2.
2756 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2758 /* Check, if it is write protected */
2759 if (nand_check_wp(mtd)) {
2760 chip->select_chip(mtd, -1);
2764 /* Invalidate the page cache, if we write to the cached page */
2765 if (page == chip->pagebuf)
2768 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2770 if (ops->mode == MTD_OPS_RAW)
2771 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2773 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2775 chip->select_chip(mtd, -1);
2780 ops->oobretlen = ops->ooblen;
2786 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2787 * @mtd: MTD device structure
2788 * @to: offset to write to
2789 * @ops: oob operation description structure
2791 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2792 struct mtd_oob_ops *ops)
2794 int ret = -ENOTSUPP;
2798 /* Do not allow writes past end of device */
2799 if (ops->datbuf && (to + ops->len) > mtd->size) {
2800 pr_debug("%s: attempt to write beyond end of device\n",
2805 nand_get_device(mtd, FL_WRITING);
2807 switch (ops->mode) {
2808 case MTD_OPS_PLACE_OOB:
2809 case MTD_OPS_AUTO_OOB:
2818 ret = nand_do_write_oob(mtd, to, ops);
2820 ret = nand_do_write_ops(mtd, to, ops);
2823 nand_release_device(mtd);
2828 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2829 * @mtd: MTD device structure
2830 * @page: the page address of the block which will be erased
2832 * Standard erase command for NAND chips.
2834 static void single_erase_cmd(struct mtd_info *mtd, int page)
2836 struct nand_chip *chip = mtd->priv;
2837 /* Send commands to erase a block */
2838 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2839 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2843 * nand_erase - [MTD Interface] erase block(s)
2844 * @mtd: MTD device structure
2845 * @instr: erase instruction
2847 * Erase one ore more blocks.
2849 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2851 return nand_erase_nand(mtd, instr, 0);
2855 * nand_erase_nand - [INTERN] erase block(s)
2856 * @mtd: MTD device structure
2857 * @instr: erase instruction
2858 * @allowbbt: allow erasing the bbt area
2860 * Erase one ore more blocks.
2862 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2865 int page, status, pages_per_block, ret, chipnr;
2866 struct nand_chip *chip = mtd->priv;
2869 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2870 __func__, (unsigned long long)instr->addr,
2871 (unsigned long long)instr->len);
2873 if (check_offs_len(mtd, instr->addr, instr->len))
2876 /* Grab the lock and see if the device is available */
2877 nand_get_device(mtd, FL_ERASING);
2879 /* Shift to get first page */
2880 page = (int)(instr->addr >> chip->page_shift);
2881 chipnr = (int)(instr->addr >> chip->chip_shift);
2883 /* Calculate pages in each block */
2884 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2886 /* Select the NAND device */
2887 chip->select_chip(mtd, chipnr);
2889 /* Check, if it is write protected */
2890 if (nand_check_wp(mtd)) {
2891 pr_debug("%s: device is write protected!\n",
2893 instr->state = MTD_ERASE_FAILED;
2897 /* Loop through the pages */
2900 instr->state = MTD_ERASING;
2905 /* Check if we have a bad block, we do not erase bad blocks! */
2906 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2907 chip->page_shift, 0, allowbbt)) {
2908 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2910 instr->state = MTD_ERASE_FAILED;
2915 * Invalidate the page cache, if we erase the block which
2916 * contains the current cached page.
2918 if (page <= chip->pagebuf && chip->pagebuf <
2919 (page + pages_per_block))
2922 chip->erase_cmd(mtd, page & chip->pagemask);
2924 status = chip->waitfunc(mtd, chip);
2927 * See if operation failed and additional status checks are
2930 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2931 status = chip->errstat(mtd, chip, FL_ERASING,
2934 /* See if block erase succeeded */
2935 if (status & NAND_STATUS_FAIL) {
2936 pr_debug("%s: failed erase, page 0x%08x\n",
2938 instr->state = MTD_ERASE_FAILED;
2940 ((loff_t)page << chip->page_shift);
2944 /* Increment page address and decrement length */
2945 len -= (1ULL << chip->phys_erase_shift);
2946 page += pages_per_block;
2948 /* Check, if we cross a chip boundary */
2949 if (len && !(page & chip->pagemask)) {
2951 chip->select_chip(mtd, -1);
2952 chip->select_chip(mtd, chipnr);
2955 instr->state = MTD_ERASE_DONE;
2959 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2961 /* Deselect and wake up anyone waiting on the device */
2962 chip->select_chip(mtd, -1);
2963 nand_release_device(mtd);
2965 /* Do call back function */
2967 mtd_erase_callback(instr);
2969 /* Return more or less happy */
2974 * nand_sync - [MTD Interface] sync
2975 * @mtd: MTD device structure
2977 * Sync is actually a wait for chip ready function.
2979 static void nand_sync(struct mtd_info *mtd)
2981 pr_debug("%s: called\n", __func__);
2983 /* Grab the lock and see if the device is available */
2984 nand_get_device(mtd, FL_SYNCING);
2985 /* Release it and go back */
2986 nand_release_device(mtd);
2990 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2991 * @mtd: MTD device structure
2992 * @offs: offset relative to mtd start
2994 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2996 return nand_block_checkbad(mtd, offs, 1, 0);
3000 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3001 * @mtd: MTD device structure
3002 * @ofs: offset relative to mtd start
3004 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3008 ret = nand_block_isbad(mtd, ofs);
3010 /* If it was bad already, return success and do nothing */
3016 return nand_block_markbad_lowlevel(mtd, ofs);
3020 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3021 * @mtd: MTD device structure
3022 * @chip: nand chip info structure
3023 * @addr: feature address.
3024 * @subfeature_param: the subfeature parameters, a four bytes array.
3026 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3027 int addr, uint8_t *subfeature_param)
3032 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3033 if (!chip->onfi_version ||
3034 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3035 & ONFI_OPT_CMD_SET_GET_FEATURES))
3039 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3040 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3041 chip->write_byte(mtd, subfeature_param[i]);
3043 status = chip->waitfunc(mtd, chip);
3044 if (status & NAND_STATUS_FAIL)
3050 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3051 * @mtd: MTD device structure
3052 * @chip: nand chip info structure
3053 * @addr: feature address.
3054 * @subfeature_param: the subfeature parameters, a four bytes array.
3056 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3057 int addr, uint8_t *subfeature_param)
3061 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3062 if (!chip->onfi_version ||
3063 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3064 & ONFI_OPT_CMD_SET_GET_FEATURES))
3068 /* clear the sub feature parameters */
3069 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3071 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3072 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3073 *subfeature_param++ = chip->read_byte(mtd);
3079 * nand_suspend - [MTD Interface] Suspend the NAND flash
3080 * @mtd: MTD device structure
3082 static int nand_suspend(struct mtd_info *mtd)
3084 return nand_get_device(mtd, FL_PM_SUSPENDED);
3088 * nand_resume - [MTD Interface] Resume the NAND flash
3089 * @mtd: MTD device structure
3091 static void nand_resume(struct mtd_info *mtd)
3093 struct nand_chip *chip = mtd->priv;
3095 if (chip->state == FL_PM_SUSPENDED)
3096 nand_release_device(mtd);
3098 pr_err("%s called for a chip which is not in suspended state\n",
3103 /* Set default functions */
3104 static void nand_set_defaults(struct nand_chip *chip, int busw)
3106 /* check for proper chip_delay setup, set 20us if not */
3107 if (!chip->chip_delay)
3108 chip->chip_delay = 20;
3110 /* check, if a user supplied command function given */
3111 if (chip->cmdfunc == NULL)
3112 chip->cmdfunc = nand_command;
3114 /* check, if a user supplied wait function given */
3115 if (chip->waitfunc == NULL)
3116 chip->waitfunc = nand_wait;
3118 if (!chip->select_chip)
3119 chip->select_chip = nand_select_chip;
3121 /* set for ONFI nand */
3122 if (!chip->onfi_set_features)
3123 chip->onfi_set_features = nand_onfi_set_features;
3124 if (!chip->onfi_get_features)
3125 chip->onfi_get_features = nand_onfi_get_features;
3127 /* If called twice, pointers that depend on busw may need to be reset */
3128 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3129 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3130 if (!chip->read_word)
3131 chip->read_word = nand_read_word;
3132 if (!chip->block_bad)
3133 chip->block_bad = nand_block_bad;
3134 if (!chip->block_markbad)
3135 chip->block_markbad = nand_default_block_markbad;
3136 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3137 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3138 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3139 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3140 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3141 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3142 if (!chip->scan_bbt)
3143 chip->scan_bbt = nand_default_bbt;
3145 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
3146 if (!chip->verify_buf)
3147 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
3151 if (!chip->controller) {
3152 chip->controller = &chip->hwcontrol;
3153 spin_lock_init(&chip->controller->lock);
3154 init_waitqueue_head(&chip->controller->wq);
3159 /* Sanitize ONFI strings so we can safely print them */
3161 static void sanitize_string(uint8_t *s, size_t len)
3163 static void sanitize_string(char *s, size_t len)
3168 /* Null terminate */
3171 /* Remove non printable chars */
3172 for (i = 0; i < len - 1; i++) {
3173 if (s[i] < ' ' || s[i] > 127)
3177 /* Remove trailing spaces */
3181 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3186 for (i = 0; i < 8; i++)
3187 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3193 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3194 /* Parse the Extended Parameter Page. */
3195 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3196 struct nand_chip *chip, struct nand_onfi_params *p)
3198 struct onfi_ext_param_page *ep;
3199 struct onfi_ext_section *s;
3200 struct onfi_ext_ecc_info *ecc;
3206 len = le16_to_cpu(p->ext_param_page_length) * 16;
3207 ep = kmalloc(len, GFP_KERNEL);
3211 /* Send our own NAND_CMD_PARAM. */
3212 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3214 /* Use the Change Read Column command to skip the ONFI param pages. */
3215 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3216 sizeof(*p) * p->num_of_param_pages , -1);
3218 /* Read out the Extended Parameter Page. */
3219 chip->read_buf(mtd, (uint8_t *)ep, len);
3220 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3221 != le16_to_cpu(ep->crc))) {
3222 pr_debug("fail in the CRC.\n");
3227 * Check the signature.
3228 * Do not strictly follow the ONFI spec, maybe changed in future.
3231 if (strncmp(ep->sig, "EPPS", 4)) {
3233 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3235 pr_debug("The signature is invalid.\n");
3239 /* find the ECC section. */
3240 cursor = (uint8_t *)(ep + 1);
3241 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3242 s = ep->sections + i;
3243 if (s->type == ONFI_SECTION_TYPE_2)
3245 cursor += s->length * 16;
3247 if (i == ONFI_EXT_SECTION_MAX) {
3248 pr_debug("We can not find the ECC section.\n");
3252 /* get the info we want. */
3253 ecc = (struct onfi_ext_ecc_info *)cursor;
3255 if (!ecc->codeword_size) {
3256 pr_debug("Invalid codeword size\n");
3260 chip->ecc_strength_ds = ecc->ecc_bits;
3261 chip->ecc_step_ds = 1 << ecc->codeword_size;
3269 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3271 struct nand_chip *chip = mtd->priv;
3272 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3274 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3279 * Configure chip properties from Micron vendor-specific ONFI table
3281 static void nand_onfi_detect_micron(struct nand_chip *chip,
3282 struct nand_onfi_params *p)
3284 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3286 if (le16_to_cpu(p->vendor_revision) < 1)
3289 chip->read_retries = micron->read_retry_options;
3290 chip->setup_read_retry = nand_setup_read_retry_micron;
3294 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3296 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3299 struct nand_onfi_params *p = &chip->onfi_params;
3303 /* Try ONFI for unknown chip or LP */
3304 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3305 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3306 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3309 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3310 for (i = 0; i < 3; i++) {
3311 for (j = 0; j < sizeof(*p); j++)
3312 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3313 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3314 le16_to_cpu(p->crc)) {
3320 pr_err("Could not find valid ONFI parameter page; aborting\n");
3325 val = le16_to_cpu(p->revision);
3327 chip->onfi_version = 23;
3328 else if (val & (1 << 4))
3329 chip->onfi_version = 22;
3330 else if (val & (1 << 3))
3331 chip->onfi_version = 21;
3332 else if (val & (1 << 2))
3333 chip->onfi_version = 20;
3334 else if (val & (1 << 1))
3335 chip->onfi_version = 10;
3337 if (!chip->onfi_version) {
3338 pr_info("unsupported ONFI version: %d\n", val);
3342 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3343 sanitize_string(p->model, sizeof(p->model));
3345 mtd->name = p->model;
3347 mtd->writesize = le32_to_cpu(p->byte_per_page);
3350 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3351 * (don't ask me who thought of this...). MTD assumes that these
3352 * dimensions will be power-of-2, so just truncate the remaining area.
3354 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3355 mtd->erasesize *= mtd->writesize;
3357 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3359 /* See erasesize comment */
3360 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3361 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3362 chip->bits_per_cell = p->bits_per_cell;
3364 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3365 *busw = NAND_BUSWIDTH_16;
3369 if (p->ecc_bits != 0xff) {
3370 chip->ecc_strength_ds = p->ecc_bits;
3371 chip->ecc_step_ds = 512;
3372 } else if (chip->onfi_version >= 21 &&
3373 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3376 * The nand_flash_detect_ext_param_page() uses the
3377 * Change Read Column command which maybe not supported
3378 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3379 * now. We do not replace user supplied command function.
3381 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3382 chip->cmdfunc = nand_command_lp;
3384 /* The Extended Parameter Page is supported since ONFI 2.1. */
3385 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3386 pr_warn("Failed to detect ONFI extended param page\n");
3388 pr_warn("Could not retrieve ONFI ECC requirements\n");
3391 if (p->jedec_id == NAND_MFR_MICRON)
3392 nand_onfi_detect_micron(chip, p);
3397 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3405 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3407 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3410 struct nand_jedec_params *p = &chip->jedec_params;
3411 struct jedec_ecc_info *ecc;
3415 /* Try JEDEC for unknown chip or LP */
3416 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3417 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3418 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3419 chip->read_byte(mtd) != 'C')
3422 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3423 for (i = 0; i < 3; i++) {
3424 for (j = 0; j < sizeof(*p); j++)
3425 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3427 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3428 le16_to_cpu(p->crc))
3433 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3438 val = le16_to_cpu(p->revision);
3440 chip->jedec_version = 10;
3441 else if (val & (1 << 1))
3442 chip->jedec_version = 1; /* vendor specific version */
3444 if (!chip->jedec_version) {
3445 pr_info("unsupported JEDEC version: %d\n", val);
3449 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3450 sanitize_string(p->model, sizeof(p->model));
3452 mtd->name = p->model;
3454 mtd->writesize = le32_to_cpu(p->byte_per_page);
3456 /* Please reference to the comment for nand_flash_detect_onfi. */
3457 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3458 mtd->erasesize *= mtd->writesize;
3460 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3462 /* Please reference to the comment for nand_flash_detect_onfi. */
3463 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3464 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3465 chip->bits_per_cell = p->bits_per_cell;
3467 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3468 *busw = NAND_BUSWIDTH_16;
3473 ecc = &p->ecc_info[0];
3475 if (ecc->codeword_size >= 9) {
3476 chip->ecc_strength_ds = ecc->ecc_bits;
3477 chip->ecc_step_ds = 1 << ecc->codeword_size;
3479 pr_warn("Invalid codeword size\n");
3486 * nand_id_has_period - Check if an ID string has a given wraparound period
3487 * @id_data: the ID string
3488 * @arrlen: the length of the @id_data array
3489 * @period: the period of repitition
3491 * Check if an ID string is repeated within a given sequence of bytes at
3492 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3493 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3494 * if the repetition has a period of @period; otherwise, returns zero.
3496 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3499 for (i = 0; i < period; i++)
3500 for (j = i + period; j < arrlen; j += period)
3501 if (id_data[i] != id_data[j])
3507 * nand_id_len - Get the length of an ID string returned by CMD_READID
3508 * @id_data: the ID string
3509 * @arrlen: the length of the @id_data array
3511 * Returns the length of the ID string, according to known wraparound/trailing
3512 * zero patterns. If no pattern exists, returns the length of the array.
3514 static int nand_id_len(u8 *id_data, int arrlen)
3516 int last_nonzero, period;
3518 /* Find last non-zero byte */
3519 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3520 if (id_data[last_nonzero])
3524 if (last_nonzero < 0)
3527 /* Calculate wraparound period */
3528 for (period = 1; period < arrlen; period++)
3529 if (nand_id_has_period(id_data, arrlen, period))
3532 /* There's a repeated pattern */
3533 if (period < arrlen)
3536 /* There are trailing zeros */
3537 if (last_nonzero < arrlen - 1)
3538 return last_nonzero + 1;
3540 /* No pattern detected */
3544 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3545 static int nand_get_bits_per_cell(u8 cellinfo)
3549 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3550 bits >>= NAND_CI_CELLTYPE_SHIFT;
3555 * Many new NAND share similar device ID codes, which represent the size of the
3556 * chip. The rest of the parameters must be decoded according to generic or
3557 * manufacturer-specific "extended ID" decoding patterns.
3559 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3560 u8 id_data[8], int *busw)
3563 /* The 3rd id byte holds MLC / multichip data */
3564 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3565 /* The 4th id byte is the important one */
3568 id_len = nand_id_len(id_data, 8);
3571 * Field definitions are in the following datasheets:
3572 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3573 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3574 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3576 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3577 * ID to decide what to do.
3579 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3580 !nand_is_slc(chip) && id_data[5] != 0x00) {
3582 mtd->writesize = 2048 << (extid & 0x03);
3585 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3605 default: /* Other cases are "reserved" (unknown) */
3606 mtd->oobsize = 1024;
3610 /* Calc blocksize */
3611 mtd->erasesize = (128 * 1024) <<
3612 (((extid >> 1) & 0x04) | (extid & 0x03));
3614 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3615 !nand_is_slc(chip)) {
3619 mtd->writesize = 2048 << (extid & 0x03);
3622 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3646 /* Calc blocksize */
3647 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3649 mtd->erasesize = (128 * 1024) << tmp;
3650 else if (tmp == 0x03)
3651 mtd->erasesize = 768 * 1024;
3653 mtd->erasesize = (64 * 1024) << tmp;
3657 mtd->writesize = 1024 << (extid & 0x03);
3660 mtd->oobsize = (8 << (extid & 0x01)) *
3661 (mtd->writesize >> 9);
3663 /* Calc blocksize. Blocksize is multiples of 64KiB */
3664 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3666 /* Get buswidth information */
3667 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3670 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3671 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3673 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3675 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3677 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3678 nand_is_slc(chip) &&
3679 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3680 !(id_data[4] & 0x80) /* !BENAND */) {
3681 mtd->oobsize = 32 * mtd->writesize >> 9;
3688 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3689 * decodes a matching ID table entry and assigns the MTD size parameters for
3692 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3693 struct nand_flash_dev *type, u8 id_data[8],
3696 int maf_id = id_data[0];
3698 mtd->erasesize = type->erasesize;
3699 mtd->writesize = type->pagesize;
3700 mtd->oobsize = mtd->writesize / 32;
3701 *busw = type->options & NAND_BUSWIDTH_16;
3703 /* All legacy ID NAND are small-page, SLC */
3704 chip->bits_per_cell = 1;
3707 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3708 * some Spansion chips have erasesize that conflicts with size
3709 * listed in nand_ids table.
3710 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3712 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3713 && id_data[6] == 0x00 && id_data[7] == 0x00
3714 && mtd->writesize == 512) {
3715 mtd->erasesize = 128 * 1024;
3716 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3721 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3722 * heuristic patterns using various detected parameters (e.g., manufacturer,
3723 * page size, cell-type information).
3725 static void nand_decode_bbm_options(struct mtd_info *mtd,
3726 struct nand_chip *chip, u8 id_data[8])
3728 int maf_id = id_data[0];
3730 /* Set the bad block position */
3731 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3732 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3734 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3737 * Bad block marker is stored in the last page of each block on Samsung
3738 * and Hynix MLC devices; stored in first two pages of each block on
3739 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3740 * AMD/Spansion, and Macronix. All others scan only the first page.
3742 if (!nand_is_slc(chip) &&
3743 (maf_id == NAND_MFR_SAMSUNG ||
3744 maf_id == NAND_MFR_HYNIX))
3745 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3746 else if ((nand_is_slc(chip) &&
3747 (maf_id == NAND_MFR_SAMSUNG ||
3748 maf_id == NAND_MFR_HYNIX ||
3749 maf_id == NAND_MFR_TOSHIBA ||
3750 maf_id == NAND_MFR_AMD ||
3751 maf_id == NAND_MFR_MACRONIX)) ||
3752 (mtd->writesize == 2048 &&
3753 maf_id == NAND_MFR_MICRON))
3754 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3757 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3759 return type->id_len;
3762 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3763 struct nand_flash_dev *type, u8 *id_data, int *busw)
3766 if (!strncmp(type->id, id_data, type->id_len)) {
3768 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3770 mtd->writesize = type->pagesize;
3771 mtd->erasesize = type->erasesize;
3772 mtd->oobsize = type->oobsize;
3774 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3775 chip->chipsize = (uint64_t)type->chipsize << 20;
3776 chip->options |= type->options;
3777 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3778 chip->ecc_step_ds = NAND_ECC_STEP(type);
3780 *busw = type->options & NAND_BUSWIDTH_16;
3783 mtd->name = type->name;
3791 * Get the flash and manufacturer id and lookup if the type is supported.
3793 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3794 struct nand_chip *chip,
3795 int *maf_id, int *dev_id,
3796 struct nand_flash_dev *type)
3802 /* Select the device */
3803 chip->select_chip(mtd, 0);
3806 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3809 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3811 /* Send the command for reading device ID */
3812 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3814 /* Read manufacturer and device IDs */
3815 *maf_id = chip->read_byte(mtd);
3816 *dev_id = chip->read_byte(mtd);
3819 * Try again to make sure, as some systems the bus-hold or other
3820 * interface concerns can cause random data which looks like a
3821 * possibly credible NAND flash to appear. If the two results do
3822 * not match, ignore the device completely.
3825 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3827 /* Read entire ID string */
3828 for (i = 0; i < 8; i++)
3829 id_data[i] = chip->read_byte(mtd);
3831 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3832 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3833 *maf_id, *dev_id, id_data[0], id_data[1]);
3834 return ERR_PTR(-ENODEV);
3838 type = nand_flash_ids;
3840 for (; type->name != NULL; type++) {
3841 if (is_full_id_nand(type)) {
3842 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3844 } else if (*dev_id == type->dev_id) {
3849 chip->onfi_version = 0;
3850 if (!type->name || !type->pagesize) {
3851 /* Check is chip is ONFI compliant */
3852 if (nand_flash_detect_onfi(mtd, chip, &busw))
3855 /* Check if the chip is JEDEC compliant */
3856 if (nand_flash_detect_jedec(mtd, chip, &busw))
3861 return ERR_PTR(-ENODEV);
3864 mtd->name = type->name;
3866 chip->chipsize = (uint64_t)type->chipsize << 20;
3868 if (!type->pagesize && chip->init_size) {
3869 /* Set the pagesize, oobsize, erasesize by the driver */
3870 busw = chip->init_size(mtd, chip, id_data);
3871 } else if (!type->pagesize) {
3872 /* Decode parameters from extended ID */
3873 nand_decode_ext_id(mtd, chip, id_data, &busw);
3875 nand_decode_id(mtd, chip, type, id_data, &busw);
3877 /* Get chip options */
3878 chip->options |= type->options;
3881 * Check if chip is not a Samsung device. Do not clear the
3882 * options for chips which do not have an extended id.
3884 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3885 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3888 /* Try to identify manufacturer */
3889 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3890 if (nand_manuf_ids[maf_idx].id == *maf_id)
3894 if (chip->options & NAND_BUSWIDTH_AUTO) {
3895 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3896 chip->options |= busw;
3897 nand_set_defaults(chip, busw);
3898 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3900 * Check, if buswidth is correct. Hardware drivers should set
3903 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3905 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3906 pr_warn("bus width %d instead %d bit\n",
3907 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3909 return ERR_PTR(-EINVAL);
3912 nand_decode_bbm_options(mtd, chip, id_data);
3914 /* Calculate the address shift from the page size */
3915 chip->page_shift = ffs(mtd->writesize) - 1;
3916 /* Convert chipsize to number of pages per chip -1 */
3917 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3919 chip->bbt_erase_shift = chip->phys_erase_shift =
3920 ffs(mtd->erasesize) - 1;
3921 if (chip->chipsize & 0xffffffff)
3922 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3924 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3925 chip->chip_shift += 32 - 1;
3928 chip->badblockbits = 8;
3929 chip->erase_cmd = single_erase_cmd;
3931 /* Do not replace user supplied command function! */
3932 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3933 chip->cmdfunc = nand_command_lp;
3935 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3938 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3939 if (chip->onfi_version)
3940 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3941 chip->onfi_params.model);
3942 else if (chip->jedec_version)
3943 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3944 chip->jedec_params.model);
3946 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3949 if (chip->jedec_version)
3950 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3951 chip->jedec_params.model);
3953 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3956 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3960 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3961 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3962 mtd->writesize, mtd->oobsize);
3967 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3968 * @mtd: MTD device structure
3969 * @maxchips: number of chips to scan for
3970 * @table: alternative NAND ID table
3972 * This is the first phase of the normal nand_scan() function. It reads the
3973 * flash ID and sets up MTD fields accordingly.
3975 * The mtd->owner field must be set to the module of the caller.
3977 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3978 struct nand_flash_dev *table)
3980 int i, nand_maf_id, nand_dev_id;
3981 struct nand_chip *chip = mtd->priv;
3982 struct nand_flash_dev *type;
3984 /* Set the default functions */
3985 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3987 /* Read the flash type */
3988 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3989 &nand_dev_id, table);
3992 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3993 pr_warn("No NAND device found\n");
3994 chip->select_chip(mtd, -1);
3995 return PTR_ERR(type);
3998 chip->select_chip(mtd, -1);
4000 /* Check for a chip array */
4001 for (i = 1; i < maxchips; i++) {
4002 chip->select_chip(mtd, i);
4003 /* See comment in nand_get_flash_type for reset */
4004 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4005 /* Send the command for reading device ID */
4006 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4007 /* Read manufacturer and device IDs */
4008 if (nand_maf_id != chip->read_byte(mtd) ||
4009 nand_dev_id != chip->read_byte(mtd)) {
4010 chip->select_chip(mtd, -1);
4013 chip->select_chip(mtd, -1);
4018 pr_info("%d chips detected\n", i);
4021 /* Store the number of chips and calc total size for mtd */
4023 mtd->size = i * chip->chipsize;
4027 EXPORT_SYMBOL(nand_scan_ident);
4031 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4032 * @mtd: MTD device structure
4034 * This is the second phase of the normal nand_scan() function. It fills out
4035 * all the uninitialized function pointers with the defaults and scans for a
4036 * bad block table if appropriate.
4038 int nand_scan_tail(struct mtd_info *mtd)
4041 struct nand_chip *chip = mtd->priv;
4042 struct nand_ecc_ctrl *ecc = &chip->ecc;
4043 struct nand_buffers *nbuf;
4045 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4046 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4047 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4049 if (!(chip->options & NAND_OWN_BUFFERS)) {
4051 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4052 + mtd->oobsize * 3, GFP_KERNEL);
4055 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4056 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4057 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4059 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4062 chip->buffers = nbuf;
4068 /* Set the internal oob buffer location, just after the page data */
4069 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4072 * If no default placement scheme is given, select an appropriate one.
4074 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4075 switch (mtd->oobsize) {
4077 ecc->layout = &nand_oob_8;
4080 ecc->layout = &nand_oob_16;
4083 ecc->layout = &nand_oob_64;
4086 ecc->layout = &nand_oob_128;
4089 pr_warn("No oob scheme defined for oobsize %d\n",
4095 if (!chip->write_page)
4096 chip->write_page = nand_write_page;
4099 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4100 * selected and we have 256 byte pagesize fallback to software ECC
4103 switch (ecc->mode) {
4104 case NAND_ECC_HW_OOB_FIRST:
4105 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4106 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4107 pr_warn("No ECC functions supplied; "
4108 "hardware ECC not possible\n");
4111 if (!ecc->read_page)
4112 ecc->read_page = nand_read_page_hwecc_oob_first;
4115 /* Use standard hwecc read page function? */
4116 if (!ecc->read_page)
4117 ecc->read_page = nand_read_page_hwecc;
4118 if (!ecc->write_page)
4119 ecc->write_page = nand_write_page_hwecc;
4120 if (!ecc->read_page_raw)
4121 ecc->read_page_raw = nand_read_page_raw;
4122 if (!ecc->write_page_raw)
4123 ecc->write_page_raw = nand_write_page_raw;
4125 ecc->read_oob = nand_read_oob_std;
4126 if (!ecc->write_oob)
4127 ecc->write_oob = nand_write_oob_std;
4128 if (!ecc->read_subpage)
4129 ecc->read_subpage = nand_read_subpage;
4130 if (!ecc->write_subpage)
4131 ecc->write_subpage = nand_write_subpage_hwecc;
4133 case NAND_ECC_HW_SYNDROME:
4134 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4136 ecc->read_page == nand_read_page_hwecc ||
4138 ecc->write_page == nand_write_page_hwecc)) {
4139 pr_warn("No ECC functions supplied; "
4140 "hardware ECC not possible\n");
4143 /* Use standard syndrome read/write page function? */
4144 if (!ecc->read_page)
4145 ecc->read_page = nand_read_page_syndrome;
4146 if (!ecc->write_page)
4147 ecc->write_page = nand_write_page_syndrome;
4148 if (!ecc->read_page_raw)
4149 ecc->read_page_raw = nand_read_page_raw_syndrome;
4150 if (!ecc->write_page_raw)
4151 ecc->write_page_raw = nand_write_page_raw_syndrome;
4153 ecc->read_oob = nand_read_oob_syndrome;
4154 if (!ecc->write_oob)
4155 ecc->write_oob = nand_write_oob_syndrome;
4157 if (mtd->writesize >= ecc->size) {
4158 if (!ecc->strength) {
4159 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4164 pr_warn("%d byte HW ECC not possible on "
4165 "%d byte page size, fallback to SW ECC\n",
4166 ecc->size, mtd->writesize);
4167 ecc->mode = NAND_ECC_SOFT;
4170 ecc->calculate = nand_calculate_ecc;
4171 ecc->correct = nand_correct_data;
4172 ecc->read_page = nand_read_page_swecc;
4173 ecc->read_subpage = nand_read_subpage;
4174 ecc->write_page = nand_write_page_swecc;
4175 ecc->read_page_raw = nand_read_page_raw;
4176 ecc->write_page_raw = nand_write_page_raw;
4177 ecc->read_oob = nand_read_oob_std;
4178 ecc->write_oob = nand_write_oob_std;
4185 case NAND_ECC_SOFT_BCH:
4186 if (!mtd_nand_has_bch()) {
4187 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4190 ecc->calculate = nand_bch_calculate_ecc;
4191 ecc->correct = nand_bch_correct_data;
4192 ecc->read_page = nand_read_page_swecc;
4193 ecc->read_subpage = nand_read_subpage;
4194 ecc->write_page = nand_write_page_swecc;
4195 ecc->read_page_raw = nand_read_page_raw;
4196 ecc->write_page_raw = nand_write_page_raw;
4197 ecc->read_oob = nand_read_oob_std;
4198 ecc->write_oob = nand_write_oob_std;
4200 * Board driver should supply ecc.size and ecc.bytes values to
4201 * select how many bits are correctable; see nand_bch_init()
4202 * for details. Otherwise, default to 4 bits for large page
4205 if (!ecc->size && (mtd->oobsize >= 64)) {
4209 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4212 pr_warn("BCH ECC initialization failed!\n");
4215 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
4219 pr_warn("NAND_ECC_NONE selected by board driver. "
4220 "This is not recommended!\n");
4221 ecc->read_page = nand_read_page_raw;
4222 ecc->write_page = nand_write_page_raw;
4223 ecc->read_oob = nand_read_oob_std;
4224 ecc->read_page_raw = nand_read_page_raw;
4225 ecc->write_page_raw = nand_write_page_raw;
4226 ecc->write_oob = nand_write_oob_std;
4227 ecc->size = mtd->writesize;
4233 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4237 /* For many systems, the standard OOB write also works for raw */
4238 if (!ecc->read_oob_raw)
4239 ecc->read_oob_raw = ecc->read_oob;
4240 if (!ecc->write_oob_raw)
4241 ecc->write_oob_raw = ecc->write_oob;
4244 * The number of bytes available for a client to place data into
4245 * the out of band area.
4247 ecc->layout->oobavail = 0;
4248 for (i = 0; ecc->layout->oobfree[i].length
4249 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4250 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4251 mtd->oobavail = ecc->layout->oobavail;
4254 * Set the number of read / write steps for one page depending on ECC
4257 ecc->steps = mtd->writesize / ecc->size;
4258 if (ecc->steps * ecc->size != mtd->writesize) {
4259 pr_warn("Invalid ECC parameters\n");
4262 ecc->total = ecc->steps * ecc->bytes;
4264 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4265 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4266 switch (ecc->steps) {
4268 mtd->subpage_sft = 1;
4273 mtd->subpage_sft = 2;
4277 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4279 /* Initialize state */
4280 chip->state = FL_READY;
4282 /* Invalidate the pagebuffer reference */
4285 /* Large page NAND with SOFT_ECC should support subpage reads */
4286 if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4287 chip->options |= NAND_SUBPAGE_READ;
4289 /* Fill in remaining MTD driver data */
4290 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4291 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4293 mtd->_erase = nand_erase;
4296 mtd->_unpoint = NULL;
4298 mtd->_read = nand_read;
4299 mtd->_write = nand_write;
4300 mtd->_panic_write = panic_nand_write;
4301 mtd->_read_oob = nand_read_oob;
4302 mtd->_write_oob = nand_write_oob;
4303 mtd->_sync = nand_sync;
4305 mtd->_unlock = NULL;
4307 mtd->_suspend = nand_suspend;
4308 mtd->_resume = nand_resume;
4310 mtd->_block_isbad = nand_block_isbad;
4311 mtd->_block_markbad = nand_block_markbad;
4312 mtd->writebufsize = mtd->writesize;
4314 /* propagate ecc info to mtd_info */
4315 mtd->ecclayout = ecc->layout;
4316 mtd->ecc_strength = ecc->strength;
4317 mtd->ecc_step_size = ecc->size;
4319 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4320 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4323 if (!mtd->bitflip_threshold)
4324 mtd->bitflip_threshold = mtd->ecc_strength;
4326 /* Check, if we should skip the bad block table scan */
4327 if (chip->options & NAND_SKIP_BBTSCAN)
4330 /* Build bad block table */
4331 return chip->scan_bbt(mtd);
4333 EXPORT_SYMBOL(nand_scan_tail);
4336 * is_module_text_address() isn't exported, and it's mostly a pointless
4337 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4338 * to call us from in-kernel code if the core NAND support is modular.
4341 #define caller_is_module() (1)
4343 #define caller_is_module() \
4344 is_module_text_address((unsigned long)__builtin_return_address(0))
4348 * nand_scan - [NAND Interface] Scan for the NAND device
4349 * @mtd: MTD device structure
4350 * @maxchips: number of chips to scan for
4352 * This fills out all the uninitialized function pointers with the defaults.
4353 * The flash ID is read and the mtd/chip structures are filled with the
4354 * appropriate values. The mtd->owner field must be set to the module of the
4357 int nand_scan(struct mtd_info *mtd, int maxchips)
4361 /* Many callers got this wrong, so check for it for a while... */
4362 if (!mtd->owner && caller_is_module()) {
4363 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4367 ret = nand_scan_ident(mtd, maxchips, NULL);
4369 ret = nand_scan_tail(mtd);
4372 EXPORT_SYMBOL(nand_scan);
4376 * nand_release - [NAND Interface] Free resources held by the NAND device
4377 * @mtd: MTD device structure
4379 void nand_release(struct mtd_info *mtd)
4381 struct nand_chip *chip = mtd->priv;
4383 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4384 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4386 mtd_device_unregister(mtd);
4388 /* Free bad block table memory */
4390 if (!(chip->options & NAND_OWN_BUFFERS))
4391 kfree(chip->buffers);
4393 /* Free bad block descriptor memory */
4394 if (chip->badblock_pattern && chip->badblock_pattern->options
4395 & NAND_BBT_DYNAMICSTRUCT)
4396 kfree(chip->badblock_pattern);
4398 EXPORT_SYMBOL_GPL(nand_release);
4400 static int __init nand_base_init(void)
4402 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4406 static void __exit nand_base_exit(void)
4408 led_trigger_unregister_simple(nand_led_trigger);
4412 module_init(nand_base_init);
4413 module_exit(nand_base_exit);
4415 MODULE_LICENSE("GPL");
4416 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4417 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4418 MODULE_DESCRIPTION("Generic NAND flash driver code");