2 * (C) Copyright 2006-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <linux/mtd/nand_ecc.h>
26 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
27 static nand_info_t mtd;
28 static struct nand_chip nand_chip;
30 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
32 * NAND command for small page NAND devices (512)
34 static int nand_command(int block, int page, uint32_t offs,
37 struct nand_chip *this = mtd.priv;
38 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
40 while (!this->dev_ready(&mtd))
43 /* Begin command latch cycle */
44 this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
45 /* Set ALE and clear CLE to start address cycle */
47 this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
48 this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
49 this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
50 NAND_CTRL_ALE); /* A[24:17] */
51 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
52 /* One more address cycle for devices > 32MiB */
53 this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
54 NAND_CTRL_ALE); /* A[28:25] */
56 /* Latch in address */
57 this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
60 * Wait a while for the data to be ready
62 while (!this->dev_ready(&mtd))
69 * NAND command for large page NAND devices (2k)
71 static int nand_command(int block, int page, uint32_t offs,
74 struct nand_chip *this = mtd.priv;
75 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
76 void (*hwctrl)(struct mtd_info *mtd, int cmd,
77 unsigned int ctrl) = this->cmd_ctrl;
79 while (!this->dev_ready(&mtd))
82 /* Emulate NAND_CMD_READOOB */
83 if (cmd == NAND_CMD_READOOB) {
84 offs += CONFIG_SYS_NAND_PAGE_SIZE;
88 /* Shift the offset from byte addressing to word addressing. */
89 if (this->options & NAND_BUSWIDTH_16)
92 /* Begin command latch cycle */
93 hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
94 /* Set ALE and clear CLE to start address cycle */
96 hwctrl(&mtd, offs & 0xff,
97 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
98 hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
100 hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
101 hwctrl(&mtd, ((page_addr >> 8) & 0xff),
102 NAND_CTRL_ALE); /* A[27:20] */
103 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
104 /* One more address cycle for devices > 128MiB */
105 hwctrl(&mtd, (page_addr >> 16) & 0x0f,
106 NAND_CTRL_ALE); /* A[31:28] */
108 /* Latch in address */
109 hwctrl(&mtd, NAND_CMD_READSTART,
110 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
111 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
114 * Wait a while for the data to be ready
116 while (!this->dev_ready(&mtd))
123 static int nand_is_bad_block(int block)
125 struct nand_chip *this = mtd.priv;
127 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
131 * Read one byte (or two if it's a 16 bit chip).
133 if (this->options & NAND_BUSWIDTH_16) {
134 if (readw(this->IO_ADDR_R) != 0xffff)
137 if (readb(this->IO_ADDR_R) != 0xff)
144 #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
145 static int nand_read_page(int block, int page, uchar *dst)
147 struct nand_chip *this = mtd.priv;
152 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
153 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
154 int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
158 * No malloc available for now, just use some temporary locations
161 ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
162 ecc_code = ecc_calc + 0x100;
163 oob_data = ecc_calc + 0x200;
165 nand_command(block, page, 0, NAND_CMD_READOOB);
166 this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
167 nand_command(block, page, 0, NAND_CMD_READ0);
169 /* Pick the ECC bytes out of the oob data */
170 for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
171 ecc_code[i] = oob_data[nand_ecc_pos[i]];
174 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
175 this->ecc.hwctl(&mtd, NAND_ECC_READ);
176 this->read_buf(&mtd, p, eccsize);
177 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
178 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
184 static int nand_read_page(int block, int page, void *dst)
186 struct nand_chip *this = mtd.priv;
191 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
192 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
193 int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
196 nand_command(block, page, 0, NAND_CMD_READ0);
198 /* No malloc available for now, just use some temporary locations
201 ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
202 ecc_code = ecc_calc + 0x100;
203 oob_data = ecc_calc + 0x200;
205 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
206 if (this->ecc.mode != NAND_ECC_SOFT)
207 this->ecc.hwctl(&mtd, NAND_ECC_READ);
208 this->read_buf(&mtd, p, eccsize);
209 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
211 this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
213 /* Pick the ECC bytes out of the oob data */
214 for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
215 ecc_code[i] = oob_data[nand_ecc_pos[i]];
217 eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
220 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
221 /* No chance to do something with the possible error message
222 * from correct_data(). We just hope that all possible errors
223 * are corrected by this routine.
225 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
232 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
234 unsigned int block, lastblock;
238 * offs has to be aligned to a page address!
240 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
241 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
242 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
244 while (block <= lastblock) {
245 if (!nand_is_bad_block(block)) {
249 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
250 nand_read_page(block, page, dst);
251 dst += CONFIG_SYS_NAND_PAGE_SIZE;
266 /* nand_init() - initialize data to make nand usable by SPL */
270 * Init board specific nand support
272 mtd.priv = &nand_chip;
273 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
274 (void __iomem *)CONFIG_SYS_NAND_BASE;
275 board_nand_init(&nand_chip);
277 #ifdef CONFIG_SPL_NAND_SOFTECC
278 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
279 nand_chip.ecc.calculate = nand_calculate_ecc;
280 nand_chip.ecc.correct = nand_correct_data;
284 if (nand_chip.select_chip)
285 nand_chip.select_chip(&mtd, 0);
288 /* Unselect after operation */
289 void nand_deselect(void)
291 if (nand_chip.select_chip)
292 nand_chip.select_chip(&mtd, -1);