2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/errno.h>
27 #include <asm/arch/mem.h>
28 #include <asm/arch/omap_gpmc.h>
29 #include <linux/mtd/nand_ecc.h>
33 static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
34 static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
37 * omap_nand_hwcontrol - Set the address pointers corretly for the
38 * following address/data/command operation
40 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
43 register struct nand_chip *this = mtd->priv;
46 * Point the IO_ADDR to DATA and ADDRESS registers instead
50 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
51 this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd;
53 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
54 this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_adr;
56 case NAND_CTRL_CHANGE | NAND_NCE:
57 this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_dat;
61 if (cmd != NAND_CMD_NONE)
62 writeb(cmd, this->IO_ADDR_W);
66 * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
68 * @mtd: MTD device structure
71 static void omap_hwecc_init(struct nand_chip *chip)
74 * Init ECC Control Register
75 * Clear all ECC | Enable Reg1
77 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
78 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_base->ecc_size_config);
82 * gen_true_ecc - This function will generate true ECC value, which
83 * can be used when correcting data read from NAND flash memory core
85 * @ecc_buf: buffer to store ecc code
87 * @return: re-formatted ECC value
89 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
91 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
92 ((ecc_buf[2] & 0x0F) << 8);
96 * omap_correct_data - Compares the ecc read from nand spare area with ECC
97 * registers values and corrects one bit error if it has occured
98 * Further details can be had from OMAP TRM and the following selected links:
99 * http://en.wikipedia.org/wiki/Hamming_code
100 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
102 * @mtd: MTD device structure
104 * @read_ecc: ecc read from nand flash
105 * @calc_ecc: ecc read from ECC registers
107 * @return 0 if data is OK or corrected, else returns -1
109 static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
110 uint8_t *read_ecc, uint8_t *calc_ecc)
112 uint32_t orig_ecc, new_ecc, res, hm;
113 uint16_t parity_bits, byte;
116 /* Regenerate the orginal ECC */
117 orig_ecc = gen_true_ecc(read_ecc);
118 new_ecc = gen_true_ecc(calc_ecc);
119 /* Get the XOR of real ecc */
120 res = orig_ecc ^ new_ecc;
122 /* Get the hamming width */
124 /* Single bit errors can be corrected! */
126 /* Correctable data! */
127 parity_bits = res >> 16;
128 bit = (parity_bits & 0x7);
129 byte = (parity_bits >> 3) & 0x1FF;
130 /* Flip the bit to correct */
131 dat[byte] ^= (0x1 << bit);
132 } else if (hm == 1) {
133 printf("Error: Ecc is wrong\n");
134 /* ECC itself is corrupted */
138 * hm distance != parity pairs OR one, could mean 2 bit
139 * error OR potentially be on a blank page..
140 * orig_ecc: contains spare area data from nand flash.
141 * new_ecc: generated ecc while reading data area.
142 * Note: if the ecc = 0, all data bits from which it was
143 * generated are 0xFF.
144 * The 3 byte(24 bits) ecc is generated per 512byte
145 * chunk of a page. If orig_ecc(from spare area)
146 * is 0xFF && new_ecc(computed now from data area)=0x0,
147 * this means that data area is 0xFF and spare area is
148 * 0xFF. A sure sign of a erased page!
150 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
152 printf("Error: Bad compare! failed\n");
153 /* detected 2 bit error */
161 * omap_calculate_ecc - Generate non-inverted ECC bytes.
163 * Using noninverted ECC can be considered ugly since writing a blank
164 * page ie. padding will clear the ECC bytes. This is no problem as
165 * long nobody is trying to write data on the seemingly unused page.
166 * Reading an erased page will produce an ECC mismatch between
167 * generated and read ECC bytes that has to be dealt with separately.
168 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
169 * is used, the result of read will be 0x0 while the ECC offsets of the
170 * spare area will be 0xFF which will result in an ECC mismatch.
171 * @mtd: MTD structure
173 * @ecc_code: ecc_code buffer
175 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
180 /* Start Reading from HW ECC1_Result = 0x200 */
181 val = readl(&gpmc_base->ecc1_result);
183 ecc_code[0] = val & 0xFF;
184 ecc_code[1] = (val >> 16) & 0xFF;
185 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
188 * Stop reading anymore ECC vals and clear old results
189 * enable will be called if more reads are required
191 writel(0x000, &gpmc_base->ecc_config);
197 * omap_enable_ecc - This function enables the hardware ecc functionality
198 * @mtd: MTD device structure
199 * @mode: Read/Write mode
201 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
203 struct nand_chip *chip = mtd->priv;
204 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
209 /* Clear the ecc result registers, select ecc reg as 1 */
210 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
213 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
214 * tell all regs to generate size0 sized regs
215 * we just have a single ECC engine for all CS
217 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
218 &gpmc_base->ecc_size_config);
219 val = (dev_width << 7) | (cs << 1) | (0x1);
220 writel(val, &gpmc_base->ecc_config);
223 printf("Error: Unrecognized Mode[%d]!\n", mode);
229 * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
230 * The default is to come up on s/w ecc
232 * @hardware - 1 -switch to h/w ecc, 0 - s/w ecc
235 void omap_nand_switch_ecc(int32_t hardware)
237 struct nand_chip *nand;
238 struct mtd_info *mtd;
240 if (nand_curr_device < 0 ||
241 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
242 !nand_info[nand_curr_device].name) {
243 printf("Error: Can't switch ecc, no devices available\n");
247 mtd = &nand_info[nand_curr_device];
250 nand->options |= NAND_OWN_BUFFERS;
252 /* Reset ecc interface */
253 nand->ecc.read_page = NULL;
254 nand->ecc.write_page = NULL;
255 nand->ecc.read_oob = NULL;
256 nand->ecc.write_oob = NULL;
257 nand->ecc.hwctl = NULL;
258 nand->ecc.correct = NULL;
259 nand->ecc.calculate = NULL;
261 /* Setup the ecc configurations again */
263 nand->ecc.mode = NAND_ECC_HW;
264 nand->ecc.layout = &hw_nand_oob;
265 nand->ecc.size = 512;
267 nand->ecc.hwctl = omap_enable_hwecc;
268 nand->ecc.correct = omap_correct_data;
269 nand->ecc.calculate = omap_calculate_ecc;
270 omap_hwecc_init(nand);
271 printf("HW ECC selected\n");
273 nand->ecc.mode = NAND_ECC_SOFT;
274 /* Use mtd default settings */
275 nand->ecc.layout = NULL;
276 printf("SW ECC selected\n");
279 /* Update NAND handling after ECC mode switch */
282 nand->options &= ~NAND_OWN_BUFFERS;
286 * Board-specific NAND initialization. The following members of the
287 * argument are board-specific:
288 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
289 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
290 * - cmd_ctrl: hardwarespecific function for accesing control-lines
291 * - waitfunc: hardwarespecific function for accesing device ready/busy line
292 * - ecc.hwctl: function to enable (reset) hardware ecc generator
293 * - ecc.mode: mode of ecc, see defines
294 * - chip_delay: chip dependent delay for transfering data from array to
296 * - options: various chip options. They can partly be set to inform
297 * nand_scan about special functionality. See the defines for further
300 int board_nand_init(struct nand_chip *nand)
302 int32_t gpmc_config = 0;
306 * xloader/Uboot's gpmc configuration would have configured GPMC for
307 * nand type of memory. The following logic scans and latches on to the
308 * first CS with NAND type memory.
309 * TBD: need to make this logic generic to handle multiple CS NAND
312 while (cs < GPMC_MAX_CS) {
313 /* Check if NAND type is set */
314 if ((readl(&gpmc_base->cs[cs].config1) & 0xC00) == 0x800) {
320 if (cs >= GPMC_MAX_CS) {
321 printf("NAND: Unable to find NAND settings in "
322 "GPMC Configuration - quitting\n");
326 gpmc_config = readl(&gpmc_base->config);
327 /* Disable Write protect */
329 writel(gpmc_config, &gpmc_base->config);
331 nand->IO_ADDR_R = (void __iomem *)&gpmc_base->cs[cs].nand_dat;
332 nand->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd;
334 nand->cmd_ctrl = omap_nand_hwcontrol;
335 nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
336 /* If we are 16 bit dev, our gpmc config tells us that */
337 if ((readl(&gpmc_base->cs[cs].config1) & 0x3000) == 0x1000)
338 nand->options |= NAND_BUSWIDTH_16;
340 nand->chip_delay = 100;
341 /* Default ECC mode */
342 nand->ecc.mode = NAND_ECC_SOFT;