2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/mem.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/omap_gpmc.h>
14 #include <linux/mtd/nand_ecc.h>
15 #include <linux/bch.h>
16 #include <linux/compiler.h>
18 #include <asm/omap_elm.h>
20 #define BADBLOCK_MARKER_LENGTH 2
21 #define SECTOR_BYTES 512
22 #define ECCCLEAR (0x1 << 8)
23 #define ECCRESULTREG1 (0x1 << 0)
24 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
25 #define BCH4_BIT_PAD 4
28 static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
29 0x97, 0x79, 0xe5, 0x24, 0xb5};
32 static __maybe_unused struct nand_ecclayout omap_ecclayout;
35 * omap_nand_hwcontrol - Set the address pointers corretly for the
36 * following address/data/command operation
38 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
41 register struct nand_chip *this = mtd->priv;
44 * Point the IO_ADDR to DATA and ADDRESS registers instead
48 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
49 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
51 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
52 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
54 case NAND_CTRL_CHANGE | NAND_NCE:
55 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
59 if (cmd != NAND_CMD_NONE)
60 writeb(cmd, this->IO_ADDR_W);
63 #ifdef CONFIG_SPL_BUILD
64 /* Check wait pin as dev ready indicator */
65 int omap_spl_dev_ready(struct mtd_info *mtd)
67 return gpmc_cfg->status & (1 << 8);
73 * gen_true_ecc - This function will generate true ECC value, which
74 * can be used when correcting data read from NAND flash memory core
76 * @ecc_buf: buffer to store ecc code
78 * @return: re-formatted ECC value
80 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
82 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
83 ((ecc_buf[2] & 0x0F) << 8);
87 * omap_correct_data - Compares the ecc read from nand spare area with ECC
88 * registers values and corrects one bit error if it has occured
89 * Further details can be had from OMAP TRM and the following selected links:
90 * http://en.wikipedia.org/wiki/Hamming_code
91 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
93 * @mtd: MTD device structure
95 * @read_ecc: ecc read from nand flash
96 * @calc_ecc: ecc read from ECC registers
98 * @return 0 if data is OK or corrected, else returns -1
100 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
101 uint8_t *read_ecc, uint8_t *calc_ecc)
103 uint32_t orig_ecc, new_ecc, res, hm;
104 uint16_t parity_bits, byte;
107 /* Regenerate the orginal ECC */
108 orig_ecc = gen_true_ecc(read_ecc);
109 new_ecc = gen_true_ecc(calc_ecc);
110 /* Get the XOR of real ecc */
111 res = orig_ecc ^ new_ecc;
113 /* Get the hamming width */
115 /* Single bit errors can be corrected! */
117 /* Correctable data! */
118 parity_bits = res >> 16;
119 bit = (parity_bits & 0x7);
120 byte = (parity_bits >> 3) & 0x1FF;
121 /* Flip the bit to correct */
122 dat[byte] ^= (0x1 << bit);
123 } else if (hm == 1) {
124 printf("Error: Ecc is wrong\n");
125 /* ECC itself is corrupted */
129 * hm distance != parity pairs OR one, could mean 2 bit
130 * error OR potentially be on a blank page..
131 * orig_ecc: contains spare area data from nand flash.
132 * new_ecc: generated ecc while reading data area.
133 * Note: if the ecc = 0, all data bits from which it was
134 * generated are 0xFF.
135 * The 3 byte(24 bits) ecc is generated per 512byte
136 * chunk of a page. If orig_ecc(from spare area)
137 * is 0xFF && new_ecc(computed now from data area)=0x0,
138 * this means that data area is 0xFF and spare area is
139 * 0xFF. A sure sign of a erased page!
141 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
143 printf("Error: Bad compare! failed\n");
144 /* detected 2 bit error */
152 * Generic BCH interface
154 struct nand_bch_priv {
158 struct bch_control *control;
159 enum omap_ecc ecc_scheme;
167 /* BCH nibbles for diff bch levels */
168 #define ECC_BCH4_NIBBLES 13
169 #define ECC_BCH8_NIBBLES 26
170 #define ECC_BCH16_NIBBLES 52
173 * This can be a single instance cause all current users have only one NAND
174 * with nearly the same setup (BCH8, some with ELM and others with sw BCH
176 * When some users with other BCH strength will exists this have to change!
178 static __maybe_unused struct nand_bch_priv bch_priv = {
180 .nibbles = ECC_BCH8_NIBBLES,
185 * omap_reverse_list - re-orders list elements in reverse order [internal]
186 * @list: pointer to start of list
187 * @length: length of list
189 void omap_reverse_list(u8 *list, unsigned int length)
192 unsigned int half_length = length / 2;
194 for (i = 0, j = length - 1; i < half_length; i++, j--) {
202 * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
203 * @mtd: MTD device structure
204 * @mode: Read/Write mode
207 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
209 struct nand_chip *nand = mtd->priv;
210 struct nand_bch_priv *bch = nand->priv;
211 unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
212 unsigned int ecc_algo = 0;
213 unsigned int bch_type = 0;
214 unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
215 u32 ecc_size_config_val = 0;
216 u32 ecc_config_val = 0;
218 /* configure GPMC for specific ecc-scheme */
219 switch (bch->ecc_scheme) {
220 case OMAP_ECC_HAM1_CODE_SW:
222 case OMAP_ECC_HAM1_CODE_HW:
229 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
230 case OMAP_ECC_BCH8_CODE_HW:
233 if (mode == NAND_ECC_WRITE) {
235 eccsize0 = 0; /* extra bits in nibbles per sector */
236 eccsize1 = 28; /* OOB bits in nibbles per sector */
239 eccsize0 = 26; /* ECC bits in nibbles per sector */
240 eccsize1 = 2; /* non-ECC bits in nibbles per sector */
246 /* Clear ecc and enable bits */
247 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
248 /* Configure ecc size for BCH */
249 ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
250 writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
252 /* Configure device details for BCH engine */
253 ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */
254 (bch_type << 12) | /* BCH4/BCH8/BCH16 */
255 (bch_wrapmode << 8) | /* wrap mode */
256 (dev_width << 7) | /* bus width */
257 (0x0 << 4) | /* number of sectors */
258 (cs << 1) | /* ECC CS */
259 (0x1)); /* enable ECC */
260 writel(ecc_config_val, &gpmc_cfg->ecc_config);
264 * omap_calculate_ecc - Read ECC result
265 * @mtd: MTD structure
267 * @ecc_code: ecc_code buffer
268 * Using noninverted ECC can be considered ugly since writing a blank
269 * page ie. padding will clear the ECC bytes. This is no problem as
270 * long nobody is trying to write data on the seemingly unused page.
271 * Reading an erased page will produce an ECC mismatch between
272 * generated and read ECC bytes that has to be dealt with separately.
273 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
274 * is used, the result of read will be 0x0 while the ECC offsets of the
275 * spare area will be 0xFF which will result in an ECC mismatch.
277 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
280 struct nand_chip *chip = mtd->priv;
281 struct nand_bch_priv *bch = chip->priv;
282 uint32_t *ptr, val = 0;
285 switch (bch->ecc_scheme) {
286 case OMAP_ECC_HAM1_CODE_HW:
287 val = readl(&gpmc_cfg->ecc1_result);
288 ecc_code[0] = val & 0xFF;
289 ecc_code[1] = (val >> 16) & 0xFF;
290 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
293 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
295 case OMAP_ECC_BCH8_CODE_HW:
296 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
298 ecc_code[i++] = (val >> 0) & 0xFF;
300 for (j = 0; j < 3; j++) {
302 ecc_code[i++] = (val >> 24) & 0xFF;
303 ecc_code[i++] = (val >> 16) & 0xFF;
304 ecc_code[i++] = (val >> 8) & 0xFF;
305 ecc_code[i++] = (val >> 0) & 0xFF;
312 /* ECC scheme specific syndrome customizations */
313 switch (bch->ecc_scheme) {
314 case OMAP_ECC_HAM1_CODE_HW:
317 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
319 for (i = 0; i < chip->ecc.bytes; i++)
320 *(ecc_code + i) = *(ecc_code + i) ^
324 case OMAP_ECC_BCH8_CODE_HW:
325 ecc_code[chip->ecc.bytes - 1] = 0x00;
333 #ifdef CONFIG_NAND_OMAP_ELM
335 * omap_correct_data_bch - Compares the ecc read from nand spare area
336 * with ECC registers values and corrects one bit error if it has occured
338 * @mtd: MTD device structure
340 * @read_ecc: ecc read from nand flash (ignored)
341 * @calc_ecc: ecc read from ECC registers
343 * @return 0 if data is OK or corrected, else returns -1
345 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
346 uint8_t *read_ecc, uint8_t *calc_ecc)
348 struct nand_chip *chip = mtd->priv;
349 struct nand_bch_priv *bch = chip->priv;
350 uint32_t eccbytes = chip->ecc.bytes;
351 uint32_t error_count = 0, error_max;
352 uint32_t error_loc[8];
353 uint32_t i, ecc_flag = 0;
354 uint8_t count, err = 0;
355 uint32_t byte_pos, bit_pos;
357 /* check calculated ecc */
358 for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
359 if (calc_ecc[i] != 0x00)
365 /* check for whether its a erased-page */
367 for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
368 if (read_ecc[i] != 0xff)
375 * while reading ECC result we read it in big endian.
376 * Hence while loading to ELM we have rotate to get the right endian.
378 switch (bch->ecc_scheme) {
379 case OMAP_ECC_BCH8_CODE_HW:
380 omap_reverse_list(calc_ecc, eccbytes - 1);
385 /* use elm module to check for errors */
386 elm_config((enum bch_level)(bch->type));
387 if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) {
388 printf("nand: error: uncorrectable ECC errors\n");
391 /* correct bch error */
392 for (count = 0; count < error_count; count++) {
395 /* 14th byte in ECC is reserved to match ROM layout */
396 error_max = SECTOR_BYTES + (eccbytes - 1);
401 byte_pos = error_max - (error_loc[count] / 8) - 1;
402 bit_pos = error_loc[count] % 8;
403 if (byte_pos < SECTOR_BYTES) {
404 dat[byte_pos] ^= 1 << bit_pos;
405 printf("nand: bit-flip corrected @data=%d\n", byte_pos);
406 } else if (byte_pos < error_max) {
407 read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos;
408 printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
412 printf("nand: error: invalid bit-flip location\n");
415 return (err) ? err : error_count;
419 * omap_read_page_bch - hardware ecc based page read function
420 * @mtd: mtd info structure
421 * @chip: nand chip info structure
422 * @buf: buffer to store read data
423 * @oob_required: caller expects OOB data read to chip->oob_poi
424 * @page: page number to read
427 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
428 uint8_t *buf, int oob_required, int page)
430 int i, eccsize = chip->ecc.size;
431 int eccbytes = chip->ecc.bytes;
432 int eccsteps = chip->ecc.steps;
434 uint8_t *ecc_calc = chip->buffers->ecccalc;
435 uint8_t *ecc_code = chip->buffers->ecccode;
436 uint32_t *eccpos = chip->ecc.layout->eccpos;
437 uint8_t *oob = chip->oob_poi;
443 oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
444 oob += chip->ecc.layout->eccpos[0];
446 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
448 chip->ecc.hwctl(mtd, NAND_ECC_READ);
450 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
451 chip->read_buf(mtd, p, eccsize);
453 /* read respective ecc from oob area */
454 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
455 chip->read_buf(mtd, oob, eccbytes);
457 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
463 for (i = 0; i < chip->ecc.total; i++)
464 ecc_code[i] = chip->oob_poi[eccpos[i]];
466 eccsteps = chip->ecc.steps;
469 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
472 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
474 mtd->ecc_stats.failed++;
476 mtd->ecc_stats.corrected += stat;
480 #endif /* CONFIG_NAND_OMAP_ELM */
483 * OMAP3 BCH8 support (with BCH library)
487 * omap_correct_data_bch_sw - Decode received data and correct errors
488 * @mtd: MTD device structure
490 * @read_ecc: ecc read from nand flash
491 * @calc_ecc: ecc read from HW ECC registers
493 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
494 u_char *read_ecc, u_char *calc_ecc)
497 /* cannot correct more than 8 errors */
498 unsigned int errloc[8];
499 struct nand_chip *chip = mtd->priv;
500 struct nand_bch_priv *chip_priv = chip->priv;
501 struct bch_control *bch = chip_priv->control;
503 count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
506 for (i = 0; i < count; i++) {
507 /* correct data only, not ecc bytes */
508 if (errloc[i] < 8*512)
509 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
510 printf("corrected bitflip %u\n", errloc[i]);
514 * BCH8 have 13 bytes of ECC; BCH4 needs adoption
517 for (i = 0; i < 13; i++)
518 printf("%02x ", read_ecc[i]);
521 for (i = 0; i < 13; i++)
522 printf("%02x ", calc_ecc[i]);
526 } else if (count < 0) {
527 puts("ecc unrecoverable error\n");
533 * omap_free_bch - Release BCH ecc resources
534 * @mtd: MTD device structure
536 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
538 struct nand_chip *chip = mtd->priv;
539 struct nand_bch_priv *chip_priv = chip->priv;
540 struct bch_control *bch = NULL;
543 bch = chip_priv->control;
547 chip_priv->control = NULL;
550 #endif /* CONFIG_BCH */
553 * omap_select_ecc_scheme - configures driver for particular ecc-scheme
554 * @nand: NAND chip device structure
555 * @ecc_scheme: ecc scheme to configure
556 * @pagesize: number of main-area bytes per page of NAND device
557 * @oobsize: number of OOB/spare bytes per page of NAND device
559 static int omap_select_ecc_scheme(struct nand_chip *nand,
560 enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
561 struct nand_bch_priv *bch = nand->priv;
562 struct nand_ecclayout *ecclayout = &omap_ecclayout;
563 int eccsteps = pagesize / SECTOR_BYTES;
566 switch (ecc_scheme) {
567 case OMAP_ECC_HAM1_CODE_SW:
568 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
569 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
570 * initialized in nand_scan_tail(), so just set ecc.mode */
571 bch_priv.control = NULL;
573 nand->ecc.mode = NAND_ECC_SOFT;
574 nand->ecc.layout = NULL;
576 bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW;
579 case OMAP_ECC_HAM1_CODE_HW:
580 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
581 /* check ecc-scheme requirements before updating ecc info */
582 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
583 printf("nand: error: insufficient OOB: require=%d\n", (
584 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
587 bch_priv.control = NULL;
589 /* populate ecc specific fields */
590 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
591 nand->ecc.mode = NAND_ECC_HW;
592 nand->ecc.strength = 1;
593 nand->ecc.size = SECTOR_BYTES;
595 nand->ecc.hwctl = omap_enable_hwecc;
596 nand->ecc.correct = omap_correct_data;
597 nand->ecc.calculate = omap_calculate_ecc;
598 /* define ecc-layout */
599 ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
600 for (i = 0; i < ecclayout->eccbytes; i++) {
601 if (nand->options & NAND_BUSWIDTH_16)
602 ecclayout->eccpos[i] = i + 2;
604 ecclayout->eccpos[i] = i + 1;
606 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
607 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
608 BADBLOCK_MARKER_LENGTH;
609 bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW;
612 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
614 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
615 /* check ecc-scheme requirements before updating ecc info */
616 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
617 printf("nand: error: insufficient OOB: require=%d\n", (
618 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
621 /* check if BCH S/W library can be used for error detection */
622 bch_priv.control = init_bch(13, 8, 0x201b);
623 if (!bch_priv.control) {
624 printf("nand: error: could not init_bch()\n");
627 bch_priv.type = ECC_BCH8;
628 /* populate ecc specific fields */
629 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
630 nand->ecc.mode = NAND_ECC_HW;
631 nand->ecc.strength = 8;
632 nand->ecc.size = SECTOR_BYTES;
633 nand->ecc.bytes = 13;
634 nand->ecc.hwctl = omap_enable_hwecc;
635 nand->ecc.correct = omap_correct_data_bch_sw;
636 nand->ecc.calculate = omap_calculate_ecc;
637 /* define ecc-layout */
638 ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
639 ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
640 for (i = 1; i < ecclayout->eccbytes; i++) {
641 if (i % nand->ecc.bytes)
642 ecclayout->eccpos[i] =
643 ecclayout->eccpos[i - 1] + 1;
645 ecclayout->eccpos[i] =
646 ecclayout->eccpos[i - 1] + 2;
648 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
649 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
650 BADBLOCK_MARKER_LENGTH;
651 bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
654 printf("nand: error: CONFIG_BCH required for ECC\n");
658 case OMAP_ECC_BCH8_CODE_HW:
659 #ifdef CONFIG_NAND_OMAP_ELM
660 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
661 /* check ecc-scheme requirements before updating ecc info */
662 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
663 printf("nand: error: insufficient OOB: require=%d\n", (
664 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
667 /* intialize ELM for ECC error detection */
669 bch_priv.type = ECC_BCH8;
670 /* populate ecc specific fields */
671 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
672 nand->ecc.mode = NAND_ECC_HW;
673 nand->ecc.strength = 8;
674 nand->ecc.size = SECTOR_BYTES;
675 nand->ecc.bytes = 14;
676 nand->ecc.hwctl = omap_enable_hwecc;
677 nand->ecc.correct = omap_correct_data_bch;
678 nand->ecc.calculate = omap_calculate_ecc;
679 nand->ecc.read_page = omap_read_page_bch;
680 /* define ecc-layout */
681 ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
682 for (i = 0; i < ecclayout->eccbytes; i++)
683 ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
684 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
685 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
686 BADBLOCK_MARKER_LENGTH;
687 bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW;
690 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
695 debug("nand: error: ecc scheme not enabled or supported\n");
699 /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
700 if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
701 nand->ecc.layout = ecclayout;
706 #ifndef CONFIG_SPL_BUILD
708 * omap_nand_switch_ecc - switch the ECC operation between different engines
709 * (h/w and s/w) and different algorithms (hamming and BCHx)
711 * @hardware - true if one of the HW engines should be used
712 * @eccstrength - the number of bits that could be corrected
713 * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
715 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
717 struct nand_chip *nand;
718 struct mtd_info *mtd;
721 if (nand_curr_device < 0 ||
722 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
723 !nand_info[nand_curr_device].name) {
724 printf("nand: error: no NAND devices found\n");
728 mtd = &nand_info[nand_curr_device];
730 nand->options |= NAND_OWN_BUFFERS;
731 nand->options &= ~NAND_SUBPAGE_READ;
732 /* Setup the ecc configurations again */
734 if (eccstrength == 1) {
735 err = omap_select_ecc_scheme(nand,
736 OMAP_ECC_HAM1_CODE_HW,
737 mtd->writesize, mtd->oobsize);
738 } else if (eccstrength == 8) {
739 err = omap_select_ecc_scheme(nand,
740 OMAP_ECC_BCH8_CODE_HW,
741 mtd->writesize, mtd->oobsize);
743 printf("nand: error: unsupported ECC scheme\n");
747 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
748 mtd->writesize, mtd->oobsize);
751 /* Update NAND handling after ECC mode switch */
753 err = nand_scan_tail(mtd);
756 #endif /* CONFIG_SPL_BUILD */
759 * Board-specific NAND initialization. The following members of the
760 * argument are board-specific:
761 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
762 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
763 * - cmd_ctrl: hardwarespecific function for accesing control-lines
764 * - waitfunc: hardwarespecific function for accesing device ready/busy line
765 * - ecc.hwctl: function to enable (reset) hardware ecc generator
766 * - ecc.mode: mode of ecc, see defines
767 * - chip_delay: chip dependent delay for transfering data from array to
769 * - options: various chip options. They can partly be set to inform
770 * nand_scan about special functionality. See the defines for further
773 int board_nand_init(struct nand_chip *nand)
775 int32_t gpmc_config = 0;
779 * xloader/Uboot's gpmc configuration would have configured GPMC for
780 * nand type of memory. The following logic scans and latches on to the
781 * first CS with NAND type memory.
782 * TBD: need to make this logic generic to handle multiple CS NAND
785 while (cs < GPMC_MAX_CS) {
786 /* Check if NAND type is set */
787 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
793 if (cs >= GPMC_MAX_CS) {
794 printf("nand: error: Unable to find NAND settings in "
795 "GPMC Configuration - quitting\n");
799 gpmc_config = readl(&gpmc_cfg->config);
800 /* Disable Write protect */
802 writel(gpmc_config, &gpmc_cfg->config);
804 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
805 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
806 nand->priv = &bch_priv;
807 nand->cmd_ctrl = omap_nand_hwcontrol;
808 nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
809 /* If we are 16 bit dev, our gpmc config tells us that */
810 if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
811 nand->options |= NAND_BUSWIDTH_16;
813 nand->chip_delay = 100;
814 nand->ecc.layout = &omap_ecclayout;
816 /* select ECC scheme */
817 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
818 err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
819 CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
821 /* pagesize and oobsize are not required to configure sw ecc-scheme */
822 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
828 #ifdef CONFIG_SPL_BUILD
829 if (nand->options & NAND_BUSWIDTH_16)
830 nand->read_buf = nand_read_buf16;
832 nand->read_buf = nand_read_buf;
833 nand->dev_ready = omap_spl_dev_ready;