git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/s3c2410_nand.c

   1 /*
   2  * (C) Copyright 2006 OpenMoko, Inc.
   3  * Author: Harald Welte <laforge@openmoko.org>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22
  23 #include <nand.h>
  24 #include <asm/arch/s3c24x0_cpu.h>
  25 #include <asm/io.h>
  26
  27 #define S3C2410_NFCONF_EN          (1<<15)
  28 #define S3C2410_NFCONF_512BYTE     (1<<14)
  29 #define S3C2410_NFCONF_4STEP       (1<<13)
  30 #define S3C2410_NFCONF_INITECC     (1<<12)
  31 #define S3C2410_NFCONF_nFCE        (1<<11)
  32 #define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
  33 #define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
  34 #define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
  35
  36 #define S3C2410_ADDR_NALE 4
  37 #define S3C2410_ADDR_NCLE 8
  38
  39 #ifdef CONFIG_NAND_SPL
  40
  41 /* in the early stage of NAND flash booting, printf() is not available */
  42 #define printf(fmt, args...)
  43
  44 static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  45 {
  46         int i;
  47         struct nand_chip *this = mtd->priv;
  48
  49         for (i = 0; i < len; i++)
  50                 buf[i] = readb(this->IO_ADDR_R);
  51 }
  52 #endif
  53
  54 static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  55 {
  56         struct nand_chip *chip = mtd->priv;
  57         struct s3c2410_nand *nand = s3c2410_get_base_nand();
  58
  59         debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
  60
  61         if (ctrl & NAND_CTRL_CHANGE) {
  62                 ulong IO_ADDR_W = (ulong)nand;
  63
  64                 if (!(ctrl & NAND_CLE))
  65                         IO_ADDR_W |= S3C2410_ADDR_NCLE;
  66                 if (!(ctrl & NAND_ALE))
  67                         IO_ADDR_W |= S3C2410_ADDR_NALE;
  68
  69                 chip->IO_ADDR_W = (void *)IO_ADDR_W;
  70
  71                 if (ctrl & NAND_NCE)
  72                         writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
  73                                &nand->nfconf);
  74                 else
  75                         writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
  76                                &nand->nfconf);
  77         }
  78
  79         if (cmd != NAND_CMD_NONE)
  80                 writeb(cmd, chip->IO_ADDR_W);
  81 }
  82
  83 static int s3c2410_dev_ready(struct mtd_info *mtd)
  84 {
  85         struct s3c2410_nand *nand = s3c2410_get_base_nand();
  86         debug("dev_ready\n");
  87         return readl(&nand->nfstat) & 0x01;
  88 }
  89
  90 #ifdef CONFIG_S3C2410_NAND_HWECC
  91 void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  92 {
  93         struct s3c2410_nand *nand = s3c2410_get_base_nand();
  94         debug("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
  95         writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
  96 }
  97
  98 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  99                                       u_char *ecc_code)
 100 {
 101         struct s3c2410_nand *nand = s3c2410_get_base_nand();
 102         ecc_code[0] = readb(&nand->nfecc);
 103         ecc_code[1] = readb(&nand->nfecc + 1);
 104         ecc_code[2] = readb(&nand->nfecc + 2);
 105         debug("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
 106                mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
 107
 108         return 0;
 109 }
 110
 111 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 112                                      u_char *read_ecc, u_char *calc_ecc)
 113 {
 114         if (read_ecc[0] == calc_ecc[0] &&
 115             read_ecc[1] == calc_ecc[1] &&
 116             read_ecc[2] == calc_ecc[2])
 117                 return 0;
 118
 119         printf("s3c2410_nand_correct_data: not implemented\n");
 120         return -1;
 121 }
 122 #endif
 123
 124 int board_nand_init(struct nand_chip *nand)
 125 {
 126         u_int32_t cfg;
 127         u_int8_t tacls, twrph0, twrph1;
 128         struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 129         struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();
 130
 131         debug("board_nand_init()\n");
 132
 133         writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 134
 135         /* initialize hardware */
 136 #if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
 137         tacls  = CONFIG_S3C24XX_TACLS;
 138         twrph0 = CONFIG_S3C24XX_TWRPH0;
 139         twrph1 =  CONFIG_S3C24XX_TWRPH1;
 140 #else
 141         tacls = 4;
 142         twrph0 = 8;
 143         twrph1 = 8;
 144 #endif
 145
 146         cfg = S3C2410_NFCONF_EN;
 147         cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
 148         cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 149         cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 150         writel(cfg, &nand_reg->nfconf);
 151
 152         /* initialize nand_chip data structure */
 153         nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
 154         nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
 155
 156         nand->select_chip = NULL;
 157
 158         /* read_buf and write_buf are default */
 159         /* read_byte and write_byte are default */
 160 #ifdef CONFIG_NAND_SPL
 161         nand->read_buf = nand_read_buf;
 162 #endif
 163
 164         /* hwcontrol always must be implemented */
 165         nand->cmd_ctrl = s3c2410_hwcontrol;
 166
 167         nand->dev_ready = s3c2410_dev_ready;
 168
 169 #ifdef CONFIG_S3C2410_NAND_HWECC
 170         nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
 171         nand->ecc.calculate = s3c2410_nand_calculate_ecc;
 172         nand->ecc.correct = s3c2410_nand_correct_data;
 173         nand->ecc.mode = NAND_ECC_HW;
 174         nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
 175         nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
 176 #else
 177         nand->ecc.mode = NAND_ECC_SOFT;
 178 #endif
 179
 180 #ifdef CONFIG_S3C2410_NAND_BBT
 181         nand->options = NAND_USE_FLASH_BBT;
 182 #else
 183         nand->options = 0;
 184 #endif
 185
 186         debug("end of nand_init\n");
 187
 188         return 0;
 189 }