git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/sunxi_nand_spl.c

   1 /*
   2  * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
   3  * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <common.h>
  11 #include <config.h>
  12 #include <nand.h>
  13
  14 /* registers */
  15 #define NFC_CTL                    0x00000000
  16 #define NFC_ST                     0x00000004
  17 #define NFC_INT                    0x00000008
  18 #define NFC_TIMING_CTL             0x0000000C
  19 #define NFC_TIMING_CFG             0x00000010
  20 #define NFC_ADDR_LOW               0x00000014
  21 #define NFC_ADDR_HIGH              0x00000018
  22 #define NFC_SECTOR_NUM             0x0000001C
  23 #define NFC_CNT                    0x00000020
  24 #define NFC_CMD                    0x00000024
  25 #define NFC_RCMD_SET               0x00000028
  26 #define NFC_WCMD_SET               0x0000002C
  27 #define NFC_IO_DATA                0x00000030
  28 #define NFC_ECC_CTL                0x00000034
  29 #define NFC_ECC_ST                 0x00000038
  30 #define NFC_DEBUG                  0x0000003C
  31 #define NFC_ECC_CNT0               0x00000040
  32 #define NFC_ECC_CNT1               0x00000044
  33 #define NFC_ECC_CNT2               0x00000048
  34 #define NFC_ECC_CNT3               0x0000004C
  35 #define NFC_USER_DATA_BASE         0x00000050
  36 #define NFC_EFNAND_STATUS          0x00000090
  37 #define NFC_SPARE_AREA             0x000000A0
  38 #define NFC_PATTERN_ID             0x000000A4
  39 #define NFC_RAM0_BASE              0x00000400
  40 #define NFC_RAM1_BASE              0x00000800
  41
  42 #define NFC_CTL_EN                 (1 << 0)
  43 #define NFC_CTL_RESET              (1 << 1)
  44 #define NFC_CTL_RAM_METHOD         (1 << 14)
  45 #define NFC_CTL_PAGE_SIZE_MASK     (0xf << 8)
  46 #define NFC_CTL_PAGE_SIZE(a)       ((fls(a) - 11) << 8)
  47
  48
  49 #define NFC_ECC_EN                 (1 << 0)
  50 #define NFC_ECC_PIPELINE           (1 << 3)
  51 #define NFC_ECC_EXCEPTION          (1 << 4)
  52 #define NFC_ECC_BLOCK_SIZE         (1 << 5)
  53 #define NFC_ECC_RANDOM_EN          (1 << 9)
  54 #define NFC_ECC_RANDOM_DIRECTION   (1 << 10)
  55
  56
  57 #define NFC_ADDR_NUM_OFFSET        16
  58 #define NFC_SEND_ADR               (1 << 19)
  59 #define NFC_ACCESS_DIR             (1 << 20)
  60 #define NFC_DATA_TRANS             (1 << 21)
  61 #define NFC_SEND_CMD1              (1 << 22)
  62 #define NFC_WAIT_FLAG              (1 << 23)
  63 #define NFC_SEND_CMD2              (1 << 24)
  64 #define NFC_SEQ                    (1 << 25)
  65 #define NFC_DATA_SWAP_METHOD       (1 << 26)
  66 #define NFC_ROW_AUTO_INC           (1 << 27)
  67 #define NFC_SEND_CMD3              (1 << 28)
  68 #define NFC_SEND_CMD4              (1 << 29)
  69
  70 #define NFC_ST_CMD_INT_FLAG        (1 << 1)
  71 #define NFC_ST_DMA_INT_FLAG        (1 << 2)
  72
  73 #define NFC_READ_CMD_OFFSET         0
  74 #define NFC_RANDOM_READ_CMD0_OFFSET 8
  75 #define NFC_RANDOM_READ_CMD1_OFFSET 16
  76
  77 #define NFC_CMD_RNDOUTSTART        0xE0
  78 #define NFC_CMD_RNDOUT             0x05
  79 #define NFC_CMD_READSTART          0x30
  80
  81
  82 #define NFC_PAGE_CMD               (2 << 30)
  83
  84 #define SUNXI_DMA_CFG_REG0              0x300
  85 #define SUNXI_DMA_SRC_START_ADDR_REG0   0x304
  86 #define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
  87 #define SUNXI_DMA_DDMA_BC_REG0          0x30C
  88 #define SUNXI_DMA_DDMA_PARA_REG0        0x318
  89
  90 #define SUNXI_DMA_DDMA_CFG_REG_LOADING  (1 << 31)
  91 #define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
  92 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
  93 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
  94 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
  95 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
  96
  97 #define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
  98 #define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
  99
 100 /* minimal "boot0" style NAND support for Allwinner A20 */
 101
 102 /* random seed used by linux */
 103 const uint16_t random_seed[128] = {
 104         0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
 105         0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
 106         0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
 107         0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
 108         0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
 109         0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
 110         0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
 111         0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
 112         0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
 113         0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
 114         0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
 115         0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
 116         0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
 117         0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
 118         0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
 119         0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
 120 };
 121
 122 #define DEFAULT_TIMEOUT_US      100000
 123
 124 static int check_value_inner(int offset, int expected_bits,
 125                              int timeout_us, int negation)
 126 {
 127         do {
 128                 int val = readl(offset) & expected_bits;
 129                 if (negation ? !val : val)
 130                         return 1;
 131                 udelay(1);
 132         } while (--timeout_us);
 133
 134         return 0;
 135 }
 136
 137 static inline int check_value(int offset, int expected_bits,
 138                               int timeout_us)
 139 {
 140         return check_value_inner(offset, expected_bits, timeout_us, 0);
 141 }
 142
 143 static inline int check_value_negated(int offset, int unexpected_bits,
 144                                       int timeout_us)
 145 {
 146         return check_value_inner(offset, unexpected_bits, timeout_us, 1);
 147 }
 148
 149 void nand_init(void)
 150 {
 151         uint32_t val;
 152
 153         board_nand_init();
 154
 155         val = readl(SUNXI_NFC_BASE + NFC_CTL);
 156         /* enable and reset CTL */
 157         writel(val | NFC_CTL_EN | NFC_CTL_RESET,
 158                SUNXI_NFC_BASE + NFC_CTL);
 159
 160         if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
 161                                  NFC_CTL_RESET, DEFAULT_TIMEOUT_US)) {
 162                 printf("Couldn't initialize nand\n");
 163         }
 164
 165         /* reset NAND */
 166         writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 167         writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET,
 168                SUNXI_NFC_BASE + NFC_CMD);
 169
 170         if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
 171                          DEFAULT_TIMEOUT_US)) {
 172                 printf("Error timeout waiting for nand reset\n");
 173                 return;
 174         }
 175         writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 176 }
 177
 178 static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
 179         int addr_cycles, uint32_t real_addr, dma_addr_t dst)
 180 {
 181         uint32_t val;
 182         int i, ecc_off = 0;
 183         uint16_t ecc_mode = 0;
 184         uint16_t rand_seed;
 185         uint32_t page;
 186         uint16_t column;
 187         static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
 188
 189         for (i = 0; i < ARRAY_SIZE(strengths); i++) {
 190                 if (ecc_strength == strengths[i]) {
 191                         ecc_mode = i;
 192                         break;
 193                 }
 194         }
 195
 196         /* HW ECC always request ECC bytes for 1024 bytes blocks */
 197         ecc_off = DIV_ROUND_UP(ecc_strength * fls(8 * 1024), 8);
 198         /* HW ECC always work with even numbers of ECC bytes */
 199         ecc_off += (ecc_off & 1);
 200         ecc_off += 4; /* prepad */
 201
 202         page = real_addr / page_size;
 203         column = real_addr % page_size;
 204
 205         /* clear ecc status */
 206         writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
 207
 208         /* Choose correct seed */
 209         rand_seed = random_seed[page % 128];
 210
 211         writel((rand_seed << 16) | NFC_ECC_RANDOM_EN | NFC_ECC_EN
 212                 | NFC_ECC_PIPELINE | (ecc_mode << 12),
 213                 SUNXI_NFC_BASE + NFC_ECC_CTL);
 214
 215         val = readl(SUNXI_NFC_BASE + NFC_CTL);
 216         writel(val | NFC_CTL_RAM_METHOD, SUNXI_NFC_BASE + NFC_CTL);
 217
 218         writel(page_size + (column / ecc_page_size) * ecc_off,
 219                SUNXI_NFC_BASE + NFC_SPARE_AREA);
 220
 221         flush_dcache_range(dst, ALIGN(dst + ecc_page_size, ARCH_DMA_MINALIGN));
 222
 223         /* SUNXI_DMA */
 224         writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
 225         /* read from REG_IO_DATA */
 226         writel(SUNXI_NFC_BASE + NFC_IO_DATA,
 227                SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
 228         /* read to RAM */
 229         writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
 230         writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC
 231                         | SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
 232                         SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
 233         writel(ecc_page_size,
 234                SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0); /* 1kB */
 235         writel(SUNXI_DMA_DDMA_CFG_REG_LOADING
 236                 | SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32
 237                 | SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM
 238                 | SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32
 239                 | SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO
 240                 | SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
 241                 SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
 242
 243         writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET)
 244                 | (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET)
 245                 | (NFC_CMD_READSTART | NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE
 246                         + NFC_RCMD_SET);
 247         writel(1, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
 248         writel(((page & 0xFFFF) << 16) | column,
 249                SUNXI_NFC_BASE + NFC_ADDR_LOW);
 250         writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
 251         writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 252         writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_DATA_TRANS |
 253                 NFC_PAGE_CMD | NFC_WAIT_FLAG |
 254                 ((addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) |
 255                 NFC_SEND_ADR | NFC_DATA_SWAP_METHOD,
 256                 SUNXI_NFC_BASE + NFC_CMD);
 257
 258         if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG,
 259                          DEFAULT_TIMEOUT_US)) {
 260                 printf("Error while initializing dma interrupt\n");
 261                 return -1;
 262         }
 263         writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 264
 265         if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
 266                                  SUNXI_DMA_DDMA_CFG_REG_LOADING,
 267                                  DEFAULT_TIMEOUT_US)) {
 268                 printf("Error while waiting for dma transfer to finish\n");
 269                 return -1;
 270         }
 271
 272         invalidate_dcache_range(dst,
 273                                 ALIGN(dst + ecc_page_size, ARCH_DMA_MINALIGN));
 274
 275         if (readl(SUNXI_NFC_BASE + NFC_ECC_ST))
 276                 return -1;
 277
 278         return 0;
 279 }
 280
 281 static int nand_read_ecc(int page_size, int ecc_strength, int ecc_page_size,
 282         int addr_cycles, uint32_t offs, uint32_t size, void *dest)
 283 {
 284         void *end = dest + size;
 285
 286         clrsetbits_le32(SUNXI_NFC_BASE + NFC_CTL, NFC_CTL_PAGE_SIZE_MASK,
 287                         NFC_CTL_PAGE_SIZE(page_size));
 288
 289         for ( ;dest < end; dest += ecc_page_size, offs += ecc_page_size) {
 290                 if (nand_read_page(page_size, ecc_strength, ecc_page_size,
 291                                    addr_cycles, offs, (dma_addr_t)dest))
 292                         return -1;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest)
 299 {
 300         const struct {
 301                 int page_size;
 302                 int ecc_strength;
 303                 int ecc_page_size;
 304                 int addr_cycles;
 305         } nand_configs[] = {
 306                 {  8192, 40, 1024, 5 },
 307                 { 16384, 56, 1024, 5 },
 308                 {  8192, 24, 1024, 5 },
 309                 {  4096, 24, 1024, 5 },
 310         };
 311         static int nand_config = -1;
 312         int i;
 313
 314         if (nand_config == -1) {
 315                 for (i = 0; i < ARRAY_SIZE(nand_configs); i++) {
 316                         debug("nand: trying page %d ecc %d / %d addr %d: ",
 317                               nand_configs[i].page_size,
 318                               nand_configs[i].ecc_strength,
 319                               nand_configs[i].ecc_page_size,
 320                               nand_configs[i].addr_cycles);
 321                         if (nand_read_ecc(nand_configs[i].page_size,
 322                                           nand_configs[i].ecc_strength,
 323                                           nand_configs[i].ecc_page_size,
 324                                           nand_configs[i].addr_cycles,
 325                                           offs, size, dest) == 0) {
 326                                 debug("success\n");
 327                                 nand_config = i;
 328                                 return 0;
 329                         }
 330                         debug("failed\n");
 331                 }
 332                 return -1;
 333         }
 334
 335         return nand_read_ecc(nand_configs[nand_config].page_size,
 336                              nand_configs[nand_config].ecc_strength,
 337                              nand_configs[nand_config].ecc_page_size,
 338                              nand_configs[nand_config].addr_cycles,
 339                              offs, size, dest);
 340 }
 341
 342 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
 343 {
 344         return nand_read_buffer(offs, size, dest);
 345 }
 346
 347 void nand_deselect(void)
 348 {
 349         struct sunxi_ccm_reg *const ccm =
 350                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 351
 352         clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
 353 #ifdef CONFIG_MACH_SUN9I
 354         clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
 355 #else
 356         clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
 357 #endif
 358         clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
 359 }