1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
5 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
6 * (C) Copyright 2006 DENX Software Engineering
13 #include <asm/arch/clock.h>
14 #include <asm/arch/funcmux.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <linux/errno.h>
19 #include <bouncebuf.h>
20 #include "tegra_nand.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 #define NAND_CMD_TIMEOUT_MS 10
26 #define SKIPPED_SPARE_BYTES 4
28 /* ECC bytes to be generated for tag data */
29 #define TAG_ECC_BYTES 4
31 /* 64 byte oob block info for large page (== 2KB) device
33 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
39 * Yaffs2 will use 16 tag bytes.
41 static struct nand_ecclayout eccoob = {
44 4, 5, 6, 7, 8, 9, 10, 11, 12,
45 13, 14, 15, 16, 17, 18, 19, 20, 21,
46 22, 23, 24, 25, 26, 27, 28, 29, 30,
47 31, 32, 33, 34, 35, 36, 37, 38, 39,
60 ECC_TAG_ERROR = 1 << 0,
61 ECC_DATA_ERROR = 1 << 1
64 /* Timing parameters */
66 FDT_NAND_MAX_TRP_TREA,
68 FDT_NAND_MAX_TCR_TAR_TRR,
70 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
79 /* Information about an attached NAND chip */
81 struct nand_ctlr *reg;
82 int enabled; /* 1 to enable, 0 to disable */
83 struct gpio_desc wp_gpio; /* write-protect GPIO */
84 s32 width; /* bit width, normally 8 */
85 u32 timing[FDT_NAND_TIMING_COUNT];
89 struct nand_ctlr *reg;
90 struct fdt_nand config;
93 static struct nand_drv nand_ctrl;
94 static struct mtd_info *our_mtd;
95 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
98 * Wait for command completion
100 * @param reg nand_ctlr structure
102 * 1 - Command completed
105 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
111 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
112 if ((readl(®->command) & CMD_GO) ||
113 !(readl(®->status) & STATUS_RBSY0) ||
114 !(readl(®->isr) & ISR_IS_CMD_DONE)) {
118 reg_val = readl(®->dma_mst_ctrl);
120 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
121 * is set, that means DMA engine is running.
123 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
124 * is cleared, indicating DMA transfer completion.
126 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
127 DMA_MST_CTRL_EN_B_ENABLE);
128 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
136 * Read one byte from the chip
138 * @param mtd MTD device structure
141 * Read function for 8bit bus-width
143 static uint8_t read_byte(struct mtd_info *mtd)
145 struct nand_chip *chip = mtd_to_nand(mtd);
146 struct nand_drv *info;
148 info = (struct nand_drv *)nand_get_controller_data(chip);
150 writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
151 &info->reg->command);
152 if (!nand_waitfor_cmd_completion(info->reg))
153 printf("Command timeout\n");
155 return (uint8_t)readl(&info->reg->resp);
159 * Read len bytes from the chip into a buffer
161 * @param mtd MTD device structure
162 * @param buf buffer to store data to
163 * @param len number of bytes to read
165 * Read function for 8bit bus-width
167 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
171 struct nand_chip *chip = mtd_to_nand(mtd);
172 struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
174 for (i = 0; i < len; i += 4) {
175 s = (len - i) > 4 ? 4 : len - i;
176 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
177 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
178 &info->reg->command);
179 if (!nand_waitfor_cmd_completion(info->reg))
180 puts("Command timeout during read_buf\n");
181 reg = readl(&info->reg->resp);
182 memcpy(buf + i, ®, s);
187 * Check NAND status to see if it is ready or not
189 * @param mtd MTD device structure
194 static int nand_dev_ready(struct mtd_info *mtd)
196 struct nand_chip *chip = mtd_to_nand(mtd);
198 struct nand_drv *info;
200 info = (struct nand_drv *)nand_get_controller_data(chip);
202 reg_val = readl(&info->reg->status);
203 if (reg_val & STATUS_RBSY0)
209 /* Dummy implementation: we don't support multiple chips */
210 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
223 * Clear all interrupt status bits
225 * @param reg nand_ctlr structure
227 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
231 /* Clear interrupt status */
232 reg_val = readl(®->isr);
233 writel(reg_val, ®->isr);
237 * Send command to NAND device
239 * @param mtd MTD device structure
240 * @param command the command to be sent
241 * @param column the column address for this command, -1 if none
242 * @param page_addr the page address for this command, -1 if none
244 static void nand_command(struct mtd_info *mtd, unsigned int command,
245 int column, int page_addr)
247 struct nand_chip *chip = mtd_to_nand(mtd);
248 struct nand_drv *info;
250 info = (struct nand_drv *)nand_get_controller_data(chip);
253 * Write out the command to the device.
255 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
256 * here before mtd->writesize is initialized.
259 /* Emulate NAND_CMD_READOOB */
260 if (command == NAND_CMD_READOOB) {
261 assert(mtd->writesize != 0);
262 column += mtd->writesize;
263 command = NAND_CMD_READ0;
266 /* Adjust columns for 16 bit bus-width */
267 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
270 nand_clear_interrupt_status(info->reg);
272 /* Stop DMA engine, clear DMA completion status */
273 writel(DMA_MST_CTRL_EN_A_DISABLE
274 | DMA_MST_CTRL_EN_B_DISABLE
275 | DMA_MST_CTRL_IS_DMA_DONE,
276 &info->reg->dma_mst_ctrl);
279 * Program and erase have their own busy handlers
280 * status and sequential in needs no delay
283 case NAND_CMD_READID:
284 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
285 writel(column & 0xFF, &info->reg->addr_reg1);
286 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
287 &info->reg->command);
290 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
291 writel(column & 0xFF, &info->reg->addr_reg1);
292 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
293 &info->reg->command);
296 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
297 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
298 writel((page_addr << 16) | (column & 0xFFFF),
299 &info->reg->addr_reg1);
300 writel(page_addr >> 16, &info->reg->addr_reg2);
303 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
304 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
305 writel((page_addr << 16) | (column & 0xFFFF),
306 &info->reg->addr_reg1);
307 writel(page_addr >> 16,
308 &info->reg->addr_reg2);
310 case NAND_CMD_PAGEPROG:
312 case NAND_CMD_ERASE1:
313 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
314 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
315 writel(page_addr, &info->reg->addr_reg1);
316 writel(CMD_GO | CMD_CLE | CMD_ALE |
317 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
318 &info->reg->command);
320 case NAND_CMD_ERASE2:
322 case NAND_CMD_STATUS:
323 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
324 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
325 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
327 &info->reg->command);
330 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
331 writel(CMD_GO | CMD_CLE | CMD_CE0,
332 &info->reg->command);
334 case NAND_CMD_RNDOUT:
336 printf("%s: Unsupported command %d\n", __func__, command);
339 if (!nand_waitfor_cmd_completion(info->reg))
340 printf("Command 0x%02X timeout\n", command);
344 * Check whether the pointed buffer are all 0xff (blank).
346 * @param buf data buffer for blank check
347 * @param len length of the buffer in byte
352 static int blank_check(u8 *buf, int len)
356 for (i = 0; i < len; i++)
363 * After a DMA transfer for read, we call this function to see whether there
364 * is any uncorrectable error on the pointed data buffer or oob buffer.
366 * @param reg nand_ctlr structure
367 * @param databuf data buffer
368 * @param a_len data buffer length
369 * @param oobbuf oob buffer
370 * @param b_len oob buffer length
372 * ECC_OK - no ECC error or correctable ECC error
373 * ECC_TAG_ERROR - uncorrectable tag ECC error
374 * ECC_DATA_ERROR - uncorrectable data ECC error
375 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
377 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
378 int a_len, u8 *oobbuf, int b_len)
380 int return_val = ECC_OK;
383 if (!(readl(®->isr) & ISR_IS_ECC_ERR))
387 * Area A is used for the data block (databuf). Area B is used for
388 * the spare block (oobbuf)
390 reg_val = readl(®->dec_status);
391 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
392 reg_val = readl(®->bch_dec_status_buf);
394 * If uncorrectable error occurs on data area, then see whether
395 * they are all FF. If all are FF, it's a blank page.
398 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
399 !blank_check(databuf, a_len))
400 return_val |= ECC_DATA_ERROR;
403 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
404 reg_val = readl(®->bch_dec_status_buf);
406 * If uncorrectable error occurs on tag area, then see whether
407 * they are all FF. If all are FF, it's a blank page.
410 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
411 !blank_check(oobbuf, b_len))
412 return_val |= ECC_TAG_ERROR;
419 * Set GO bit to send command to device
421 * @param reg nand_ctlr structure
423 static void start_command(struct nand_ctlr *reg)
427 reg_val = readl(®->command);
429 writel(reg_val, ®->command);
433 * Clear command GO bit, DMA GO bit, and DMA completion status
435 * @param reg nand_ctlr structure
437 static void stop_command(struct nand_ctlr *reg)
440 writel(0, ®->command);
442 /* Stop DMA engine and clear DMA completion status */
443 writel(DMA_MST_CTRL_GO_DISABLE
444 | DMA_MST_CTRL_IS_DMA_DONE,
449 * Set up NAND bus width and page size
451 * @param info nand_info structure
452 * @param *reg_val address of reg_val
453 * @return 0 if ok, -1 on error
455 static int set_bus_width_page_size(struct fdt_nand *config,
458 if (config->width == 8)
459 *reg_val = CFG_BUS_WIDTH_8BIT;
460 else if (config->width == 16)
461 *reg_val = CFG_BUS_WIDTH_16BIT;
463 debug("%s: Unsupported bus width %d\n", __func__,
468 if (our_mtd->writesize == 512)
469 *reg_val |= CFG_PAGE_SIZE_512;
470 else if (our_mtd->writesize == 2048)
471 *reg_val |= CFG_PAGE_SIZE_2048;
472 else if (our_mtd->writesize == 4096)
473 *reg_val |= CFG_PAGE_SIZE_4096;
475 debug("%s: Unsupported page size %d\n", __func__,
484 * Page read/write function
486 * @param mtd mtd info structure
487 * @param chip nand chip info structure
488 * @param buf data buffer
489 * @param page page number
490 * @param with_ecc 1 to enable ECC, 0 to disable ECC
491 * @param is_writing 0 for read, 1 for write
492 * @return 0 when successfully completed
493 * -EIO when command timeout
495 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
496 uint8_t *buf, int page, int with_ecc, int is_writing)
500 struct nand_oobfree *free = chip->ecc.layout->oobfree;
501 /* 4*128=512 (byte) is the value that our HW can support. */
502 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
504 struct nand_drv *info;
505 struct fdt_nand *config;
506 unsigned int bbflags;
507 struct bounce_buffer bbstate, bbstate_oob;
509 if ((uintptr_t)buf & 0x03) {
510 printf("buf %p has to be 4-byte aligned\n", buf);
514 info = (struct nand_drv *)nand_get_controller_data(chip);
515 config = &info->config;
516 if (set_bus_width_page_size(config, ®_val))
519 /* Need to be 4-byte aligned */
520 tag_ptr = (char *)tag_buf;
522 stop_command(info->reg);
525 bbflags = GEN_BB_READ;
527 bbflags = GEN_BB_WRITE;
529 bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
531 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
532 writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
534 /* Set ECC selection, configure ECC settings */
537 memcpy(tag_ptr, chip->oob_poi + free->offset,
538 chip->ecc.layout->oobavail + TAG_ECC_BYTES);
539 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
540 reg_val |= (CFG_SKIP_SPARE_SEL_4
541 | CFG_SKIP_SPARE_ENABLE
542 | CFG_HW_ECC_CORRECTION_ENABLE
543 | CFG_ECC_EN_TAG_DISABLE
550 tag_size += SKIPPED_SPARE_BYTES;
551 bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
554 tag_size = mtd->oobsize;
555 reg_val |= (CFG_SKIP_SPARE_DISABLE
556 | CFG_HW_ECC_CORRECTION_DISABLE
557 | CFG_ECC_EN_TAG_DISABLE
560 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
563 writel(reg_val, &info->reg->config);
564 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
565 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
566 writel(tag_size - 1, &info->reg->dma_cfg_b);
568 nand_clear_interrupt_status(info->reg);
570 reg_val = CMD_CLE | CMD_ALE
572 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
575 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
578 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
580 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
581 writel(reg_val, &info->reg->command);
583 /* Setup DMA engine */
584 reg_val = DMA_MST_CTRL_GO_ENABLE
585 | DMA_MST_CTRL_BURST_8WORDS
586 | DMA_MST_CTRL_EN_A_ENABLE
587 | DMA_MST_CTRL_EN_B_ENABLE;
590 reg_val |= DMA_MST_CTRL_DIR_READ;
592 reg_val |= DMA_MST_CTRL_DIR_WRITE;
594 writel(reg_val, &info->reg->dma_mst_ctrl);
596 start_command(info->reg);
598 if (!nand_waitfor_cmd_completion(info->reg)) {
600 printf("Read Page 0x%X timeout ", page);
602 printf("Write Page 0x%X timeout ", page);
606 printf("without ECC");
611 bounce_buffer_stop(&bbstate_oob);
612 bounce_buffer_stop(&bbstate);
614 if (with_ecc && !is_writing) {
615 memcpy(chip->oob_poi, tag_ptr,
616 SKIPPED_SPARE_BYTES);
617 memcpy(chip->oob_poi + free->offset,
618 tag_ptr + SKIPPED_SPARE_BYTES,
619 chip->ecc.layout->oobavail);
620 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
621 1 << chip->page_shift,
622 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
623 chip->ecc.layout->oobavail);
624 if (reg_val & ECC_TAG_ERROR)
625 printf("Read Page 0x%X tag ECC error\n", page);
626 if (reg_val & ECC_DATA_ERROR)
627 printf("Read Page 0x%X data ECC error\n",
629 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
636 * Hardware ecc based page read function
638 * @param mtd mtd info structure
639 * @param chip nand chip info structure
640 * @param buf buffer to store read data
641 * @param page page number to read
642 * @return 0 when successfully completed
643 * -EIO when command timeout
645 static int nand_read_page_hwecc(struct mtd_info *mtd,
646 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
648 return nand_rw_page(mtd, chip, buf, page, 1, 0);
652 * Hardware ecc based page write function
654 * @param mtd mtd info structure
655 * @param chip nand chip info structure
656 * @param buf data buffer
658 static int nand_write_page_hwecc(struct mtd_info *mtd,
659 struct nand_chip *chip, const uint8_t *buf, int oob_required,
662 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
668 * Read raw page data without ecc
670 * @param mtd mtd info structure
671 * @param chip nand chip info structure
672 * @param buf buffer to store read data
673 * @param page page number to read
674 * @return 0 when successfully completed
675 * -EINVAL when chip->oob_poi is not double-word aligned
676 * -EIO when command timeout
678 static int nand_read_page_raw(struct mtd_info *mtd,
679 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
681 return nand_rw_page(mtd, chip, buf, page, 0, 0);
685 * Raw page write function
687 * @param mtd mtd info structure
688 * @param chip nand chip info structure
689 * @param buf data buffer
691 static int nand_write_page_raw(struct mtd_info *mtd,
692 struct nand_chip *chip, const uint8_t *buf,
693 int oob_required, int page)
695 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
700 * OOB data read/write function
702 * @param mtd mtd info structure
703 * @param chip nand chip info structure
704 * @param page page number to read
705 * @param with_ecc 1 to enable ECC, 0 to disable ECC
706 * @param is_writing 0 for read, 1 for write
707 * @return 0 when successfully completed
708 * -EINVAL when chip->oob_poi is not double-word aligned
709 * -EIO when command timeout
711 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
712 int page, int with_ecc, int is_writing)
716 struct nand_oobfree *free = chip->ecc.layout->oobfree;
717 struct nand_drv *info;
718 unsigned int bbflags;
719 struct bounce_buffer bbstate_oob;
721 if (((int)chip->oob_poi) & 0x03)
723 info = (struct nand_drv *)nand_get_controller_data(chip);
724 if (set_bus_width_page_size(&info->config, ®_val))
727 stop_command(info->reg);
729 /* Set ECC selection */
730 tag_size = mtd->oobsize;
732 reg_val |= CFG_ECC_EN_TAG_ENABLE;
734 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
736 reg_val |= ((tag_size - 1) |
737 CFG_SKIP_SPARE_DISABLE |
738 CFG_HW_ECC_CORRECTION_DISABLE |
740 writel(reg_val, &info->reg->config);
742 if (is_writing && with_ecc)
743 tag_size -= TAG_ECC_BYTES;
746 bbflags = GEN_BB_READ;
748 bbflags = GEN_BB_WRITE;
750 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
752 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
754 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
756 writel(tag_size - 1, &info->reg->dma_cfg_b);
758 nand_clear_interrupt_status(info->reg);
760 reg_val = CMD_CLE | CMD_ALE
762 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
766 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
768 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
769 writel(reg_val, &info->reg->command);
771 /* Setup DMA engine */
772 reg_val = DMA_MST_CTRL_GO_ENABLE
773 | DMA_MST_CTRL_BURST_8WORDS
774 | DMA_MST_CTRL_EN_B_ENABLE;
776 reg_val |= DMA_MST_CTRL_DIR_READ;
778 reg_val |= DMA_MST_CTRL_DIR_WRITE;
780 writel(reg_val, &info->reg->dma_mst_ctrl);
782 start_command(info->reg);
784 if (!nand_waitfor_cmd_completion(info->reg)) {
786 printf("Read OOB of Page 0x%X timeout\n", page);
788 printf("Write OOB of Page 0x%X timeout\n", page);
792 bounce_buffer_stop(&bbstate_oob);
794 if (with_ecc && !is_writing) {
795 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
796 (u8 *)(chip->oob_poi + free->offset),
797 chip->ecc.layout->oobavail);
798 if (reg_val & ECC_TAG_ERROR)
799 printf("Read OOB of Page 0x%X tag ECC error\n", page);
805 * OOB data read function
807 * @param mtd mtd info structure
808 * @param chip nand chip info structure
809 * @param page page number to read
811 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
814 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
815 nand_rw_oob(mtd, chip, page, 0, 0);
820 * OOB data write function
822 * @param mtd mtd info structure
823 * @param chip nand chip info structure
824 * @param page page number to write
825 * @return 0 when successfully completed
826 * -EINVAL when chip->oob_poi is not double-word aligned
827 * -EIO when command timeout
829 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
832 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
834 return nand_rw_oob(mtd, chip, page, 0, 1);
838 * Set up NAND memory timings according to the provided parameters
840 * @param timing Timing parameters
841 * @param reg NAND controller register address
843 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
844 struct nand_ctlr *reg)
846 u32 reg_val, clk_rate, clk_period, time_val;
848 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
849 CLOCK_ID_PERIPH) / 1000000;
850 clk_period = 1000 / clk_rate;
851 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
852 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
853 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
854 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
855 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
857 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
858 TIMING_TCR_TAR_TRR_CNT_MASK;
859 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
860 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
861 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
863 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
865 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
866 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
867 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
868 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
869 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
870 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
871 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
872 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
873 writel(reg_val, ®->timing);
876 time_val = timing[FDT_NAND_TADL] / clk_period;
878 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
879 writel(reg_val, ®->timing2);
883 * Decode NAND parameters from the device tree
885 * @param blob Device tree blob
886 * @param node Node containing "nand-flash" compatible node
887 * @return 0 if ok, -ve on error (FDT_ERR_...)
889 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
893 config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
894 config->enabled = fdtdec_get_is_enabled(blob, node);
895 config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
896 err = gpio_request_by_name_nodev(offset_to_ofnode(node),
897 "nvidia,wp-gpios", 0, &config->wp_gpio, GPIOD_IS_OUT);
900 err = fdtdec_get_int_array(blob, node, "nvidia,timing",
901 config->timing, FDT_NAND_TIMING_COUNT);
905 /* Now look up the controller and decode that */
906 node = fdt_next_node(blob, node, NULL);
914 * Board-specific NAND initialization
916 * @param nand nand chip info structure
917 * @return 0, after initialized, -1 on error
919 int tegra_nand_init(struct nand_chip *nand, int devnum)
921 struct nand_drv *info = &nand_ctrl;
922 struct fdt_nand *config = &info->config;
925 node = fdtdec_next_compatible(gd->fdt_blob, 0,
926 COMPAT_NVIDIA_TEGRA20_NAND);
929 if (fdt_decode_nand(gd->fdt_blob, node, config)) {
930 printf("Could not decode nand-flash in device tree\n");
933 if (!config->enabled)
935 info->reg = config->reg;
936 nand->ecc.mode = NAND_ECC_HW;
937 nand->ecc.layout = &eccoob;
939 nand->options = LP_OPTIONS;
940 nand->cmdfunc = nand_command;
941 nand->read_byte = read_byte;
942 nand->read_buf = read_buf;
943 nand->ecc.read_page = nand_read_page_hwecc;
944 nand->ecc.write_page = nand_write_page_hwecc;
945 nand->ecc.read_page_raw = nand_read_page_raw;
946 nand->ecc.write_page_raw = nand_write_page_raw;
947 nand->ecc.read_oob = nand_read_oob;
948 nand->ecc.write_oob = nand_write_oob;
949 nand->ecc.strength = 1;
950 nand->select_chip = nand_select_chip;
951 nand->dev_ready = nand_dev_ready;
952 nand_set_controller_data(nand, &nand_ctrl);
954 /* Disable subpage writes as we do not provide ecc->hwctl */
955 nand->options |= NAND_NO_SUBPAGE_WRITE;
957 /* Adjust controller clock rate */
958 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
960 /* Adjust timing for NAND device */
961 setup_timing(config->timing, info->reg);
963 dm_gpio_set_value(&config->wp_gpio, 1);
965 our_mtd = nand_to_mtd(nand);
966 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
970 nand->ecc.size = our_mtd->writesize;
971 nand->ecc.bytes = our_mtd->oobsize;
973 ret = nand_scan_tail(our_mtd);
977 ret = nand_register(devnum, our_mtd);
984 void board_nand_init(void)
986 struct nand_chip *nand = &nand_chip[0];
988 if (tegra_nand_init(nand, 0))
989 puts("Tegra NAND init failed\n");