2 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Ported to U-Boot by Stefan Agner
6 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
7 * Jason ported to M54418TWR and MVFA5.
8 * Authors: Stefan Agner <stefan.agner@toradex.com>
9 * Bill Pringlemeir <bpringlemeir@nbsps.com>
10 * Shaohui Xie <b21989@freescale.com>
11 * Jason Jin <Jason.jin@freescale.com>
13 * Based on original driver mpc5121_nfc.c.
15 * SPDX-License-Identifier: GPL-2.0+
18 * - Untested on MPC5125 and M54418.
19 * - DMA and pipelining not used.
21 * - HW ECC: Only 2K page with 64+ OOB.
22 * - HW ECC: Only 24 and 32-bit error correction implemented.
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/partitions.h>
36 /* Register Offsets */
37 #define NFC_FLASH_CMD1 0x3F00
38 #define NFC_FLASH_CMD2 0x3F04
39 #define NFC_COL_ADDR 0x3F08
40 #define NFC_ROW_ADDR 0x3F0c
41 #define NFC_ROW_ADDR_INC 0x3F14
42 #define NFC_FLASH_STATUS1 0x3F18
43 #define NFC_FLASH_STATUS2 0x3F1c
44 #define NFC_CACHE_SWAP 0x3F28
45 #define NFC_SECTOR_SIZE 0x3F2c
46 #define NFC_FLASH_CONFIG 0x3F30
47 #define NFC_IRQ_STATUS 0x3F38
49 /* Addresses for NFC MAIN RAM BUFFER areas */
50 #define NFC_MAIN_AREA(n) ((n) * 0x1000)
52 #define PAGE_2K 0x0800
54 #define OOB_MAX 0x0100
57 * NFC_CMD2[CODE] values. See section:
58 * - 31.4.7 Flash Command Code Description, Vybrid manual
59 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
61 * Briefly these are bitmasks of controller cycles.
63 #define READ_PAGE_CMD_CODE 0x7EE0
64 #define READ_ONFI_PARAM_CMD_CODE 0x4860
65 #define PROGRAM_PAGE_CMD_CODE 0x7FC0
66 #define ERASE_CMD_CODE 0x4EC0
67 #define READ_ID_CMD_CODE 0x4804
68 #define RESET_CMD_CODE 0x4040
69 #define STATUS_READ_CMD_CODE 0x4068
71 /* NFC ECC mode define */
76 /*** Register Mask and bit definitions */
78 /* NFC_FLASH_CMD1 Field */
79 #define CMD_BYTE2_MASK 0xFF000000
80 #define CMD_BYTE2_SHIFT 24
82 /* NFC_FLASH_CM2 Field */
83 #define CMD_BYTE1_MASK 0xFF000000
84 #define CMD_BYTE1_SHIFT 24
85 #define CMD_CODE_MASK 0x00FFFF00
86 #define CMD_CODE_SHIFT 8
87 #define BUFNO_MASK 0x00000006
89 #define START_BIT (1<<0)
91 /* NFC_COL_ADDR Field */
92 #define COL_ADDR_MASK 0x0000FFFF
93 #define COL_ADDR_SHIFT 0
95 /* NFC_ROW_ADDR Field */
96 #define ROW_ADDR_MASK 0x00FFFFFF
97 #define ROW_ADDR_SHIFT 0
98 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
99 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
100 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
101 #define ROW_ADDR_CHIP_SEL_SHIFT 24
103 /* NFC_FLASH_STATUS2 Field */
104 #define STATUS_BYTE1_MASK 0x000000FF
106 /* NFC_FLASH_CONFIG Field */
107 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
108 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
109 #define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
110 #define CONFIG_DMA_REQ_BIT (1<<20)
111 #define CONFIG_ECC_MODE_MASK 0x000E0000
112 #define CONFIG_ECC_MODE_SHIFT 17
113 #define CONFIG_FAST_FLASH_BIT (1<<16)
114 #define CONFIG_16BIT (1<<7)
115 #define CONFIG_BOOT_MODE_BIT (1<<6)
116 #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
117 #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
118 #define CONFIG_PAGE_CNT_MASK 0xF
119 #define CONFIG_PAGE_CNT_SHIFT 0
121 /* NFC_IRQ_STATUS Field */
122 #define IDLE_IRQ_BIT (1<<29)
123 #define IDLE_EN_BIT (1<<20)
124 #define CMD_DONE_CLEAR_BIT (1<<18)
125 #define IDLE_CLEAR_BIT (1<<17)
127 #define NFC_TIMEOUT (1000)
130 * ECC status - seems to consume 8 bytes (double word). The documented
131 * status byte is located in the lowest byte of the second word (which is
132 * the 4th or 7th byte depending on endianness).
133 * Calculate an offset to store the ECC status at the end of the buffer.
135 #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
137 #define ECC_STATUS 0x4
138 #define ECC_STATUS_MASK 0x80
139 #define ECC_STATUS_ERR_COUNT 0x3F
141 enum vf610_nfc_alt_buf {
149 struct mtd_info *mtd;
150 struct nand_chip chip;
154 /* Status and ID are in alternate locations. */
155 enum vf610_nfc_alt_buf alt_buf;
158 #define mtd_to_nfc(_mtd) \
159 (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
161 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
162 #define ECC_HW_MODE ECC_45_BYTE
164 static struct nand_ecclayout vf610_nfc_ecc = {
166 .eccpos = {19, 20, 21, 22, 23,
167 24, 25, 26, 27, 28, 29, 30, 31,
168 32, 33, 34, 35, 36, 37, 38, 39,
169 40, 41, 42, 43, 44, 45, 46, 47,
170 48, 49, 50, 51, 52, 53, 54, 55,
171 56, 57, 58, 59, 60, 61, 62, 63},
176 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
177 #define ECC_HW_MODE ECC_60_BYTE
179 static struct nand_ecclayout vf610_nfc_ecc = {
181 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
182 12, 13, 14, 15, 16, 17, 18, 19,
183 20, 21, 22, 23, 24, 25, 26, 27,
184 28, 29, 30, 31, 32, 33, 34, 35,
185 36, 37, 38, 39, 40, 41, 42, 43,
186 44, 45, 46, 47, 48, 49, 50, 51,
187 52, 53, 54, 55, 56, 57, 58, 59,
195 static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
197 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
199 return readl(nfc->regs + reg);
202 static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
204 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
206 writel(val, nfc->regs + reg);
209 static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
211 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
214 static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
216 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
219 static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
220 u32 mask, u32 shift, u32 val)
222 vf610_nfc_write(mtd, reg,
223 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
226 static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
229 * Use this accessor for the internal SRAM buffers. On the ARM
230 * Freescale Vybrid SoC it's known that the driver can treat
231 * the SRAM buffer as if it's memory. Other platform might need
232 * to treat the buffers differently.
234 * For the time being, use memcpy
239 /* Clear flags for upcoming command */
240 static inline void vf610_nfc_clear_status(void __iomem *regbase)
242 void __iomem *reg = regbase + NFC_IRQ_STATUS;
243 u32 tmp = __raw_readl(reg);
244 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
245 __raw_writel(tmp, reg);
248 /* Wait for complete operation */
249 static void vf610_nfc_done(struct mtd_info *mtd)
251 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
255 * Barrier is needed after this write. This write need
256 * to be done before reading the next register the first
258 * vf610_nfc_set implicates such a barrier by using writel
259 * to write to the register.
261 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
263 start = get_timer(0);
265 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
266 if (get_timer(start) > NFC_TIMEOUT) {
267 printf("Timeout while waiting for IDLE.\n");
271 vf610_nfc_clear_status(nfc->regs);
274 static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
279 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
280 flash_id >>= (3 - col) * 8;
282 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
286 return flash_id & 0xff;
289 static u8 vf610_nfc_get_status(struct mtd_info *mtd)
291 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
295 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
298 void __iomem *reg = regbase + NFC_FLASH_CMD2;
300 vf610_nfc_clear_status(regbase);
302 tmp = __raw_readl(reg);
303 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
304 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
305 tmp |= cmd_code << CMD_CODE_SHIFT;
306 __raw_writel(tmp, reg);
310 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
311 u32 cmd_byte2, u32 cmd_code)
313 void __iomem *reg = regbase + NFC_FLASH_CMD1;
315 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
317 tmp = __raw_readl(reg);
318 tmp &= ~CMD_BYTE2_MASK;
319 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
320 __raw_writel(tmp, reg);
323 static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
326 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
327 if (nfc->chip.options & NAND_BUSWIDTH_16)
329 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
330 COL_ADDR_SHIFT, column);
333 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
334 ROW_ADDR_SHIFT, page);
337 static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
339 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
340 CONFIG_ECC_MODE_MASK,
341 CONFIG_ECC_MODE_SHIFT, ecc_mode);
344 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
346 __raw_writel(size, regbase + NFC_SECTOR_SIZE);
349 /* Send command to NAND chip */
350 static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
351 int column, int page)
353 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
354 int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
356 nfc->buf_offset = max(column, 0);
357 nfc->alt_buf = ALT_BUF_DATA;
361 /* Use valid column/page from preread... */
362 vf610_nfc_addr_cycle(mtd, column, page);
366 * SEQIN => data => PAGEPROG sequence is done by the controller
367 * hence we do not need to issue the command here...
370 case NAND_CMD_PAGEPROG:
371 trfr_sz += nfc->write_sz;
372 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
373 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
374 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
375 command, PROGRAM_PAGE_CMD_CODE);
379 vf610_nfc_transfer_size(nfc->regs, 0);
380 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
383 case NAND_CMD_READOOB:
384 trfr_sz += mtd->oobsize;
385 column = mtd->writesize;
386 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
387 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
388 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
389 vf610_nfc_addr_cycle(mtd, column, page);
390 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
394 trfr_sz += mtd->writesize + mtd->oobsize;
395 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
396 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
397 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
398 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
399 vf610_nfc_addr_cycle(mtd, column, page);
403 nfc->alt_buf = ALT_BUF_ONFI;
404 trfr_sz = 3 * sizeof(struct nand_onfi_params);
405 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
406 vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
407 READ_ONFI_PARAM_CMD_CODE);
408 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
409 ROW_ADDR_SHIFT, column);
410 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
413 case NAND_CMD_ERASE1:
414 vf610_nfc_transfer_size(nfc->regs, 0);
415 vf610_nfc_send_commands(nfc->regs, command,
416 NAND_CMD_ERASE2, ERASE_CMD_CODE);
417 vf610_nfc_addr_cycle(mtd, column, page);
420 case NAND_CMD_READID:
421 nfc->alt_buf = ALT_BUF_ID;
423 vf610_nfc_transfer_size(nfc->regs, 0);
424 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
425 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
426 ROW_ADDR_SHIFT, column);
429 case NAND_CMD_STATUS:
430 nfc->alt_buf = ALT_BUF_STAT;
431 vf610_nfc_transfer_size(nfc->regs, 0);
432 vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE);
443 /* Read data from NFC buffers */
444 static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
446 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
447 uint c = nfc->buf_offset;
449 /* Alternate buffers are only supported through read_byte */
453 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
455 nfc->buf_offset += len;
458 /* Write data to NFC buffers */
459 static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
462 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
463 uint c = nfc->buf_offset;
466 l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
467 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
470 nfc->buf_offset += l;
473 /* Read byte from NFC buffers */
474 static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
476 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
478 uint c = nfc->buf_offset;
480 switch (nfc->alt_buf) {
482 tmp = vf610_nfc_get_id(mtd, c);
485 tmp = vf610_nfc_get_status(mtd);
487 #ifdef __LITTLE_ENDIAN
489 /* Reverse byte since the controller uses big endianness */
490 c = nfc->buf_offset ^ 0x3;
494 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
501 /* Read word from NFC buffers */
502 static u16 vf610_nfc_read_word(struct mtd_info *mtd)
506 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
510 /* If not provided, upper layers apply a fixed delay. */
511 static int vf610_nfc_dev_ready(struct mtd_info *mtd)
513 /* NFC handles R/B internally; always ready. */
518 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
520 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
523 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
524 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
527 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
528 tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT;
531 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
535 /* Count the number of 0's in buff upto max_bits */
536 static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
538 uint32_t *buff32 = (uint32_t *)buff;
539 int k, written_bits = 0;
541 for (k = 0; k < (size / 4); k++) {
542 written_bits += hweight32(~buff32[k]);
543 if (written_bits > max_bits)
550 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
551 uint8_t *oob, int page)
553 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
554 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
558 int flips_threshold = nfc->chip.ecc.strength / 2;
560 ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff;
561 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
563 if (!(ecc_status & ECC_STATUS_MASK))
566 /* Read OOB without ECC unit enabled */
567 vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
568 vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
571 * On an erased page, bit count (including OOB) should be zero or
572 * at least less then half of the ECC strength.
574 flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
575 flips += count_written_bits(oob, mtd->oobsize, flips_threshold);
577 if (unlikely(flips > flips_threshold))
581 memset(dat, 0xff, nfc->chip.ecc.size);
582 memset(oob, 0xff, mtd->oobsize);
586 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
587 uint8_t *buf, int oob_required, int page)
589 int eccsize = chip->ecc.size;
592 vf610_nfc_read_buf(mtd, buf, eccsize);
594 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
596 stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
599 mtd->ecc_stats.failed++;
602 mtd->ecc_stats.corrected += stat;
608 * ECC will be calculated automatically
610 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
611 const uint8_t *buf, int oob_required)
613 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
615 vf610_nfc_write_buf(mtd, buf, mtd->writesize);
617 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
619 /* Always write whole page including OOB due to HW ECC */
620 nfc->write_sz = mtd->writesize + mtd->oobsize;
625 struct vf610_nfc_config {
631 static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
633 struct mtd_info *mtd = &nand_info[devnum];
634 struct nand_chip *chip;
635 struct vf610_nfc *nfc;
637 struct vf610_nfc_config cfg = {
639 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
647 nfc = malloc(sizeof(*nfc));
649 printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
660 chip->options |= NAND_BUSWIDTH_16;
662 chip->dev_ready = vf610_nfc_dev_ready;
663 chip->cmdfunc = vf610_nfc_command;
664 chip->read_byte = vf610_nfc_read_byte;
665 chip->read_word = vf610_nfc_read_word;
666 chip->read_buf = vf610_nfc_read_buf;
667 chip->write_buf = vf610_nfc_write_buf;
668 chip->select_chip = vf610_nfc_select_chip;
670 chip->options |= NAND_NO_SUBPAGE_WRITE;
672 chip->ecc.size = PAGE_2K;
674 /* Set configuration register. */
675 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
676 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
677 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
678 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
679 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
680 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
682 /* Disable virtual pages, only one elementary transfer unit */
683 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
684 CONFIG_PAGE_CNT_SHIFT, 1);
686 /* first scan to find the device and get the page size */
687 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
693 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
695 /* Bad block options. */
697 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
700 /* Single buffer only, max 256 OOB minus ECC status */
701 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
702 dev_err(nfc->dev, "Unsupported flash page size\n");
707 if (cfg.hardware_ecc) {
708 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
709 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
714 if (chip->ecc.size != mtd->writesize) {
715 dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size);
716 dev_err(nfc->dev, "Step size needs to be page size\n");
721 /* Current HW ECC layouts only use 64 bytes of OOB */
722 if (mtd->oobsize > 64)
725 /* propagate ecc.layout to mtd_info */
726 mtd->ecclayout = chip->ecc.layout;
727 chip->ecc.read_page = vf610_nfc_read_page;
728 chip->ecc.write_page = vf610_nfc_write_page;
729 chip->ecc.mode = NAND_ECC_HW;
731 chip->ecc.size = PAGE_2K;
732 chip->ecc.layout = &vf610_nfc_ecc;
733 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
734 chip->ecc.strength = 24;
735 chip->ecc.bytes = 45;
736 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
737 chip->ecc.strength = 32;
738 chip->ecc.bytes = 60;
741 /* Set ECC_STATUS offset */
742 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
743 CONFIG_ECC_SRAM_ADDR_MASK,
744 CONFIG_ECC_SRAM_ADDR_SHIFT,
747 /* Enable ECC status in SRAM */
748 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
751 /* second phase scan */
752 err = nand_scan_tail(mtd);
756 err = nand_register(devnum);
766 void board_nand_init(void)
768 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
770 printf("VF610 NAND init failed (err %d)\n", err);