2 * S5PC100 OneNAND driver at U-Boot
4 * Copyright (C) 2008-2009 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
8 * Emulate the pseudo BufferRAM
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <linux/compat.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/onenand.h>
18 #include <linux/mtd/flashchip.h>
19 #include <linux/mtd/samsung_onenand.h>
22 #include <asm/errno.h>
24 #define ONENAND_ERASE_STATUS 0x00
25 #define ONENAND_MULTI_ERASE_SET 0x01
26 #define ONENAND_ERASE_START 0x03
27 #define ONENAND_UNLOCK_START 0x08
28 #define ONENAND_UNLOCK_END 0x09
29 #define ONENAND_LOCK_START 0x0A
30 #define ONENAND_LOCK_END 0x0B
31 #define ONENAND_LOCK_TIGHT_START 0x0C
32 #define ONENAND_LOCK_TIGHT_END 0x0D
33 #define ONENAND_UNLOCK_ALL 0x0E
34 #define ONENAND_OTP_ACCESS 0x12
35 #define ONENAND_SPARE_ACCESS_ONLY 0x13
36 #define ONENAND_MAIN_ACCESS_ONLY 0x14
37 #define ONENAND_ERASE_VERIFY 0x15
38 #define ONENAND_MAIN_SPARE_ACCESS 0x16
39 #define ONENAND_PIPELINE_READ 0x4000
41 #if defined(CONFIG_S5P)
42 #define MAP_00 (0x0 << 26)
43 #define MAP_01 (0x1 << 26)
44 #define MAP_10 (0x2 << 26)
45 #define MAP_11 (0x3 << 26)
48 /* read/write of XIP buffer */
49 #define CMD_MAP_00(mem_addr) (MAP_00 | ((mem_addr) << 1))
50 /* read/write to the memory device */
51 #define CMD_MAP_01(mem_addr) (MAP_01 | (mem_addr))
52 /* control special functions of the memory device */
53 #define CMD_MAP_10(mem_addr) (MAP_10 | (mem_addr))
54 /* direct interface(direct access) with the memory device */
55 #define CMD_MAP_11(mem_addr) (MAP_11 | ((mem_addr) << 2))
60 void __iomem *ahb_addr;
62 void __iomem *page_buf;
63 void __iomem *oob_buf;
64 unsigned int (*mem_addr)(int fba, int fpa, int fsa);
65 struct samsung_onenand *reg;
68 static struct s3c_onenand *onenand;
70 static int s3c_read_cmd(unsigned int cmd)
72 return readl(onenand->ahb_addr + cmd);
75 static void s3c_write_cmd(int value, unsigned int cmd)
77 writel(value, onenand->ahb_addr + cmd);
83 * fba: flash block address
84 * fpa: flash page address
85 * fsa: flash sector address
87 * return the buffer address on the memory device
88 * It will be combined with CMD_MAP_XX
90 #if defined(CONFIG_S5P)
91 static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
93 return (fba << 13) | (fpa << 7) | (fsa << 5);
97 static void s3c_onenand_reset(void)
99 unsigned long timeout = 0x10000;
102 writel(ONENAND_MEM_RESET_COLD, &onenand->reg->mem_reset);
104 stat = readl(&onenand->reg->int_err_stat);
108 stat = readl(&onenand->reg->int_err_stat);
109 writel(stat, &onenand->reg->int_err_ack);
111 /* Clear interrupt */
112 writel(0x0, &onenand->reg->int_err_ack);
113 /* Clear the ECC status */
114 writel(0x0, &onenand->reg->ecc_err_stat);
117 static unsigned short s3c_onenand_readw(void __iomem *addr)
119 struct onenand_chip *this = onenand->mtd->priv;
120 int reg = addr - this->base;
121 int word_addr = reg >> 1;
124 /* It's used for probing time */
126 case ONENAND_REG_MANUFACTURER_ID:
127 return readl(&onenand->reg->manufact_id);
128 case ONENAND_REG_DEVICE_ID:
129 return readl(&onenand->reg->device_id);
130 case ONENAND_REG_VERSION_ID:
131 return readl(&onenand->reg->flash_ver_id);
132 case ONENAND_REG_DATA_BUFFER_SIZE:
133 return readl(&onenand->reg->data_buf_size);
134 case ONENAND_REG_TECHNOLOGY:
135 return readl(&onenand->reg->tech);
136 case ONENAND_REG_SYS_CFG1:
137 return readl(&onenand->reg->mem_cfg);
139 /* Used at unlock all status */
140 case ONENAND_REG_CTRL_STATUS:
143 case ONENAND_REG_WP_STATUS:
144 return ONENAND_WP_US;
150 /* BootRAM access control */
151 if (reg < ONENAND_DATARAM && onenand->bootram_command) {
153 return readl(&onenand->reg->manufact_id);
155 return readl(&onenand->reg->device_id);
157 return readl(&onenand->reg->flash_ver_id);
160 value = s3c_read_cmd(CMD_MAP_11(word_addr)) & 0xffff;
161 printk(KERN_INFO "s3c_onenand_readw: Illegal access"
162 " at reg 0x%x, value 0x%x\n", word_addr, value);
166 static void s3c_onenand_writew(unsigned short value, void __iomem *addr)
168 struct onenand_chip *this = onenand->mtd->priv;
169 int reg = addr - this->base;
170 int word_addr = reg >> 1;
172 /* It's used for probing time */
174 case ONENAND_REG_SYS_CFG1:
175 writel(value, &onenand->reg->mem_cfg);
178 case ONENAND_REG_START_ADDRESS1:
179 case ONENAND_REG_START_ADDRESS2:
182 /* Lock/lock-tight/unlock/unlock_all */
183 case ONENAND_REG_START_BLOCK_ADDRESS:
190 /* BootRAM access control */
191 if (reg < ONENAND_DATARAM) {
192 if (value == ONENAND_CMD_READID) {
193 onenand->bootram_command = 1;
196 if (value == ONENAND_CMD_RESET) {
197 writel(ONENAND_MEM_RESET_COLD,
198 &onenand->reg->mem_reset);
199 onenand->bootram_command = 0;
204 printk(KERN_INFO "s3c_onenand_writew: Illegal access"
205 " at reg 0x%x, value 0x%x\n", word_addr, value);
207 s3c_write_cmd(value, CMD_MAP_11(word_addr));
210 static int s3c_onenand_wait(struct mtd_info *mtd, int state)
212 unsigned int flags = INT_ACT;
213 unsigned int stat, ecc;
214 unsigned long timeout = 0x100000;
218 flags |= BLK_RW_CMP | LOAD_CMP;
221 flags |= BLK_RW_CMP | PGM_CMP;
224 flags |= BLK_RW_CMP | ERS_CMP;
234 stat = readl(&onenand->reg->int_err_stat);
239 /* To get correct interrupt status in timeout case */
240 stat = readl(&onenand->reg->int_err_stat);
241 writel(stat, &onenand->reg->int_err_ack);
244 * In the Spec. it checks the controller status first
245 * However if you get the correct information in case of
246 * power off recovery (POR) test, it should read ECC status first
248 if (stat & LOAD_CMP) {
249 ecc = readl(&onenand->reg->ecc_err_stat);
250 if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
251 printk(KERN_INFO "%s: ECC error = 0x%04x\n",
253 mtd->ecc_stats.failed++;
258 if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) {
259 printk(KERN_INFO "%s: controller error = 0x%04x\n",
261 if (stat & LOCKED_BLK)
262 printk(KERN_INFO "%s: it's locked error = 0x%04x\n",
271 static int s3c_onenand_command(struct mtd_info *mtd, int cmd,
272 loff_t addr, size_t len)
274 struct onenand_chip *this = mtd->priv;
276 int fba, fpa, fsa = 0;
277 unsigned int mem_addr;
278 int i, mcount, scount;
281 fba = (int) (addr >> this->erase_shift);
282 fpa = (int) (addr >> this->page_shift);
283 fpa &= this->page_mask;
285 mem_addr = onenand->mem_addr(fba, fpa, fsa);
288 case ONENAND_CMD_READ:
289 case ONENAND_CMD_READOOB:
290 case ONENAND_CMD_BUFFERRAM:
291 ONENAND_SET_NEXT_BUFFERRAM(this);
296 index = ONENAND_CURRENT_BUFFERRAM(this);
299 * Emulate Two BufferRAMs and access with 4 bytes pointer
301 m = (unsigned int *) onenand->page_buf;
302 s = (unsigned int *) onenand->oob_buf;
305 m += (this->writesize >> 2);
306 s += (mtd->oobsize >> 2);
309 mcount = mtd->writesize >> 2;
310 scount = mtd->oobsize >> 2;
313 case ONENAND_CMD_READ:
315 for (i = 0; i < mcount; i++)
316 *m++ = s3c_read_cmd(CMD_MAP_01(mem_addr));
319 case ONENAND_CMD_READOOB:
320 writel(TSRF, &onenand->reg->trans_spare);
322 for (i = 0; i < mcount; i++)
323 *m++ = s3c_read_cmd(CMD_MAP_01(mem_addr));
326 for (i = 0; i < scount; i++)
327 *s++ = s3c_read_cmd(CMD_MAP_01(mem_addr));
329 writel(0, &onenand->reg->trans_spare);
332 case ONENAND_CMD_PROG:
334 for (i = 0; i < mcount; i++)
335 s3c_write_cmd(*m++, CMD_MAP_01(mem_addr));
338 case ONENAND_CMD_PROGOOB:
339 writel(TSRF, &onenand->reg->trans_spare);
341 /* Main - dummy write */
342 for (i = 0; i < mcount; i++)
343 s3c_write_cmd(0xffffffff, CMD_MAP_01(mem_addr));
346 for (i = 0; i < scount; i++)
347 s3c_write_cmd(*s++, CMD_MAP_01(mem_addr));
349 writel(0, &onenand->reg->trans_spare);
352 case ONENAND_CMD_UNLOCK_ALL:
353 s3c_write_cmd(ONENAND_UNLOCK_ALL, CMD_MAP_10(mem_addr));
356 case ONENAND_CMD_ERASE:
357 s3c_write_cmd(ONENAND_ERASE_START, CMD_MAP_10(mem_addr));
360 case ONENAND_CMD_MULTIBLOCK_ERASE:
361 s3c_write_cmd(ONENAND_MULTI_ERASE_SET, CMD_MAP_10(mem_addr));
364 case ONENAND_CMD_ERASE_VERIFY:
365 s3c_write_cmd(ONENAND_ERASE_VERIFY, CMD_MAP_10(mem_addr));
375 static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area)
377 struct onenand_chip *this = mtd->priv;
378 int index = ONENAND_CURRENT_BUFFERRAM(this);
381 if (area == ONENAND_DATARAM) {
382 p = (unsigned char *) onenand->page_buf;
384 p += this->writesize;
386 p = (unsigned char *) onenand->oob_buf;
394 static int onenand_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
395 unsigned char *buffer, int offset,
400 p = s3c_get_bufferram(mtd, area);
401 memcpy(buffer, p + offset, count);
405 static int onenand_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
406 const unsigned char *buffer, int offset,
411 p = s3c_get_bufferram(mtd, area);
412 memcpy(p + offset, buffer, count);
416 static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state)
418 struct samsung_onenand *reg = (struct samsung_onenand *)onenand->base;
419 unsigned int flags = INT_ACT | LOAD_CMP;
421 unsigned long timeout = 0x10000;
424 stat = readl(®->int_err_stat);
428 /* To get correct interrupt status in timeout case */
429 stat = readl(&onenand->reg->int_err_stat);
430 writel(stat, &onenand->reg->int_err_ack);
432 if (stat & LD_FAIL_ECC_ERR) {
434 return ONENAND_BBT_READ_ERROR;
437 if (stat & LOAD_CMP) {
438 int ecc = readl(&onenand->reg->ecc_err_stat);
439 if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
441 return ONENAND_BBT_READ_ERROR;
448 static void s3c_onenand_check_lock_status(struct mtd_info *mtd)
450 struct onenand_chip *this = mtd->priv;
451 unsigned int block, end;
453 end = this->chipsize >> this->erase_shift;
455 for (block = 0; block < end; block++) {
456 s3c_read_cmd(CMD_MAP_01(onenand->mem_addr(block, 0, 0)));
458 if (readl(&onenand->reg->int_err_stat) & LOCKED_BLK) {
459 printf("block %d is write-protected!\n", block);
460 writel(LOCKED_BLK, &onenand->reg->int_err_ack);
465 static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs,
468 struct onenand_chip *this = mtd->priv;
469 int start, end, start_mem_addr, end_mem_addr;
471 start = ofs >> this->erase_shift;
472 start_mem_addr = onenand->mem_addr(start, 0, 0);
473 end = start + (len >> this->erase_shift) - 1;
474 end_mem_addr = onenand->mem_addr(end, 0, 0);
476 if (cmd == ONENAND_CMD_LOCK) {
477 s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(start_mem_addr));
478 s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(end_mem_addr));
480 s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(start_mem_addr));
481 s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(end_mem_addr));
484 this->wait(mtd, FL_LOCKING);
487 static void s3c_onenand_unlock_all(struct mtd_info *mtd)
489 struct onenand_chip *this = mtd->priv;
491 size_t len = this->chipsize;
493 /* FIXME workaround */
494 this->subpagesize = mtd->writesize;
495 mtd->subpage_sft = 0;
497 if (this->options & ONENAND_HAS_UNLOCK_ALL) {
498 /* Write unlock command */
499 this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
501 /* No need to check return value */
502 this->wait(mtd, FL_LOCKING);
504 /* Workaround for all block unlock in DDP */
505 if (!ONENAND_IS_DDP(this)) {
506 s3c_onenand_check_lock_status(mtd);
510 /* All blocks on another chip */
511 ofs = this->chipsize >> 1;
512 len = this->chipsize >> 1;
515 s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
516 s3c_onenand_check_lock_status(mtd);
519 int s5pc110_chip_probe(struct mtd_info *mtd)
524 int s5pc210_chip_probe(struct mtd_info *mtd)
529 void s3c_onenand_init(struct mtd_info *mtd)
531 struct onenand_chip *this = mtd->priv;
532 u32 size = (4 << 10); /* 4 KiB */
534 onenand = malloc(sizeof(struct s3c_onenand));
538 onenand->page_buf = malloc(size * sizeof(char));
539 if (!onenand->page_buf)
541 memset(onenand->page_buf, 0xff, size);
543 onenand->oob_buf = malloc(128 * sizeof(char));
544 if (!onenand->oob_buf)
546 memset(onenand->oob_buf, 0xff, 128);
550 #if defined(CONFIG_S5P)
551 onenand->base = (void *)0xE7100000;
552 onenand->ahb_addr = (void *)0xB0000000;
554 onenand->mem_addr = s3c_mem_addr;
555 onenand->reg = (struct samsung_onenand *)onenand->base;
557 this->read_word = s3c_onenand_readw;
558 this->write_word = s3c_onenand_writew;
560 this->wait = s3c_onenand_wait;
561 this->bbt_wait = s3c_onenand_bbt_wait;
562 this->unlock_all = s3c_onenand_unlock_all;
563 this->command = s3c_onenand_command;
565 this->read_bufferram = onenand_read_bufferram;
566 this->write_bufferram = onenand_write_bufferram;
568 this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;