2 * SPI flash internal definitions
4 * Copyright (C) 2008 Atmel Corporation
5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _SF_INTERNAL_H_
11 #define _SF_INTERNAL_H_
13 #include <linux/types.h>
14 #include <linux/compiler.h>
16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */
19 SF_DUAL_STACKED_FLASH = 1 << 0,
20 SF_DUAL_PARALLEL_FLASH = 1 << 1,
23 /* Enum list - Full read commands */
27 DUAL_OUTPUT_FAST = 1 << 2,
28 DUAL_IO_FAST = 1 << 3,
29 QUAD_OUTPUT_FAST = 1 << 4,
30 QUAD_IO_FAST = 1 << 5,
33 /* Normal - Extended - Full command set */
34 #define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
35 #define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
36 #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
47 #define SPI_FLASH_3B_ADDR_LEN 3
48 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
49 #define SPI_FLASH_16MB_BOUN 0x1000000
51 /* CFI Manufacture ID's */
52 #define SPI_FLASH_CFI_MFR_SPANSION 0x01
53 #define SPI_FLASH_CFI_MFR_STMICRO 0x20
54 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
55 #define SPI_FLASH_CFI_MFR_WINBOND 0xef
58 #define CMD_ERASE_4K 0x20
59 #define CMD_ERASE_32K 0x52
60 #define CMD_ERASE_CHIP 0xc7
61 #define CMD_ERASE_64K 0xd8
64 #define CMD_WRITE_STATUS 0x01
65 #define CMD_PAGE_PROGRAM 0x02
66 #define CMD_WRITE_DISABLE 0x04
67 #define CMD_READ_STATUS 0x05
68 #define CMD_QUAD_PAGE_PROGRAM 0x32
69 #define CMD_READ_STATUS1 0x35
70 #define CMD_WRITE_ENABLE 0x06
71 #define CMD_READ_CONFIG 0x35
72 #define CMD_FLAG_STATUS 0x70
75 #define CMD_READ_ARRAY_SLOW 0x03
76 #define CMD_READ_ARRAY_FAST 0x0b
77 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b
78 #define CMD_READ_DUAL_IO_FAST 0xbb
79 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b
80 #define CMD_READ_QUAD_IO_FAST 0xeb
81 #define CMD_READ_ID 0x9f
83 /* Bank addr access commands */
84 #ifdef CONFIG_SPI_FLASH_BAR
85 # define CMD_BANKADDR_BRWR 0x17
86 # define CMD_BANKADDR_BRRD 0x16
87 # define CMD_EXTNADDR_WREAR 0xC5
88 # define CMD_EXTNADDR_RDEAR 0xC8
92 #define STATUS_WIP (1 << 0)
93 #define STATUS_QEB_WINSPAN (1 << 1)
94 #define STATUS_QEB_MXIC (1 << 6)
95 #define STATUS_PEC (1 << 7)
97 #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
98 #define STATUS_SRWD (1 << 7) /* SR write protect */
101 /* Flash timeout values */
102 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
103 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
104 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
107 #ifdef CONFIG_SPI_FLASH_SST
108 # define CMD_SST_BP 0x02 /* Byte Program */
109 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
111 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
116 * struct spi_flash_params - SPI/QSPI flash device params structure
118 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
119 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
120 * @ext_jedec: Device ext_jedec ID
121 * @sector_size: Sector size of this device
122 * @nr_sectors: No.of sectors on this device
123 * @e_rd_cmd: Enum list for read commands
124 * @flags: Important param, for flash specific behaviour
126 struct spi_flash_params {
136 extern const struct spi_flash_params spi_flash_params_table[];
138 /* Send a single-byte command to the device and read the response */
139 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
142 * Send a multi-byte command to the device and read the response. Used
143 * for flash array reads, etc.
145 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
146 size_t cmd_len, void *data, size_t data_len);
149 * Send a multi-byte command to the device followed by (optional)
150 * data. Used for programming the flash array, etc.
152 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
153 const void *data, size_t data_len);
156 /* Flash erase(sectors) operation, support all possible erase commands */
157 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
159 /* Read the status register */
160 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
162 /* Program the status register */
163 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
165 /* Read the config register */
166 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
168 /* Program the config register */
169 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
171 /* Enable writing on the SPI flash */
172 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
174 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
177 /* Disable writing on the SPI flash */
178 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
180 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
184 * Send the read status command to the device and wait for the wip
185 * (write-in-progress) bit to clear itself.
187 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
190 * Used for spi_flash write operation
192 * - spi_flash_cmd_write_enable
193 * - spi_flash_cmd_write
194 * - spi_flash_cmd_wait_ready
197 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
198 size_t cmd_len, const void *buf, size_t buf_len);
201 * Flash write operation, support all possible write commands.
202 * Write the requested data out breaking it up into multiple write
203 * commands as needed per the write size.
205 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
206 size_t len, const void *buf);
209 * Same as spi_flash_cmd_read() except it also claims/releases the SPI
210 * bus. Used as common part of the ->read() operation.
212 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
213 size_t cmd_len, void *data, size_t data_len);
215 /* Flash read operation, support all possible read commands */
216 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
217 size_t len, void *data);
219 #endif /* _SF_INTERNAL_H_ */