1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com>
6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
7 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
8 * Copyright (C) 2008 Atmel Corporation
16 #include <spi_flash.h>
17 #include <linux/log2.h>
18 #include <linux/sizes.h>
21 #include "sf_internal.h"
23 static void spi_flash_addr(u32 addr, u8 *cmd)
25 /* cmd[0] is actual command */
31 static int read_sr(struct spi_flash *flash, u8 *rs)
36 cmd = CMD_READ_STATUS;
37 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
39 debug("SF: fail to read status register\n");
46 static int read_fsr(struct spi_flash *flash, u8 *fsr)
49 const u8 cmd = CMD_FLAG_STATUS;
51 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
53 debug("SF: fail to read flag status register\n");
60 static int write_sr(struct spi_flash *flash, u8 ws)
65 cmd = CMD_WRITE_STATUS;
66 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
68 debug("SF: fail to write status register\n");
75 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
76 static int read_cr(struct spi_flash *flash, u8 *rc)
81 cmd = CMD_READ_CONFIG;
82 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
84 debug("SF: fail to read config register\n");
91 static int write_cr(struct spi_flash *flash, u8 wc)
97 ret = read_sr(flash, &data[0]);
101 cmd = CMD_WRITE_STATUS;
103 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
105 debug("SF: fail to write config register\n");
113 #ifdef CONFIG_SPI_FLASH_BAR
115 * This "clean_bar" is necessary in a situation when one was accessing
116 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
118 * After it the BA24 bit shall be cleared to allow access to correct
119 * memory region after SW reset (by calling "reset" command).
121 * Otherwise, the BA24 bit may be left set and then after reset, the
122 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
124 static int clean_bar(struct spi_flash *flash)
126 u8 cmd, bank_sel = 0;
128 if (flash->bank_curr == 0)
130 cmd = flash->bank_write_cmd;
132 return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
135 static int write_bar(struct spi_flash *flash, u32 offset)
140 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
141 if (bank_sel == flash->bank_curr)
144 cmd = flash->bank_write_cmd;
145 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
147 debug("SF: fail to write bank register\n");
152 flash->bank_curr = bank_sel;
153 return flash->bank_curr;
156 static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
161 if (flash->size <= SPI_FLASH_16MB_BOUN)
164 switch (JEDEC_MFR(info)) {
165 case SPI_FLASH_CFI_MFR_SPANSION:
166 flash->bank_read_cmd = CMD_BANKADDR_BRRD;
167 flash->bank_write_cmd = CMD_BANKADDR_BRWR;
170 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
171 flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
174 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
177 debug("SF: fail to read bank addr register\n");
182 flash->bank_curr = curr_bank;
187 #ifdef CONFIG_SF_DUAL_FLASH
188 static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
190 switch (flash->dual_flash) {
191 case SF_DUAL_STACKED_FLASH:
192 if (*addr >= (flash->size >> 1)) {
193 *addr -= flash->size >> 1;
194 flash->flags |= SNOR_F_USE_UPAGE;
196 flash->flags &= ~SNOR_F_USE_UPAGE;
199 case SF_DUAL_PARALLEL_FLASH:
200 *addr >>= flash->shift;
203 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
209 static int spi_flash_sr_ready(struct spi_flash *flash)
214 ret = read_sr(flash, &sr);
218 return !(sr & STATUS_WIP);
221 static int spi_flash_fsr_ready(struct spi_flash *flash)
226 ret = read_fsr(flash, &fsr);
230 return fsr & STATUS_PEC;
233 static int spi_flash_ready(struct spi_flash *flash)
237 sr = spi_flash_sr_ready(flash);
242 if (flash->flags & SNOR_F_USE_FSR) {
243 fsr = spi_flash_fsr_ready(flash);
251 static int spi_flash_wait_till_ready(struct spi_flash *flash,
252 unsigned long timeout)
254 unsigned long timebase;
257 timebase = get_timer(0);
259 while (get_timer(timebase) < timeout) {
260 ret = spi_flash_ready(flash);
267 printf("SF: Timeout!\n");
272 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
273 size_t cmd_len, const void *buf, size_t buf_len)
275 struct spi_slave *spi = flash->spi;
276 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
280 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
282 ret = spi_claim_bus(spi);
284 debug("SF: unable to claim SPI bus\n");
288 ret = spi_flash_cmd_write_enable(flash);
290 debug("SF: enabling write failed\n");
294 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
296 debug("SF: write cmd failed\n");
300 ret = spi_flash_wait_till_ready(flash, timeout);
302 debug("SF: write %s timed out\n",
303 timeout == SPI_FLASH_PROG_TIMEOUT ?
304 "program" : "page erase");
308 spi_release_bus(spi);
313 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
315 u32 erase_size, erase_addr;
316 u8 cmd[SPI_FLASH_CMD_LEN];
319 erase_size = flash->erase_size;
320 if (offset % erase_size || len % erase_size) {
321 printf("SF: Erase offset/length not multiple of erase size\n");
325 if (flash->flash_is_locked) {
326 if (flash->flash_is_locked(flash, offset, len) > 0) {
327 printf("offset 0x%x is protected and cannot be erased\n",
333 cmd[0] = flash->erase_cmd;
337 #ifdef CONFIG_SF_DUAL_FLASH
338 if (flash->dual_flash > SF_SINGLE_FLASH)
339 spi_flash_dual(flash, &erase_addr);
341 #ifdef CONFIG_SPI_FLASH_BAR
342 ret = write_bar(flash, erase_addr);
346 spi_flash_addr(erase_addr, cmd);
348 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
349 cmd[2], cmd[3], erase_addr);
351 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
353 debug("SF: erase failed\n");
357 offset += erase_size;
361 #ifdef CONFIG_SPI_FLASH_BAR
362 ret = clean_bar(flash);
368 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
369 size_t len, const void *buf)
371 struct spi_slave *spi = flash->spi;
372 unsigned long byte_addr, page_size;
374 size_t chunk_len, actual;
375 u8 cmd[SPI_FLASH_CMD_LEN];
378 page_size = flash->page_size;
380 if (flash->flash_is_locked) {
381 if (flash->flash_is_locked(flash, offset, len) > 0) {
382 printf("offset 0x%x is protected and cannot be written\n",
388 cmd[0] = flash->write_cmd;
389 for (actual = 0; actual < len; actual += chunk_len) {
392 #ifdef CONFIG_SF_DUAL_FLASH
393 if (flash->dual_flash > SF_SINGLE_FLASH)
394 spi_flash_dual(flash, &write_addr);
396 #ifdef CONFIG_SPI_FLASH_BAR
397 ret = write_bar(flash, write_addr);
401 byte_addr = offset % page_size;
402 chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
404 if (spi->max_write_size)
405 chunk_len = min(chunk_len,
406 spi->max_write_size - sizeof(cmd));
408 spi_flash_addr(write_addr, cmd);
410 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
411 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
413 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
414 buf + actual, chunk_len);
416 debug("SF: write failed\n");
423 #ifdef CONFIG_SPI_FLASH_BAR
424 ret = clean_bar(flash);
430 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
431 size_t cmd_len, void *data, size_t data_len)
433 struct spi_slave *spi = flash->spi;
436 ret = spi_claim_bus(spi);
438 debug("SF: unable to claim SPI bus\n");
442 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
444 debug("SF: read cmd failed\n");
448 spi_release_bus(spi);
454 * TODO: remove the weak after all the other spi_flash_copy_mmap
455 * implementations removed from drivers
457 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
460 if (!dma_memcpy(data, offset, len))
463 memcpy(data, offset, len);
466 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
467 size_t len, void *data)
469 struct spi_slave *spi = flash->spi;
471 u32 remain_len, read_len, read_addr;
475 /* Handle memory-mapped SPI */
476 if (flash->memory_map) {
477 ret = spi_claim_bus(spi);
479 debug("SF: unable to claim SPI bus\n");
482 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
483 spi_flash_copy_mmap(data, flash->memory_map + offset, len);
484 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
485 spi_release_bus(spi);
489 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
490 cmd = calloc(1, cmdsz);
492 debug("SF: Failed to allocate cmd\n");
496 cmd[0] = flash->read_cmd;
500 #ifdef CONFIG_SF_DUAL_FLASH
501 if (flash->dual_flash > SF_SINGLE_FLASH)
502 spi_flash_dual(flash, &read_addr);
504 #ifdef CONFIG_SPI_FLASH_BAR
505 ret = write_bar(flash, read_addr);
508 bank_sel = flash->bank_curr;
510 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
511 (bank_sel + 1)) - offset;
512 if (len < remain_len)
515 read_len = remain_len;
517 if (spi->max_read_size)
518 read_len = min(read_len, spi->max_read_size);
520 spi_flash_addr(read_addr, cmd);
522 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
524 debug("SF: read failed\n");
533 #ifdef CONFIG_SPI_FLASH_BAR
534 ret = clean_bar(flash);
541 #ifdef CONFIG_SPI_FLASH_SST
542 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
546 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
548 case SST26_CTL_UNLOCK:
549 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
551 case SST26_CTL_CHECK:
552 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
559 * sst26wf016/sst26wf032/sst26wf064 have next block protection:
560 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
561 * 1x - 32 KByte blocks - write protection bits
562 * rest - 64 KByte blocks - write protection bits
563 * 1x - 32 KByte blocks - write protection bits
564 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
566 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
567 * will be treated as single block.
571 * Lock, unlock or check lock status of the flash region of the flash (depending
572 * on the lock_ctl value)
574 static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl)
576 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
577 bool lower_64k = false, upper_64k = false;
578 u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
581 /* Check length and offset for 64k alignment */
582 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
585 if (ofs + len > flash->size)
588 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
589 if (flash->size != SZ_2M &&
590 flash->size != SZ_4M &&
591 flash->size != SZ_8M)
594 bpr_size = 2 + (flash->size / SZ_64K / 8);
596 cmd = SST26_CMD_READ_BPR;
597 ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size);
599 printf("SF: fail to read block-protection register\n");
603 rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE);
604 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
606 upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE));
607 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
609 /* Lower bits in block-protection register are about 64k region */
610 bpr_ptr = lptr_64k / SZ_64K - 1;
612 /* Process 64K blocks region */
613 while (lptr_64k < rptr_64k) {
614 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
621 /* 32K and 8K region bits in BPR are after 64k region bits */
622 bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
624 /* Process lower 32K block region */
626 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
631 /* Process upper 32K block region */
633 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
638 /* Process lower 8K block regions */
639 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
641 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
644 /* In 8K area BPR has both read and write protection bits */
648 /* Process upper 8K block regions */
649 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
651 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
654 /* In 8K area BPR has both read and write protection bits */
658 /* If we check region status we don't need to write BPR back */
659 if (ctl == SST26_CTL_CHECK)
662 cmd = SST26_CMD_WRITE_BPR;
663 ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size);
665 printf("SF: fail to write block-protection register\n");
672 static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len)
674 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK);
677 static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len)
679 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK);
683 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
684 * and negative on errors.
686 static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
689 * is_locked function is used for check before reading or erasing flash
690 * region, so offset and length might be not 64k allighned, so adjust
691 * them to be 64k allighned as sst26_lock_ctl works only with 64k
694 ofs -= ofs & (SZ_64K - 1);
695 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
697 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK);
700 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
702 struct spi_slave *spi = flash->spi;
711 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
712 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
714 ret = spi_flash_cmd_write_enable(flash);
718 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
722 return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
725 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
728 struct spi_slave *spi = flash->spi;
729 size_t actual, cmd_len;
733 ret = spi_claim_bus(spi);
735 debug("SF: Unable to claim SPI bus\n");
739 /* If the data is not word aligned, write out leading single byte */
742 ret = sst_byte_write(flash, offset, buf);
748 ret = spi_flash_cmd_write_enable(flash);
753 cmd[0] = CMD_SST_AAI_WP;
754 cmd[1] = offset >> 16;
755 cmd[2] = offset >> 8;
758 for (; actual < len - 1; actual += 2) {
759 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
760 spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
763 ret = spi_flash_cmd_write(spi, cmd, cmd_len,
766 debug("SF: sst word program failed\n");
770 ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
779 ret = spi_flash_cmd_write_disable(flash);
781 /* If there is a single trailing byte, write it out */
782 if (!ret && actual != len)
783 ret = sst_byte_write(flash, offset, buf + actual);
786 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
787 ret ? "failure" : "success", len, offset - actual);
789 spi_release_bus(spi);
793 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
796 struct spi_slave *spi = flash->spi;
800 ret = spi_claim_bus(spi);
802 debug("SF: Unable to claim SPI bus\n");
806 for (actual = 0; actual < len; actual++) {
807 ret = sst_byte_write(flash, offset, buf + actual);
809 debug("SF: sst byte program failed\n");
816 ret = spi_flash_cmd_write_disable(flash);
818 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
819 ret ? "failure" : "success", len, offset - actual);
821 spi_release_bus(spi);
826 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
827 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
830 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
831 int shift = ffs(mask) - 1;
839 pow = ((sr & mask) ^ mask) >> shift;
840 *len = flash->size >> pow;
841 *ofs = flash->size - *len;
846 * Return 1 if the entire region is locked, 0 otherwise
848 static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len,
854 stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
856 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
860 * Check if a region of the flash is (completely) locked. See stm_lock() for
863 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
864 * negative on errors.
866 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
871 status = read_sr(flash, &sr);
875 return stm_is_locked_sr(flash, ofs, len, sr);
879 * Lock a region of the flash. Compatible with ST Micro and similar flash.
880 * Supports only the block protection bits BP{0,1,2} in the status register
881 * (SR). Does not support these features found in newer SR bitfields:
882 * - TB: top/bottom protect - only handle TB=0 (top protect)
883 * - SEC: sector/block protect - only handle SEC=0 (block protect)
884 * - CMP: complement protect - only support CMP=0 (range is not complemented)
886 * Sample table portion for 8MB flash (Winbond w25q64fw):
888 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
889 * --------------------------------------------------------------------------
890 * X | X | 0 | 0 | 0 | NONE | NONE
891 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
892 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
893 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
894 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
895 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
896 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
897 * X | X | 1 | 1 | 1 | 8 MB | ALL
899 * Returns negative on errors, 0 on success.
901 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
903 u8 status_old, status_new;
904 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
905 u8 shift = ffs(mask) - 1, pow, val;
908 ret = read_sr(flash, &status_old);
912 /* SPI NOR always locks to the end */
913 if (ofs + len != flash->size) {
914 /* Does combined region extend to end? */
915 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
918 len = flash->size - ofs;
922 * Need smallest pow such that:
924 * 1 / (2^pow) <= (len / size)
926 * so (assuming power-of-2 size) we do:
928 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
930 pow = ilog2(flash->size) - ilog2(len);
931 val = mask - (pow << shift);
935 /* Don't "lock" with no region! */
939 status_new = (status_old & ~mask) | val;
941 /* Only modify protection if it will not unlock other areas */
942 if ((status_new & mask) <= (status_old & mask))
945 write_sr(flash, status_new);
951 * Unlock a region of the flash. See stm_lock() for more info
953 * Returns negative on errors, 0 on success.
955 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
957 uint8_t status_old, status_new;
958 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
959 u8 shift = ffs(mask) - 1, pow, val;
962 ret = read_sr(flash, &status_old);
966 /* Cannot unlock; would unlock larger region than requested */
967 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
971 * Need largest pow such that:
973 * 1 / (2^pow) >= (len / size)
975 * so (assuming power-of-2 size) we do:
977 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
979 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
980 if (ofs + len == flash->size) {
981 val = 0; /* fully unlocked */
983 val = mask - (pow << shift);
984 /* Some power-of-two sizes are not supported */
989 status_new = (status_old & ~mask) | val;
991 /* Only modify protection if it will not lock other areas */
992 if ((status_new & mask) >= (status_old & mask))
995 write_sr(flash, status_new);
1002 #ifdef CONFIG_SPI_FLASH_MACRONIX
1003 static int macronix_quad_enable(struct spi_flash *flash)
1008 ret = read_sr(flash, &qeb_status);
1012 if (qeb_status & STATUS_QEB_MXIC)
1015 ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
1019 /* read SR and check it */
1020 ret = read_sr(flash, &qeb_status);
1021 if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
1022 printf("SF: Macronix SR Quad bit not clear\n");
1030 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1031 static int spansion_quad_enable(struct spi_flash *flash)
1036 ret = read_cr(flash, &qeb_status);
1040 if (qeb_status & STATUS_QEB_WINSPAN)
1043 ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
1047 /* read CR and check it */
1048 ret = read_cr(flash, &qeb_status);
1049 if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
1050 printf("SF: Spansion CR Quad bit not clear\n");
1058 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
1061 u8 id[SPI_FLASH_MAX_ID_LEN];
1062 const struct spi_flash_info *info;
1064 tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
1066 printf("SF: error %d reading JEDEC ID\n", tmp);
1067 return ERR_PTR(tmp);
1070 info = spi_flash_ids;
1071 for (; info->name != NULL; info++) {
1073 if (!memcmp(info->id, id, info->id_len))
1078 printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1079 id[0], id[1], id[2]);
1080 return ERR_PTR(-ENODEV);
1083 static int set_quad_mode(struct spi_flash *flash,
1084 const struct spi_flash_info *info)
1086 switch (JEDEC_MFR(info)) {
1087 #ifdef CONFIG_SPI_FLASH_MACRONIX
1088 case SPI_FLASH_CFI_MFR_MACRONIX:
1089 return macronix_quad_enable(flash);
1091 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1092 case SPI_FLASH_CFI_MFR_SPANSION:
1093 case SPI_FLASH_CFI_MFR_WINBOND:
1094 return spansion_quad_enable(flash);
1096 #ifdef CONFIG_SPI_FLASH_STMICRO
1097 case SPI_FLASH_CFI_MFR_STMICRO:
1098 debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
1102 printf("SF: Need set QEB func for %02x flash\n",
1108 #if CONFIG_IS_ENABLED(OF_CONTROL)
1109 int spi_flash_decode_fdt(struct spi_flash *flash)
1111 #ifdef CONFIG_DM_SPI_FLASH
1115 addr = dev_read_addr_size(flash->dev, "memory-map", &size);
1116 if (addr == FDT_ADDR_T_NONE) {
1117 debug("%s: Cannot decode address\n", __func__);
1121 if (flash->size > size) {
1122 debug("%s: Memory map must cover entire device\n", __func__);
1125 flash->memory_map = map_sysmem(addr, size);
1130 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
1132 int spi_flash_scan(struct spi_flash *flash)
1134 struct spi_slave *spi = flash->spi;
1135 const struct spi_flash_info *info = NULL;
1138 info = spi_flash_read_id(flash);
1139 if (IS_ERR_OR_NULL(info))
1143 * Flash powers up read-only, so clear BP# bits.
1145 * Note on some flash (like Macronix), QE (quad enable) bit is in the
1146 * same status register as BP# bits, and we need preserve its original
1147 * value during a reboot cycle as this is required by some platforms
1148 * (like Intel ICH SPI controller working under descriptor mode).
1150 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
1151 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) ||
1152 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) {
1155 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
1156 read_sr(flash, &sr);
1157 sr &= STATUS_QEB_MXIC;
1159 write_sr(flash, sr);
1162 flash->name = info->name;
1163 flash->memory_map = spi->memory_map;
1165 if (info->flags & SST_WR)
1166 flash->flags |= SNOR_F_SST_WR;
1168 #ifndef CONFIG_DM_SPI_FLASH
1169 flash->write = spi_flash_cmd_write_ops;
1170 #if defined(CONFIG_SPI_FLASH_SST)
1171 if (flash->flags & SNOR_F_SST_WR) {
1172 if (spi->mode & SPI_TX_BYTE)
1173 flash->write = sst_write_bp;
1175 flash->write = sst_write_wp;
1178 flash->erase = spi_flash_cmd_erase_ops;
1179 flash->read = spi_flash_cmd_read_ops;
1182 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
1183 /* NOR protection support for STmicro/Micron chips and similar */
1184 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO ||
1185 JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) {
1186 flash->flash_lock = stm_lock;
1187 flash->flash_unlock = stm_unlock;
1188 flash->flash_is_locked = stm_is_locked;
1192 /* sst26wf series block protection implementation differs from other series */
1193 #if defined(CONFIG_SPI_FLASH_SST)
1194 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) {
1195 flash->flash_lock = sst26_lock;
1196 flash->flash_unlock = sst26_unlock;
1197 flash->flash_is_locked = sst26_is_locked;
1201 /* Compute the flash size */
1202 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
1203 flash->page_size = info->page_size;
1205 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
1206 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
1207 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
1210 if (JEDEC_EXT(info) == 0x4d00) {
1211 if ((JEDEC_ID(info) != 0x0215) &&
1212 (JEDEC_ID(info) != 0x0216))
1213 flash->page_size = 512;
1215 flash->page_size <<= flash->shift;
1216 flash->sector_size = info->sector_size << flash->shift;
1217 flash->size = flash->sector_size * info->n_sectors << flash->shift;
1218 #ifdef CONFIG_SF_DUAL_FLASH
1219 if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
1223 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1224 /* Compute erase sector and command */
1225 if (info->flags & SECT_4K) {
1226 flash->erase_cmd = CMD_ERASE_4K;
1227 flash->erase_size = 4096 << flash->shift;
1231 flash->erase_cmd = CMD_ERASE_64K;
1232 flash->erase_size = flash->sector_size;
1235 /* Now erase size becomes valid sector size */
1236 flash->sector_size = flash->erase_size;
1238 /* Look for read commands */
1239 flash->read_cmd = CMD_READ_ARRAY_FAST;
1240 if (spi->mode & SPI_RX_SLOW)
1241 flash->read_cmd = CMD_READ_ARRAY_SLOW;
1242 else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
1243 flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
1244 else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
1245 flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
1247 /* Look for write commands */
1248 if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
1249 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
1251 /* Go for default supported write cmd */
1252 flash->write_cmd = CMD_PAGE_PROGRAM;
1254 /* Set the quad enable bit - only for quad commands */
1255 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
1256 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
1257 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
1258 ret = set_quad_mode(flash, info);
1260 debug("SF: Fail to set QEB for %02x\n",
1266 /* Read dummy_byte: dummy byte is determined based on the
1267 * dummy cycles of a particular command.
1268 * Fast commands - dummy_byte = dummy_cycles/8
1269 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
1270 * For I/O commands except cmd[0] everything goes on no.of lines
1271 * based on particular command but incase of fast commands except
1272 * data all go on single line irrespective of command.
1274 switch (flash->read_cmd) {
1275 case CMD_READ_QUAD_IO_FAST:
1276 flash->dummy_byte = 2;
1278 case CMD_READ_ARRAY_SLOW:
1279 flash->dummy_byte = 0;
1282 flash->dummy_byte = 1;
1285 #ifdef CONFIG_SPI_FLASH_STMICRO
1286 if (info->flags & E_FSR)
1287 flash->flags |= SNOR_F_USE_FSR;
1290 /* Configure the BAR - discover bank cmds and read current bank */
1291 #ifdef CONFIG_SPI_FLASH_BAR
1292 ret = read_bar(flash, info);
1297 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1298 ret = spi_flash_decode_fdt(flash);
1300 debug("SF: FDT decode error\n");
1305 #ifndef CONFIG_SPL_BUILD
1306 printf("SF: Detected %s with page size ", flash->name);
1307 print_size(flash->page_size, ", erase size ");
1308 print_size(flash->erase_size, ", total ");
1309 print_size(flash->size, "");
1310 if (flash->memory_map)
1311 printf(", mapped at %p", flash->memory_map);
1315 #ifndef CONFIG_SPI_FLASH_BAR
1316 if (((flash->dual_flash == SF_SINGLE_FLASH) &&
1317 (flash->size > SPI_FLASH_16MB_BOUN)) ||
1318 ((flash->dual_flash > SF_SINGLE_FLASH) &&
1319 (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
1320 puts("SF: Warning - Only lower 16MiB accessible,");
1321 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");