4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com>
5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
7 * Copyright (C) 2008 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <spi_flash.h>
18 #include <linux/log2.h>
20 #include "sf_internal.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 static void spi_flash_addr(u32 addr, u8 *cmd)
26 /* cmd[0] is actual command */
32 static int read_sr(struct spi_flash *flash, u8 *rs)
37 cmd = CMD_READ_STATUS;
38 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
40 debug("SF: fail to read status register\n");
47 static int read_fsr(struct spi_flash *flash, u8 *fsr)
50 const u8 cmd = CMD_FLAG_STATUS;
52 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
54 debug("SF: fail to read flag status register\n");
61 static int write_sr(struct spi_flash *flash, u8 ws)
66 cmd = CMD_WRITE_STATUS;
67 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
69 debug("SF: fail to write status register\n");
76 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
77 static int read_cr(struct spi_flash *flash, u8 *rc)
82 cmd = CMD_READ_CONFIG;
83 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
85 debug("SF: fail to read config register\n");
92 static int write_cr(struct spi_flash *flash, u8 wc)
98 ret = read_sr(flash, &data[0]);
102 cmd = CMD_WRITE_STATUS;
104 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
106 debug("SF: fail to write config register\n");
114 #ifdef CONFIG_SPI_FLASH_BAR
115 static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
120 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
121 if (bank_sel == flash->bank_curr)
124 cmd = flash->bank_write_cmd;
125 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
127 debug("SF: fail to write bank register\n");
132 flash->bank_curr = bank_sel;
133 return flash->bank_curr;
136 static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0)
141 if (flash->size <= SPI_FLASH_16MB_BOUN)
145 case SPI_FLASH_CFI_MFR_SPANSION:
146 flash->bank_read_cmd = CMD_BANKADDR_BRRD;
147 flash->bank_write_cmd = CMD_BANKADDR_BRWR;
150 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
151 flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
154 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
157 debug("SF: fail to read bank addr register\n");
162 flash->bank_curr = curr_bank;
167 #ifdef CONFIG_SF_DUAL_FLASH
168 static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
170 struct spi_slave *spi = flash->spi;
172 switch (flash->dual_flash) {
173 case SF_DUAL_STACKED_FLASH:
174 if (*addr >= (flash->size >> 1)) {
175 *addr -= flash->size >> 1;
176 spi->flags |= SPI_XFER_U_PAGE;
178 spi->flags &= ~SPI_XFER_U_PAGE;
181 case SF_DUAL_PARALLEL_FLASH:
182 *addr >>= flash->shift;
185 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
191 static int spi_flash_sr_ready(struct spi_flash *flash)
196 ret = read_sr(flash, &sr);
200 return !(sr & STATUS_WIP);
203 static int spi_flash_fsr_ready(struct spi_flash *flash)
208 ret = read_fsr(flash, &fsr);
212 return fsr & STATUS_PEC;
215 static int spi_flash_ready(struct spi_flash *flash)
219 sr = spi_flash_sr_ready(flash);
224 if (flash->flags & SNOR_F_USE_FSR) {
225 fsr = spi_flash_fsr_ready(flash);
233 static int spi_flash_cmd_wait_ready(struct spi_flash *flash,
234 unsigned long timeout)
238 timebase = get_timer(0);
240 while (get_timer(timebase) < timeout) {
241 ret = spi_flash_ready(flash);
248 printf("SF: Timeout!\n");
253 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
254 size_t cmd_len, const void *buf, size_t buf_len)
256 struct spi_slave *spi = flash->spi;
257 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
261 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
263 ret = spi_claim_bus(spi);
265 debug("SF: unable to claim SPI bus\n");
269 ret = spi_flash_cmd_write_enable(flash);
271 debug("SF: enabling write failed\n");
275 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
277 debug("SF: write cmd failed\n");
281 ret = spi_flash_cmd_wait_ready(flash, timeout);
283 debug("SF: write %s timed out\n",
284 timeout == SPI_FLASH_PROG_TIMEOUT ?
285 "program" : "page erase");
289 spi_release_bus(spi);
294 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
296 u32 erase_size, erase_addr;
297 u8 cmd[SPI_FLASH_CMD_LEN];
300 erase_size = flash->erase_size;
301 if (offset % erase_size || len % erase_size) {
302 debug("SF: Erase offset/length not multiple of erase size\n");
306 if (flash->flash_is_locked) {
307 if (flash->flash_is_locked(flash, offset, len) > 0) {
308 printf("offset 0x%x is protected and cannot be erased\n",
314 cmd[0] = flash->erase_cmd;
318 #ifdef CONFIG_SF_DUAL_FLASH
319 if (flash->dual_flash > SF_SINGLE_FLASH)
320 spi_flash_dual(flash, &erase_addr);
322 #ifdef CONFIG_SPI_FLASH_BAR
323 ret = spi_flash_write_bar(flash, erase_addr);
327 spi_flash_addr(erase_addr, cmd);
329 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
330 cmd[2], cmd[3], erase_addr);
332 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
334 debug("SF: erase failed\n");
338 offset += erase_size;
345 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
346 size_t len, const void *buf)
348 struct spi_slave *spi = flash->spi;
349 unsigned long byte_addr, page_size;
351 size_t chunk_len, actual;
352 u8 cmd[SPI_FLASH_CMD_LEN];
355 page_size = flash->page_size;
357 if (flash->flash_is_locked) {
358 if (flash->flash_is_locked(flash, offset, len) > 0) {
359 printf("offset 0x%x is protected and cannot be written\n",
365 cmd[0] = flash->write_cmd;
366 for (actual = 0; actual < len; actual += chunk_len) {
369 #ifdef CONFIG_SF_DUAL_FLASH
370 if (flash->dual_flash > SF_SINGLE_FLASH)
371 spi_flash_dual(flash, &write_addr);
373 #ifdef CONFIG_SPI_FLASH_BAR
374 ret = spi_flash_write_bar(flash, write_addr);
378 byte_addr = offset % page_size;
379 chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
381 if (spi->max_write_size)
382 chunk_len = min(chunk_len,
383 (size_t)spi->max_write_size);
385 spi_flash_addr(write_addr, cmd);
387 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
388 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
390 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
391 buf + actual, chunk_len);
393 debug("SF: write failed\n");
403 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
404 size_t cmd_len, void *data, size_t data_len)
406 struct spi_slave *spi = flash->spi;
409 ret = spi_claim_bus(spi);
411 debug("SF: unable to claim SPI bus\n");
415 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
417 debug("SF: read cmd failed\n");
421 spi_release_bus(spi);
426 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
428 memcpy(data, offset, len);
431 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
432 size_t len, void *data)
434 struct spi_slave *spi = flash->spi;
436 u32 remain_len, read_len, read_addr;
440 /* Handle memory-mapped SPI */
441 if (flash->memory_map) {
442 ret = spi_claim_bus(spi);
444 debug("SF: unable to claim SPI bus\n");
447 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
448 spi_flash_copy_mmap(data, flash->memory_map + offset, len);
449 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
450 spi_release_bus(spi);
454 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
455 cmd = calloc(1, cmdsz);
457 debug("SF: Failed to allocate cmd\n");
461 cmd[0] = flash->read_cmd;
465 #ifdef CONFIG_SF_DUAL_FLASH
466 if (flash->dual_flash > SF_SINGLE_FLASH)
467 spi_flash_dual(flash, &read_addr);
469 #ifdef CONFIG_SPI_FLASH_BAR
470 ret = spi_flash_write_bar(flash, read_addr);
473 bank_sel = flash->bank_curr;
475 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
476 (bank_sel + 1)) - offset;
477 if (len < remain_len)
480 read_len = remain_len;
482 spi_flash_addr(read_addr, cmd);
484 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
486 debug("SF: read failed\n");
499 #ifdef CONFIG_SPI_FLASH_SST
500 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
502 struct spi_slave *spi = flash->spi;
511 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
512 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
514 ret = spi_flash_cmd_write_enable(flash);
518 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
522 return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
525 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
528 struct spi_slave *spi = flash->spi;
529 size_t actual, cmd_len;
533 ret = spi_claim_bus(spi);
535 debug("SF: Unable to claim SPI bus\n");
539 /* If the data is not word aligned, write out leading single byte */
542 ret = sst_byte_write(flash, offset, buf);
548 ret = spi_flash_cmd_write_enable(flash);
553 cmd[0] = CMD_SST_AAI_WP;
554 cmd[1] = offset >> 16;
555 cmd[2] = offset >> 8;
558 for (; actual < len - 1; actual += 2) {
559 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
560 spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
563 ret = spi_flash_cmd_write(spi, cmd, cmd_len,
566 debug("SF: sst word program failed\n");
570 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
579 ret = spi_flash_cmd_write_disable(flash);
581 /* If there is a single trailing byte, write it out */
582 if (!ret && actual != len)
583 ret = sst_byte_write(flash, offset, buf + actual);
586 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
587 ret ? "failure" : "success", len, offset - actual);
589 spi_release_bus(spi);
593 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
596 struct spi_slave *spi = flash->spi;
600 ret = spi_claim_bus(spi);
602 debug("SF: Unable to claim SPI bus\n");
606 for (actual = 0; actual < len; actual++) {
607 ret = sst_byte_write(flash, offset, buf + actual);
609 debug("SF: sst byte program failed\n");
616 ret = spi_flash_cmd_write_disable(flash);
618 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
619 ret ? "failure" : "success", len, offset - actual);
621 spi_release_bus(spi);
626 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
627 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
630 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
631 int shift = ffs(mask) - 1;
639 pow = ((sr & mask) ^ mask) >> shift;
640 *len = flash->size >> pow;
641 *ofs = flash->size - *len;
646 * Return 1 if the entire region is locked, 0 otherwise
648 static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
654 stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
656 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
660 * Check if a region of the flash is (completely) locked. See stm_lock() for
663 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
664 * negative on errors.
666 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
671 status = read_sr(flash, &sr);
675 return stm_is_locked_sr(flash, ofs, len, sr);
679 * Lock a region of the flash. Compatible with ST Micro and similar flash.
680 * Supports only the block protection bits BP{0,1,2} in the status register
681 * (SR). Does not support these features found in newer SR bitfields:
682 * - TB: top/bottom protect - only handle TB=0 (top protect)
683 * - SEC: sector/block protect - only handle SEC=0 (block protect)
684 * - CMP: complement protect - only support CMP=0 (range is not complemented)
686 * Sample table portion for 8MB flash (Winbond w25q64fw):
688 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
689 * --------------------------------------------------------------------------
690 * X | X | 0 | 0 | 0 | NONE | NONE
691 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
692 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
693 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
694 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
695 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
696 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
697 * X | X | 1 | 1 | 1 | 8 MB | ALL
699 * Returns negative on errors, 0 on success.
701 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
703 u8 status_old, status_new;
704 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
705 u8 shift = ffs(mask) - 1, pow, val;
708 ret = read_sr(flash, &status_old);
712 /* SPI NOR always locks to the end */
713 if (ofs + len != flash->size) {
714 /* Does combined region extend to end? */
715 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
718 len = flash->size - ofs;
722 * Need smallest pow such that:
724 * 1 / (2^pow) <= (len / size)
726 * so (assuming power-of-2 size) we do:
728 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
730 pow = ilog2(flash->size) - ilog2(len);
731 val = mask - (pow << shift);
735 /* Don't "lock" with no region! */
739 status_new = (status_old & ~mask) | val;
741 /* Only modify protection if it will not unlock other areas */
742 if ((status_new & mask) <= (status_old & mask))
745 write_sr(flash, status_new);
751 * Unlock a region of the flash. See stm_lock() for more info
753 * Returns negative on errors, 0 on success.
755 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
757 uint8_t status_old, status_new;
758 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
759 u8 shift = ffs(mask) - 1, pow, val;
762 ret = read_sr(flash, &status_old);
766 /* Cannot unlock; would unlock larger region than requested */
767 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
771 * Need largest pow such that:
773 * 1 / (2^pow) >= (len / size)
775 * so (assuming power-of-2 size) we do:
777 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
779 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
780 if (ofs + len == flash->size) {
781 val = 0; /* fully unlocked */
783 val = mask - (pow << shift);
784 /* Some power-of-two sizes are not supported */
789 status_new = (status_old & ~mask) | val;
791 /* Only modify protection if it will not lock other areas */
792 if ((status_new & mask) >= (status_old & mask))
795 write_sr(flash, status_new);
802 #ifdef CONFIG_SPI_FLASH_MACRONIX
803 static int macronix_quad_enable(struct spi_flash *flash)
808 ret = read_sr(flash, &qeb_status);
812 if (qeb_status & STATUS_QEB_MXIC) {
813 debug("SF: mxic: QEB is already set\n");
815 ret = write_sr(flash, STATUS_QEB_MXIC);
824 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
825 static int spansion_quad_enable(struct spi_flash *flash)
830 ret = read_cr(flash, &qeb_status);
834 if (qeb_status & STATUS_QEB_WINSPAN) {
835 debug("SF: winspan: QEB is already set\n");
837 ret = write_cr(flash, STATUS_QEB_WINSPAN);
846 static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
849 #ifdef CONFIG_SPI_FLASH_MACRONIX
850 case SPI_FLASH_CFI_MFR_MACRONIX:
851 return macronix_quad_enable(flash);
853 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
854 case SPI_FLASH_CFI_MFR_SPANSION:
855 case SPI_FLASH_CFI_MFR_WINBOND:
856 return spansion_quad_enable(flash);
858 #ifdef CONFIG_SPI_FLASH_STMICRO
859 case SPI_FLASH_CFI_MFR_STMICRO:
860 debug("SF: QEB is volatile for %02x flash\n", idcode0);
864 printf("SF: Need set QEB func for %02x flash\n", idcode0);
869 #if CONFIG_IS_ENABLED(OF_CONTROL)
870 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
876 /* If there is no node, do nothing */
877 node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
881 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
882 if (addr == FDT_ADDR_T_NONE) {
883 debug("%s: Cannot decode address\n", __func__);
887 if (flash->size != size) {
888 debug("%s: Memory map must cover entire device\n", __func__);
891 flash->memory_map = map_sysmem(addr, size);
895 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
897 int spi_flash_scan(struct spi_flash *flash)
899 struct spi_slave *spi = flash->spi;
900 const struct spi_flash_params *params;
901 u16 jedec, ext_jedec;
904 static u8 spi_read_cmds_array[] = {
907 CMD_READ_DUAL_OUTPUT_FAST,
908 CMD_READ_DUAL_IO_FAST,
909 CMD_READ_QUAD_OUTPUT_FAST,
910 CMD_READ_QUAD_IO_FAST };
912 /* Read the ID codes */
913 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
915 printf("SF: Failed to get idcodes\n");
920 printf("SF: Got idcodes\n");
921 print_buffer(0, idcode, 1, sizeof(idcode), 0);
924 jedec = idcode[1] << 8 | idcode[2];
925 ext_jedec = idcode[3] << 8 | idcode[4];
927 /* Validate params from spi_flash_params table */
928 params = spi_flash_params_table;
929 for (; params->name != NULL; params++) {
930 if ((params->jedec >> 16) == idcode[0]) {
931 if ((params->jedec & 0xFFFF) == jedec) {
932 if (params->ext_jedec == 0)
934 else if (params->ext_jedec == ext_jedec)
941 printf("SF: Unsupported flash IDs: ");
942 printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
943 idcode[0], jedec, ext_jedec);
944 return -EPROTONOSUPPORT;
947 /* Flash powers up read-only, so clear BP# bits */
948 if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
949 idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
950 idcode[0] == SPI_FLASH_CFI_MFR_SST)
953 /* Assign spi data */
954 flash->name = params->name;
955 flash->memory_map = spi->memory_map;
956 flash->dual_flash = spi->option;
958 /* Assign spi flash flags */
959 if (params->flags & SST_WR)
960 flash->flags |= SNOR_F_SST_WR;
962 /* Assign spi_flash ops */
963 #ifndef CONFIG_DM_SPI_FLASH
964 flash->write = spi_flash_cmd_write_ops;
965 #if defined(CONFIG_SPI_FLASH_SST)
966 if (flash->flags & SNOR_F_SST_WR) {
967 if (spi->mode & SPI_TX_BYTE)
968 flash->write = sst_write_bp;
970 flash->write = sst_write_wp;
973 flash->erase = spi_flash_cmd_erase_ops;
974 flash->read = spi_flash_cmd_read_ops;
977 /* lock hooks are flash specific - assign them based on idcode0 */
979 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
980 case SPI_FLASH_CFI_MFR_STMICRO:
981 case SPI_FLASH_CFI_MFR_SST:
982 flash->flash_lock = stm_lock;
983 flash->flash_unlock = stm_unlock;
984 flash->flash_is_locked = stm_is_locked;
988 debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
991 /* Compute the flash size */
992 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
994 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
995 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
996 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
999 if (ext_jedec == 0x4d00) {
1000 if ((jedec == 0x0215) || (jedec == 0x216))
1001 flash->page_size = 256;
1003 flash->page_size = 512;
1005 flash->page_size = 256;
1007 flash->page_size <<= flash->shift;
1008 flash->sector_size = params->sector_size << flash->shift;
1009 flash->size = flash->sector_size * params->nr_sectors << flash->shift;
1010 #ifdef CONFIG_SF_DUAL_FLASH
1011 if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
1015 /* Compute erase sector and command */
1016 if (params->flags & SECT_4K) {
1017 flash->erase_cmd = CMD_ERASE_4K;
1018 flash->erase_size = 4096 << flash->shift;
1019 } else if (params->flags & SECT_32K) {
1020 flash->erase_cmd = CMD_ERASE_32K;
1021 flash->erase_size = 32768 << flash->shift;
1023 flash->erase_cmd = CMD_ERASE_64K;
1024 flash->erase_size = flash->sector_size;
1027 /* Now erase size becomes valid sector size */
1028 flash->sector_size = flash->erase_size;
1030 /* Look for the fastest read cmd */
1031 cmd = fls(params->e_rd_cmd & spi->op_mode_rx);
1033 cmd = spi_read_cmds_array[cmd - 1];
1034 flash->read_cmd = cmd;
1036 /* Go for default supported read cmd */
1037 flash->read_cmd = CMD_READ_ARRAY_FAST;
1040 /* Not require to look for fastest only two write cmds yet */
1041 if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
1042 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
1044 /* Go for default supported write cmd */
1045 flash->write_cmd = CMD_PAGE_PROGRAM;
1047 /* Set the quad enable bit - only for quad commands */
1048 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
1049 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
1050 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
1051 ret = set_quad_mode(flash, idcode[0]);
1053 debug("SF: Fail to set QEB for %02x\n", idcode[0]);
1058 /* Read dummy_byte: dummy byte is determined based on the
1059 * dummy cycles of a particular command.
1060 * Fast commands - dummy_byte = dummy_cycles/8
1061 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
1062 * For I/O commands except cmd[0] everything goes on no.of lines
1063 * based on particular command but incase of fast commands except
1064 * data all go on single line irrespective of command.
1066 switch (flash->read_cmd) {
1067 case CMD_READ_QUAD_IO_FAST:
1068 flash->dummy_byte = 2;
1070 case CMD_READ_ARRAY_SLOW:
1071 flash->dummy_byte = 0;
1074 flash->dummy_byte = 1;
1077 #ifdef CONFIG_SPI_FLASH_STMICRO
1078 if (params->flags & E_FSR)
1079 flash->flags |= SNOR_F_USE_FSR;
1082 /* Configure the BAR - discover bank cmds and read current bank */
1083 #ifdef CONFIG_SPI_FLASH_BAR
1084 ret = spi_flash_read_bar(flash, idcode[0]);
1089 #if CONFIG_IS_ENABLED(OF_CONTROL)
1090 ret = spi_flash_decode_fdt(gd->fdt_blob, flash);
1092 debug("SF: FDT decode error\n");
1097 #ifndef CONFIG_SPL_BUILD
1098 printf("SF: Detected %s with page size ", flash->name);
1099 print_size(flash->page_size, ", erase size ");
1100 print_size(flash->erase_size, ", total ");
1101 print_size(flash->size, "");
1102 if (flash->memory_map)
1103 printf(", mapped at %p", flash->memory_map);
1107 #ifndef CONFIG_SPI_FLASH_BAR
1108 if (((flash->dual_flash == SF_SINGLE_FLASH) &&
1109 (flash->size > SPI_FLASH_16MB_BOUN)) ||
1110 ((flash->dual_flash > SF_SINGLE_FLASH) &&
1111 (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
1112 puts("SF: Warning - Only lower 16MiB accessible,");
1113 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");