4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com>
5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
7 * Copyright (C) 2008 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <spi_flash.h>
18 #include <linux/log2.h>
21 #include "sf_internal.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 static void spi_flash_addr(u32 addr, u8 *cmd)
27 /* cmd[0] is actual command */
33 static int read_sr(struct spi_flash *flash, u8 *rs)
38 cmd = CMD_READ_STATUS;
39 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
41 debug("SF: fail to read status register\n");
48 static int read_fsr(struct spi_flash *flash, u8 *fsr)
51 const u8 cmd = CMD_FLAG_STATUS;
53 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
55 debug("SF: fail to read flag status register\n");
62 static int write_sr(struct spi_flash *flash, u8 ws)
67 cmd = CMD_WRITE_STATUS;
68 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
70 debug("SF: fail to write status register\n");
77 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
78 static int read_cr(struct spi_flash *flash, u8 *rc)
83 cmd = CMD_READ_CONFIG;
84 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
86 debug("SF: fail to read config register\n");
93 static int write_cr(struct spi_flash *flash, u8 wc)
99 ret = read_sr(flash, &data[0]);
103 cmd = CMD_WRITE_STATUS;
105 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
107 debug("SF: fail to write config register\n");
115 #ifdef CONFIG_SPI_FLASH_BAR
117 * This "clean_bar" is necessary in a situation when one was accessing
118 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
120 * After it the BA24 bit shall be cleared to allow access to correct
121 * memory region after SW reset (by calling "reset" command).
123 * Otherwise, the BA24 bit may be left set and then after reset, the
124 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
126 static int clean_bar(struct spi_flash *flash)
128 u8 cmd, bank_sel = 0;
130 if (flash->bank_curr == 0)
132 cmd = flash->bank_write_cmd;
134 return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
137 static int write_bar(struct spi_flash *flash, u32 offset)
142 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
143 if (bank_sel == flash->bank_curr)
146 cmd = flash->bank_write_cmd;
147 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
149 debug("SF: fail to write bank register\n");
154 flash->bank_curr = bank_sel;
155 return flash->bank_curr;
158 static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
163 if (flash->size <= SPI_FLASH_16MB_BOUN)
166 switch (JEDEC_MFR(info)) {
167 case SPI_FLASH_CFI_MFR_SPANSION:
168 flash->bank_read_cmd = CMD_BANKADDR_BRRD;
169 flash->bank_write_cmd = CMD_BANKADDR_BRWR;
172 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
173 flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
176 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
179 debug("SF: fail to read bank addr register\n");
184 flash->bank_curr = curr_bank;
189 #ifdef CONFIG_SF_DUAL_FLASH
190 static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
192 switch (flash->dual_flash) {
193 case SF_DUAL_STACKED_FLASH:
194 if (*addr >= (flash->size >> 1)) {
195 *addr -= flash->size >> 1;
196 flash->flags |= SNOR_F_USE_UPAGE;
198 flash->flags &= ~SNOR_F_USE_UPAGE;
201 case SF_DUAL_PARALLEL_FLASH:
202 *addr >>= flash->shift;
205 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
211 static int spi_flash_sr_ready(struct spi_flash *flash)
216 ret = read_sr(flash, &sr);
220 return !(sr & STATUS_WIP);
223 static int spi_flash_fsr_ready(struct spi_flash *flash)
228 ret = read_fsr(flash, &fsr);
232 return fsr & STATUS_PEC;
235 static int spi_flash_ready(struct spi_flash *flash)
239 sr = spi_flash_sr_ready(flash);
244 if (flash->flags & SNOR_F_USE_FSR) {
245 fsr = spi_flash_fsr_ready(flash);
253 static int spi_flash_wait_till_ready(struct spi_flash *flash,
254 unsigned long timeout)
256 unsigned long timebase;
259 timebase = get_timer(0);
261 while (get_timer(timebase) < timeout) {
262 ret = spi_flash_ready(flash);
269 printf("SF: Timeout!\n");
274 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
275 size_t cmd_len, const void *buf, size_t buf_len)
277 struct spi_slave *spi = flash->spi;
278 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
282 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
284 ret = spi_claim_bus(spi);
286 debug("SF: unable to claim SPI bus\n");
290 ret = spi_flash_cmd_write_enable(flash);
292 debug("SF: enabling write failed\n");
296 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
298 debug("SF: write cmd failed\n");
302 ret = spi_flash_wait_till_ready(flash, timeout);
304 debug("SF: write %s timed out\n",
305 timeout == SPI_FLASH_PROG_TIMEOUT ?
306 "program" : "page erase");
310 spi_release_bus(spi);
315 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
317 u32 erase_size, erase_addr;
318 u8 cmd[SPI_FLASH_CMD_LEN];
321 erase_size = flash->erase_size;
322 if (offset % erase_size || len % erase_size) {
323 debug("SF: Erase offset/length not multiple of erase size\n");
327 if (flash->flash_is_locked) {
328 if (flash->flash_is_locked(flash, offset, len) > 0) {
329 printf("offset 0x%x is protected and cannot be erased\n",
335 cmd[0] = flash->erase_cmd;
339 #ifdef CONFIG_SF_DUAL_FLASH
340 if (flash->dual_flash > SF_SINGLE_FLASH)
341 spi_flash_dual(flash, &erase_addr);
343 #ifdef CONFIG_SPI_FLASH_BAR
344 ret = write_bar(flash, erase_addr);
348 spi_flash_addr(erase_addr, cmd);
350 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
351 cmd[2], cmd[3], erase_addr);
353 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
355 debug("SF: erase failed\n");
359 offset += erase_size;
363 #ifdef CONFIG_SPI_FLASH_BAR
364 ret = clean_bar(flash);
370 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
371 size_t len, const void *buf)
373 struct spi_slave *spi = flash->spi;
374 unsigned long byte_addr, page_size;
376 size_t chunk_len, actual;
377 u8 cmd[SPI_FLASH_CMD_LEN];
380 page_size = flash->page_size;
382 if (flash->flash_is_locked) {
383 if (flash->flash_is_locked(flash, offset, len) > 0) {
384 printf("offset 0x%x is protected and cannot be written\n",
390 cmd[0] = flash->write_cmd;
391 for (actual = 0; actual < len; actual += chunk_len) {
394 #ifdef CONFIG_SF_DUAL_FLASH
395 if (flash->dual_flash > SF_SINGLE_FLASH)
396 spi_flash_dual(flash, &write_addr);
398 #ifdef CONFIG_SPI_FLASH_BAR
399 ret = write_bar(flash, write_addr);
403 byte_addr = offset % page_size;
404 chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
406 if (spi->max_write_size)
407 chunk_len = min(chunk_len,
408 spi->max_write_size - sizeof(cmd));
410 spi_flash_addr(write_addr, cmd);
412 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
413 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
415 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
416 buf + actual, chunk_len);
418 debug("SF: write failed\n");
425 #ifdef CONFIG_SPI_FLASH_BAR
426 ret = clean_bar(flash);
432 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
433 size_t cmd_len, void *data, size_t data_len)
435 struct spi_slave *spi = flash->spi;
438 ret = spi_claim_bus(spi);
440 debug("SF: unable to claim SPI bus\n");
444 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
446 debug("SF: read cmd failed\n");
450 spi_release_bus(spi);
456 * TODO: remove the weak after all the other spi_flash_copy_mmap
457 * implementations removed from drivers
459 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
462 if (!dma_memcpy(data, offset, len))
465 memcpy(data, offset, len);
468 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
469 size_t len, void *data)
471 struct spi_slave *spi = flash->spi;
473 u32 remain_len, read_len, read_addr;
477 /* Handle memory-mapped SPI */
478 if (flash->memory_map) {
479 ret = spi_claim_bus(spi);
481 debug("SF: unable to claim SPI bus\n");
484 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
485 spi_flash_copy_mmap(data, flash->memory_map + offset, len);
486 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
487 spi_release_bus(spi);
491 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
492 cmd = calloc(1, cmdsz);
494 debug("SF: Failed to allocate cmd\n");
498 cmd[0] = flash->read_cmd;
502 #ifdef CONFIG_SF_DUAL_FLASH
503 if (flash->dual_flash > SF_SINGLE_FLASH)
504 spi_flash_dual(flash, &read_addr);
506 #ifdef CONFIG_SPI_FLASH_BAR
507 ret = write_bar(flash, read_addr);
510 bank_sel = flash->bank_curr;
512 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
513 (bank_sel + 1)) - offset;
514 if (len < remain_len)
517 read_len = remain_len;
519 if (spi->max_read_size)
520 read_len = min(read_len, spi->max_read_size);
522 spi_flash_addr(read_addr, cmd);
524 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
526 debug("SF: read failed\n");
535 #ifdef CONFIG_SPI_FLASH_BAR
536 ret = clean_bar(flash);
543 #ifdef CONFIG_SPI_FLASH_SST
544 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
546 struct spi_slave *spi = flash->spi;
555 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
556 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
558 ret = spi_flash_cmd_write_enable(flash);
562 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
566 return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
569 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
572 struct spi_slave *spi = flash->spi;
573 size_t actual, cmd_len;
577 ret = spi_claim_bus(spi);
579 debug("SF: Unable to claim SPI bus\n");
583 /* If the data is not word aligned, write out leading single byte */
586 ret = sst_byte_write(flash, offset, buf);
592 ret = spi_flash_cmd_write_enable(flash);
597 cmd[0] = CMD_SST_AAI_WP;
598 cmd[1] = offset >> 16;
599 cmd[2] = offset >> 8;
602 for (; actual < len - 1; actual += 2) {
603 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
604 spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
607 ret = spi_flash_cmd_write(spi, cmd, cmd_len,
610 debug("SF: sst word program failed\n");
614 ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
623 ret = spi_flash_cmd_write_disable(flash);
625 /* If there is a single trailing byte, write it out */
626 if (!ret && actual != len)
627 ret = sst_byte_write(flash, offset, buf + actual);
630 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
631 ret ? "failure" : "success", len, offset - actual);
633 spi_release_bus(spi);
637 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
640 struct spi_slave *spi = flash->spi;
644 ret = spi_claim_bus(spi);
646 debug("SF: Unable to claim SPI bus\n");
650 for (actual = 0; actual < len; actual++) {
651 ret = sst_byte_write(flash, offset, buf + actual);
653 debug("SF: sst byte program failed\n");
660 ret = spi_flash_cmd_write_disable(flash);
662 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
663 ret ? "failure" : "success", len, offset - actual);
665 spi_release_bus(spi);
670 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
671 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
674 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
675 int shift = ffs(mask) - 1;
683 pow = ((sr & mask) ^ mask) >> shift;
684 *len = flash->size >> pow;
685 *ofs = flash->size - *len;
690 * Return 1 if the entire region is locked, 0 otherwise
692 static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len,
698 stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
700 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
704 * Check if a region of the flash is (completely) locked. See stm_lock() for
707 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
708 * negative on errors.
710 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
715 status = read_sr(flash, &sr);
719 return stm_is_locked_sr(flash, ofs, len, sr);
723 * Lock a region of the flash. Compatible with ST Micro and similar flash.
724 * Supports only the block protection bits BP{0,1,2} in the status register
725 * (SR). Does not support these features found in newer SR bitfields:
726 * - TB: top/bottom protect - only handle TB=0 (top protect)
727 * - SEC: sector/block protect - only handle SEC=0 (block protect)
728 * - CMP: complement protect - only support CMP=0 (range is not complemented)
730 * Sample table portion for 8MB flash (Winbond w25q64fw):
732 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
733 * --------------------------------------------------------------------------
734 * X | X | 0 | 0 | 0 | NONE | NONE
735 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
736 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
737 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
738 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
739 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
740 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
741 * X | X | 1 | 1 | 1 | 8 MB | ALL
743 * Returns negative on errors, 0 on success.
745 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
747 u8 status_old, status_new;
748 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
749 u8 shift = ffs(mask) - 1, pow, val;
752 ret = read_sr(flash, &status_old);
756 /* SPI NOR always locks to the end */
757 if (ofs + len != flash->size) {
758 /* Does combined region extend to end? */
759 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
762 len = flash->size - ofs;
766 * Need smallest pow such that:
768 * 1 / (2^pow) <= (len / size)
770 * so (assuming power-of-2 size) we do:
772 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
774 pow = ilog2(flash->size) - ilog2(len);
775 val = mask - (pow << shift);
779 /* Don't "lock" with no region! */
783 status_new = (status_old & ~mask) | val;
785 /* Only modify protection if it will not unlock other areas */
786 if ((status_new & mask) <= (status_old & mask))
789 write_sr(flash, status_new);
795 * Unlock a region of the flash. See stm_lock() for more info
797 * Returns negative on errors, 0 on success.
799 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
801 uint8_t status_old, status_new;
802 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
803 u8 shift = ffs(mask) - 1, pow, val;
806 ret = read_sr(flash, &status_old);
810 /* Cannot unlock; would unlock larger region than requested */
811 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
815 * Need largest pow such that:
817 * 1 / (2^pow) >= (len / size)
819 * so (assuming power-of-2 size) we do:
821 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
823 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
824 if (ofs + len == flash->size) {
825 val = 0; /* fully unlocked */
827 val = mask - (pow << shift);
828 /* Some power-of-two sizes are not supported */
833 status_new = (status_old & ~mask) | val;
835 /* Only modify protection if it will not lock other areas */
836 if ((status_new & mask) >= (status_old & mask))
839 write_sr(flash, status_new);
846 #ifdef CONFIG_SPI_FLASH_MACRONIX
847 static int macronix_quad_enable(struct spi_flash *flash)
852 ret = read_sr(flash, &qeb_status);
856 if (qeb_status & STATUS_QEB_MXIC)
859 ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
863 /* read SR and check it */
864 ret = read_sr(flash, &qeb_status);
865 if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
866 printf("SF: Macronix SR Quad bit not clear\n");
874 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
875 static int spansion_quad_enable(struct spi_flash *flash)
880 ret = read_cr(flash, &qeb_status);
884 if (qeb_status & STATUS_QEB_WINSPAN)
887 ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
891 /* read CR and check it */
892 ret = read_cr(flash, &qeb_status);
893 if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
894 printf("SF: Spansion CR Quad bit not clear\n");
902 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
905 u8 id[SPI_FLASH_MAX_ID_LEN];
906 const struct spi_flash_info *info;
908 tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
910 printf("SF: error %d reading JEDEC ID\n", tmp);
914 info = spi_flash_ids;
915 for (; info->name != NULL; info++) {
917 if (!memcmp(info->id, id, info->id_len))
922 printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
923 id[0], id[1], id[2]);
924 return ERR_PTR(-ENODEV);
927 static int set_quad_mode(struct spi_flash *flash,
928 const struct spi_flash_info *info)
930 switch (JEDEC_MFR(info)) {
931 #ifdef CONFIG_SPI_FLASH_MACRONIX
932 case SPI_FLASH_CFI_MFR_MACRONIX:
933 return macronix_quad_enable(flash);
935 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
936 case SPI_FLASH_CFI_MFR_SPANSION:
937 case SPI_FLASH_CFI_MFR_WINBOND:
938 return spansion_quad_enable(flash);
940 #ifdef CONFIG_SPI_FLASH_STMICRO
941 case SPI_FLASH_CFI_MFR_STMICRO:
942 debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
946 printf("SF: Need set QEB func for %02x flash\n",
952 #if CONFIG_IS_ENABLED(OF_CONTROL)
953 int spi_flash_decode_fdt(struct spi_flash *flash)
955 #ifdef CONFIG_DM_SPI_FLASH
959 addr = dev_read_addr_size(flash->dev, "memory-map", &size);
960 if (addr == FDT_ADDR_T_NONE) {
961 debug("%s: Cannot decode address\n", __func__);
965 if (flash->size > size) {
966 debug("%s: Memory map must cover entire device\n", __func__);
969 flash->memory_map = map_sysmem(addr, size);
974 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
976 int spi_flash_scan(struct spi_flash *flash)
978 struct spi_slave *spi = flash->spi;
979 const struct spi_flash_info *info = NULL;
982 info = spi_flash_read_id(flash);
983 if (IS_ERR_OR_NULL(info))
987 * Flash powers up read-only, so clear BP# bits.
989 * Note on some flash (like Macronix), QE (quad enable) bit is in the
990 * same status register as BP# bits, and we need preserve its original
991 * value during a reboot cycle as this is required by some platforms
992 * (like Intel ICH SPI controller working under descriptor mode).
994 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
995 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) ||
996 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) {
999 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
1000 read_sr(flash, &sr);
1001 sr &= STATUS_QEB_MXIC;
1003 write_sr(flash, sr);
1006 flash->name = info->name;
1007 flash->memory_map = spi->memory_map;
1009 if (info->flags & SST_WR)
1010 flash->flags |= SNOR_F_SST_WR;
1012 #ifndef CONFIG_DM_SPI_FLASH
1013 flash->write = spi_flash_cmd_write_ops;
1014 #if defined(CONFIG_SPI_FLASH_SST)
1015 if (flash->flags & SNOR_F_SST_WR) {
1016 if (spi->mode & SPI_TX_BYTE)
1017 flash->write = sst_write_bp;
1019 flash->write = sst_write_wp;
1022 flash->erase = spi_flash_cmd_erase_ops;
1023 flash->read = spi_flash_cmd_read_ops;
1026 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
1027 /* NOR protection support for STmicro/Micron chips and similar */
1028 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO ||
1029 JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) {
1030 flash->flash_lock = stm_lock;
1031 flash->flash_unlock = stm_unlock;
1032 flash->flash_is_locked = stm_is_locked;
1036 /* Compute the flash size */
1037 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
1038 flash->page_size = info->page_size;
1040 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
1041 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
1042 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
1045 if (JEDEC_EXT(info) == 0x4d00) {
1046 if ((JEDEC_ID(info) != 0x0215) &&
1047 (JEDEC_ID(info) != 0x0216))
1048 flash->page_size = 512;
1050 flash->page_size <<= flash->shift;
1051 flash->sector_size = info->sector_size << flash->shift;
1052 flash->size = flash->sector_size * info->n_sectors << flash->shift;
1053 #ifdef CONFIG_SF_DUAL_FLASH
1054 if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
1058 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1059 /* Compute erase sector and command */
1060 if (info->flags & SECT_4K) {
1061 flash->erase_cmd = CMD_ERASE_4K;
1062 flash->erase_size = 4096 << flash->shift;
1066 flash->erase_cmd = CMD_ERASE_64K;
1067 flash->erase_size = flash->sector_size;
1070 /* Now erase size becomes valid sector size */
1071 flash->sector_size = flash->erase_size;
1073 /* Look for read commands */
1074 flash->read_cmd = CMD_READ_ARRAY_FAST;
1075 if (spi->mode & SPI_RX_SLOW)
1076 flash->read_cmd = CMD_READ_ARRAY_SLOW;
1077 else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
1078 flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
1079 else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
1080 flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
1082 /* Look for write commands */
1083 if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
1084 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
1086 /* Go for default supported write cmd */
1087 flash->write_cmd = CMD_PAGE_PROGRAM;
1089 /* Set the quad enable bit - only for quad commands */
1090 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
1091 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
1092 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
1093 ret = set_quad_mode(flash, info);
1095 debug("SF: Fail to set QEB for %02x\n",
1101 /* Read dummy_byte: dummy byte is determined based on the
1102 * dummy cycles of a particular command.
1103 * Fast commands - dummy_byte = dummy_cycles/8
1104 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
1105 * For I/O commands except cmd[0] everything goes on no.of lines
1106 * based on particular command but incase of fast commands except
1107 * data all go on single line irrespective of command.
1109 switch (flash->read_cmd) {
1110 case CMD_READ_QUAD_IO_FAST:
1111 flash->dummy_byte = 2;
1113 case CMD_READ_ARRAY_SLOW:
1114 flash->dummy_byte = 0;
1117 flash->dummy_byte = 1;
1120 #ifdef CONFIG_SPI_FLASH_STMICRO
1121 if (info->flags & E_FSR)
1122 flash->flags |= SNOR_F_USE_FSR;
1125 /* Configure the BAR - discover bank cmds and read current bank */
1126 #ifdef CONFIG_SPI_FLASH_BAR
1127 ret = read_bar(flash, info);
1132 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1133 ret = spi_flash_decode_fdt(flash);
1135 debug("SF: FDT decode error\n");
1140 #ifndef CONFIG_SPL_BUILD
1141 printf("SF: Detected %s with page size ", flash->name);
1142 print_size(flash->page_size, ", erase size ");
1143 print_size(flash->erase_size, ", total ");
1144 print_size(flash->size, "");
1145 if (flash->memory_map)
1146 printf(", mapped at %p", flash->memory_map);
1150 #ifndef CONFIG_SPI_FLASH_BAR
1151 if (((flash->dual_flash == SF_SINGLE_FLASH) &&
1152 (flash->size > SPI_FLASH_16MB_BOUN)) ||
1153 ((flash->dual_flash > SF_SINGLE_FLASH) &&
1154 (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
1155 puts("SF: Warning - Only lower 16MiB accessible,");
1156 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");