4 * Copyright (C) 2008 Atmel Corporation
5 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
8 * Licensed under the GPL-2 or later.
13 #include <spi_flash.h>
16 #include "spi_flash_internal.h"
18 static void spi_flash_addr(u32 addr, u8 *cmd)
20 /* cmd[0] is actual command */
26 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
31 cmd = CMD_WRITE_STATUS;
32 ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
34 debug("SF: fail to write status register\n");
41 #ifdef CONFIG_SPI_FLASH_BAR
42 int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
47 if (flash->bank_curr == bank_sel) {
48 debug("SF: not require to enable bank%d\n", bank_sel);
52 cmd = flash->bank_write_cmd;
53 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
55 debug("SF: fail to write bank register\n");
58 flash->bank_curr = bank_sel;
64 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
66 struct spi_slave *spi = flash->spi;
67 unsigned long timebase;
70 u8 check_status = 0x0;
71 u8 poll_bit = STATUS_WIP;
72 u8 cmd = flash->poll_cmd;
74 if (cmd == CMD_FLAG_STATUS) {
75 poll_bit = STATUS_PEC;
76 check_status = poll_bit;
79 ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
81 debug("SF: fail to read %s status register\n",
82 cmd == CMD_READ_STATUS ? "read" : "flag");
86 timebase = get_timer(0);
90 ret = spi_xfer(spi, 8, NULL, &status, 0);
94 if ((status & poll_bit) == check_status)
97 } while (get_timer(timebase) < timeout);
99 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
101 if ((status & poll_bit) == check_status)
105 debug("SF: time out!\n");
109 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
110 size_t cmd_len, const void *buf, size_t buf_len)
112 struct spi_slave *spi = flash->spi;
113 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
117 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
119 ret = spi_claim_bus(flash->spi);
121 debug("SF: unable to claim SPI bus\n");
125 ret = spi_flash_cmd_write_enable(flash);
127 debug("SF: enabling write failed\n");
131 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
133 debug("SF: write cmd failed\n");
137 ret = spi_flash_cmd_wait_ready(flash, timeout);
139 debug("SF: write %s timed out\n",
140 timeout == SPI_FLASH_PROG_TIMEOUT ?
141 "program" : "page erase");
145 spi_release_bus(spi);
150 int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
156 erase_size = flash->sector_size;
157 if (offset % erase_size || len % erase_size) {
158 debug("SF: Erase offset/length not multiple of erase size\n");
162 if (erase_size == 4096)
163 cmd[0] = CMD_ERASE_4K;
165 cmd[0] = CMD_ERASE_64K;
168 #ifdef CONFIG_SPI_FLASH_BAR
171 bank_sel = offset / SPI_FLASH_16MB_BOUN;
173 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
175 debug("SF: fail to set bank%d\n", bank_sel);
179 spi_flash_addr(offset, cmd);
181 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
182 cmd[2], cmd[3], offset);
184 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
186 debug("SF: erase failed\n");
190 offset += erase_size;
197 int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
198 size_t len, const void *buf)
200 unsigned long byte_addr, page_size;
201 size_t chunk_len, actual;
205 page_size = flash->page_size;
207 cmd[0] = CMD_PAGE_PROGRAM;
208 for (actual = 0; actual < len; actual += chunk_len) {
209 #ifdef CONFIG_SPI_FLASH_BAR
212 bank_sel = offset / SPI_FLASH_16MB_BOUN;
214 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
216 debug("SF: fail to set bank%d\n", bank_sel);
220 byte_addr = offset % page_size;
221 chunk_len = min(len - actual, page_size - byte_addr);
223 if (flash->spi->max_write_size)
224 chunk_len = min(chunk_len, flash->spi->max_write_size);
226 spi_flash_addr(offset, cmd);
228 debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
229 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
231 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
232 buf + actual, chunk_len);
234 debug("SF: write failed\n");
244 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
245 size_t cmd_len, void *data, size_t data_len)
247 struct spi_slave *spi = flash->spi;
250 ret = spi_claim_bus(flash->spi);
252 debug("SF: unable to claim SPI bus\n");
256 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
258 debug("SF: read cmd failed\n");
262 spi_release_bus(spi);
267 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
268 size_t len, void *data)
270 u8 cmd[5], bank_sel = 0;
271 u32 remain_len, read_len;
274 /* Handle memory-mapped SPI */
275 if (flash->memory_map) {
276 memcpy(data, flash->memory_map + offset, len);
280 cmd[0] = CMD_READ_ARRAY_FAST;
284 #ifdef CONFIG_SPI_FLASH_BAR
285 bank_sel = offset / SPI_FLASH_16MB_BOUN;
287 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
289 debug("SF: fail to set bank%d\n", bank_sel);
293 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
294 if (len < remain_len)
297 read_len = remain_len;
299 spi_flash_addr(offset, cmd);
301 ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
304 debug("SF: read failed\n");