2 * drivers/mtd/nandids.c
4 * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
6 * $Id: nand_ids.c,v 1.10 2004/05/26 13:40:12 gleixner Exp $
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 #ifdef CFG_NAND_LEGACY
17 #error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
20 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
22 #include <linux/mtd/nand.h>
27 * Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
30 * Pagesize; 0, 256, 512
31 * 0 get this information from the extended chip ID
32 + 256 256 Byte page size
33 * 512 512 Byte page size
35 struct nand_flash_dev nand_flash_ids[] = {
36 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
37 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
38 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
39 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
40 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
41 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
42 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
43 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
44 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
45 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
47 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
48 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
49 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
50 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
52 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
53 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
54 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
55 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
57 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
58 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
59 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
60 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
62 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
63 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
64 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
65 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
67 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
68 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
69 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
70 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
72 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
74 {"NAND 512MiB 3,3V 8-bit", 0xDC, 512, 512, 0x4000, 0},
76 /* These are the new chips with large page size. The pagesize
77 * and the erasesize is determined from the extended id bytes
80 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
81 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
82 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
83 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
86 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
87 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
88 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
89 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
92 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
93 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
94 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
95 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
98 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
99 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
100 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
101 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
104 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
105 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
106 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
107 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
109 /* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout !
110 * The chosen minimum erasesize is 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page planes
111 * 1 block = 2 pages, but due to plane arrangement the blocks 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7
112 * Anyway JFFS2 would increase the eraseblock size so we chose a combined one which can be erased in one go
113 * There are more speed improvements for reads and writes possible, but not implemented now
115 {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, NAND_IS_AND | NAND_NO_AUTOINCR | NAND_4PAGE_ARRAY},
121 * Manufacturer ID list
123 struct nand_manufacturers nand_manuf_ids[] = {
124 {NAND_MFR_TOSHIBA, "Toshiba"},
125 {NAND_MFR_SAMSUNG, "Samsung"},
126 {NAND_MFR_FUJITSU, "Fujitsu"},
127 {NAND_MFR_NATIONAL, "National"},
128 {NAND_MFR_RENESAS, "Renesas"},
129 {NAND_MFR_STMICRO, "ST Micro"},