2 * Altera 10/100/1000 triple speed ethernet mac driver
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
14 #include <fdt_support.h>
18 #include <asm/cache.h>
19 #include <asm/dma-mapping.h>
21 #include "altera_tse.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 static inline void alt_sgdma_construct_descriptor(
26 struct alt_sgdma_descriptor *desc,
27 struct alt_sgdma_descriptor *next,
33 int write_fixed_or_sop)
38 * Mark the "next" descriptor as "not" owned by hardware. This prevents
39 * The SGDMA controller from continuing to process the chain.
41 next->descriptor_control = next->descriptor_control &
42 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
44 memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
45 desc->source = virt_to_phys(read_addr);
46 desc->destination = virt_to_phys(write_addr);
47 desc->next = virt_to_phys(next);
48 desc->bytes_to_transfer = length_or_eop;
51 * Set the descriptor control block as follows:
52 * - Set "owned by hardware" bit
53 * - Optionally set "generate EOP" bit
54 * - Optionally set the "read from fixed address" bit
55 * - Optionally set the "write to fixed address bit (which serves
56 * serves as a "generate SOP" control bit in memory-to-stream mode).
57 * - Set the 4-bit atlantic channel, if specified
59 * Note this step is performed after all other descriptor information
60 * has been filled out so that, if the controller already happens to be
61 * pointing at this descriptor, it will not run (via the "owned by
62 * hardware" bit) until all other descriptor has been set up.
64 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
66 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
68 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
69 if (write_fixed_or_sop)
70 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
71 desc->descriptor_control = val;
74 static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
79 /* Wait for the descriptor (chain) to complete */
82 status = readl(®s->status);
83 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
85 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
87 debug("sgdma timeout\n");
93 writel(0, ®s->control);
95 writel(0xff, ®s->status);
100 static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
101 struct alt_sgdma_descriptor *desc)
105 /* Point the controller at the descriptor */
106 writel(virt_to_phys(desc), ®s->next_descriptor_pointer);
109 * Set up SGDMA controller to:
110 * - Disable interrupt generation
111 * - Run once a valid descriptor is written to controller
112 * - Stop on an error with any particular descriptor
114 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
115 writel(val, ®s->control);
120 static void tse_adjust_link(struct altera_tse_priv *priv,
121 struct phy_device *phydev)
123 struct alt_tse_mac *mac_dev = priv->mac_dev;
127 debug("%s: No link.\n", phydev->dev->name);
131 refvar = readl(&mac_dev->command_config);
134 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
136 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
138 switch (phydev->speed) {
140 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
141 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
144 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
145 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
148 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
149 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
152 writel(refvar, &mac_dev->command_config);
155 static int altera_tse_send(struct udevice *dev, void *packet, int length)
157 struct altera_tse_priv *priv = dev_get_priv(dev);
158 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
159 unsigned long tx_buf = (unsigned long)packet;
161 flush_dcache_range(tx_buf, tx_buf + length);
162 alt_sgdma_construct_descriptor(
165 packet, /* read addr */
166 NULL, /* write addr */
167 length, /* length or EOP ,will change for each tx */
170 1 /* write fixed or sop */
173 /* send the packet */
174 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
175 alt_sgdma_wait_transfer(priv->sgdma_tx);
176 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
178 return tx_desc->actual_bytes_transferred;
181 static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
183 struct altera_tse_priv *priv = dev_get_priv(dev);
184 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
187 if (rx_desc->descriptor_status &
188 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
189 packet_length = rx_desc->actual_bytes_transferred;
190 debug("recv %d bytes\n", packet_length);
191 *packetp = priv->rx_buf;
193 return packet_length;
199 static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
202 struct altera_tse_priv *priv = dev_get_priv(dev);
203 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
204 unsigned long rx_buf = (unsigned long)priv->rx_buf;
206 alt_sgdma_wait_transfer(priv->sgdma_rx);
207 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
208 alt_sgdma_construct_descriptor(
211 NULL, /* read addr */
212 priv->rx_buf, /* write addr */
213 0, /* length or EOP */
216 0 /* write fixed or sop */
219 /* setup the sgdma */
220 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
221 debug("recv setup\n");
226 static void altera_tse_stop_mac(struct altera_tse_priv *priv)
228 struct alt_tse_mac *mac_dev = priv->mac_dev;
233 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
234 ctime = get_timer(0);
236 status = readl(&mac_dev->command_config);
237 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
239 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
240 debug("Reset mac timeout\n");
246 static void altera_tse_stop(struct udevice *dev)
248 struct altera_tse_priv *priv = dev_get_priv(dev);
249 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
250 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
251 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
254 /* clear rx desc & wait for sgdma to complete */
255 rx_desc->descriptor_control = 0;
256 writel(0, &rx_sgdma->control);
257 ret = alt_sgdma_wait_transfer(rx_sgdma);
258 if (ret == -ETIMEDOUT)
259 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
262 writel(0, &tx_sgdma->control);
263 ret = alt_sgdma_wait_transfer(tx_sgdma);
264 if (ret == -ETIMEDOUT)
265 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
268 altera_tse_stop_mac(priv);
271 static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
273 struct altera_tse_priv *priv = bus->priv;
274 struct alt_tse_mac *mac_dev = priv->mac_dev;
277 /* set mdio address */
278 writel(addr, &mac_dev->mdio_phy1_addr);
280 value = readl(&mac_dev->mdio_phy1[reg]);
282 return value & 0xffff;
285 static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
288 struct altera_tse_priv *priv = bus->priv;
289 struct alt_tse_mac *mac_dev = priv->mac_dev;
291 /* set mdio address */
292 writel(addr, &mac_dev->mdio_phy1_addr);
294 writel(val, &mac_dev->mdio_phy1[reg]);
299 static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
301 struct mii_dev *bus = mdio_alloc();
304 printf("Failed to allocate MDIO bus\n");
308 bus->read = tse_mdio_read;
309 bus->write = tse_mdio_write;
310 snprintf(bus->name, sizeof(bus->name), name);
312 bus->priv = (void *)priv;
314 return mdio_register(bus);
317 static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
319 struct phy_device *phydev;
320 unsigned int mask = 0xffffffff;
323 mask = 1 << priv->phyaddr;
325 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
329 phy_connect_dev(phydev, dev);
331 phydev->supported &= PHY_GBIT_FEATURES;
332 phydev->advertising = phydev->supported;
334 priv->phydev = phydev;
340 static int altera_tse_write_hwaddr(struct udevice *dev)
342 struct altera_tse_priv *priv = dev_get_priv(dev);
343 struct alt_tse_mac *mac_dev = priv->mac_dev;
344 struct eth_pdata *pdata = dev_get_platdata(dev);
345 u8 *hwaddr = pdata->enetaddr;
348 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
349 (hwaddr[1] << 8) | hwaddr[0];
350 mac_hi = (hwaddr[5] << 8) | hwaddr[4];
351 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
353 writel(mac_lo, &mac_dev->mac_addr_0);
354 writel(mac_hi, &mac_dev->mac_addr_1);
355 writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
356 writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
357 writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
358 writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
359 writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
360 writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
361 writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
362 writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
367 static int altera_tse_start(struct udevice *dev)
369 struct altera_tse_priv *priv = dev_get_priv(dev);
370 struct alt_tse_mac *mac_dev = priv->mac_dev;
374 /* need to create sgdma */
375 debug("Configuring rx desc\n");
376 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
378 debug("Configuring TSE Mac\n");
379 /* Initialize MAC registers */
380 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
381 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
382 writel(0, &mac_dev->rx_sel_full_threshold);
383 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
384 writel(0, &mac_dev->tx_sel_full_threshold);
385 writel(8, &mac_dev->rx_almost_empty_threshold);
386 writel(8, &mac_dev->rx_almost_full_threshold);
387 writel(8, &mac_dev->tx_almost_empty_threshold);
388 writel(3, &mac_dev->tx_almost_full_threshold);
391 writel(0, &mac_dev->rx_cmd_stat);
392 writel(0, &mac_dev->tx_cmd_stat);
395 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
396 writel(val, &mac_dev->command_config);
398 /* Start up the PHY */
399 ret = phy_startup(priv->phydev);
401 debug("Could not initialize PHY %s\n",
402 priv->phydev->dev->name);
406 tse_adjust_link(priv, priv->phydev);
408 if (!priv->phydev->link)
414 static int altera_tse_probe(struct udevice *dev)
416 struct eth_pdata *pdata = dev_get_platdata(dev);
417 struct altera_tse_priv *priv = dev_get_priv(dev);
418 void *blob = (void *)gd->fdt_blob;
419 int node = dev->of_offset;
420 const char *list, *end;
422 void *base, *desc_mem = NULL;
423 unsigned long addr, size;
424 int parent, addrc, sizec;
429 * decode regs. there are multiple reg tuples, and they need to
430 * match with reg-names.
432 parent = fdt_parent_offset(blob, node);
433 of_bus_default_count_cells(blob, parent, &addrc, &sizec);
434 list = fdt_getprop(blob, node, "reg-names", &len);
438 cell = fdt_getprop(blob, node, "reg", &len);
443 addr = fdt_translate_address((void *)blob,
445 size = fdt_addr_to_cpu(cell[idx + addrc]);
446 base = ioremap(addr, size);
448 if (strcmp(list, "control_port") == 0)
449 priv->mac_dev = base;
450 else if (strcmp(list, "rx_csr") == 0)
451 priv->sgdma_rx = base;
452 else if (strcmp(list, "tx_csr") == 0)
453 priv->sgdma_tx = base;
454 else if (strcmp(list, "s1") == 0)
456 idx += addrc + sizec;
459 /* decode fifo depth */
460 priv->rx_fifo_depth = fdtdec_get_int(blob, node,
462 priv->tx_fifo_depth = fdtdec_get_int(blob, node,
465 addr = fdtdec_get_int(blob, node,
467 addr = fdt_node_offset_by_phandle(blob, addr);
468 priv->phyaddr = fdtdec_get_int(blob, addr,
471 len = sizeof(struct alt_sgdma_descriptor) * 4;
473 desc_mem = dma_alloc_coherent(len, &addr);
477 memset(desc_mem, 0, len);
478 priv->tx_desc = desc_mem;
479 priv->rx_desc = priv->tx_desc + 2;
480 /* allocate recv packet buffer */
481 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
485 /* stop controller */
486 debug("Reset TSE & SGDMAs\n");
487 altera_tse_stop(dev);
490 priv->interface = pdata->phy_interface;
491 tse_mdio_init(dev->name, priv);
492 priv->bus = miiphy_get_dev_by_name(dev->name);
494 ret = tse_phy_init(priv, dev);
499 static int altera_tse_ofdata_to_platdata(struct udevice *dev)
501 struct eth_pdata *pdata = dev_get_platdata(dev);
502 const char *phy_mode;
504 pdata->phy_interface = -1;
505 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
507 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
508 if (pdata->phy_interface == -1) {
509 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
516 static const struct eth_ops altera_tse_ops = {
517 .start = altera_tse_start,
518 .send = altera_tse_send,
519 .recv = altera_tse_recv,
520 .free_pkt = altera_tse_free_pkt,
521 .stop = altera_tse_stop,
522 .write_hwaddr = altera_tse_write_hwaddr,
525 static const struct udevice_id altera_tse_ids[] = {
526 { .compatible = "altr,tse-1.0", },
530 U_BOOT_DRIVER(altera_tse) = {
531 .name = "altera_tse",
533 .of_match = altera_tse_ids,
534 .ops = &altera_tse_ops,
535 .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
536 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
537 .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
538 .probe = altera_tse_probe,