2 * Altera 10/100/1000 triple speed ethernet mac
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef _ALTERA_TSE_H_
12 #define _ALTERA_TSE_H_
14 #define __packed_1_ __attribute__ ((packed, aligned(1)))
17 #define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001)
18 #define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002)
19 #define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004)
20 #define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008)
21 #define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010)
23 #define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020)
24 #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040)
25 #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000)
27 #define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \
28 | ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \
29 | ALT_SGDMA_CONTROL_IE_GLOBAL_MSK)
32 * Descriptor control bit masks & offsets
34 * Note: The control byte physically occupies bits [31:24] in memory.
35 * The following bit-offsets are expressed relative to the LSB of
36 * the control register bitfield.
38 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001)
39 #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002)
40 #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004)
41 #define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008)
42 #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080)
45 * Descriptor status bit masks & offsets
47 * Note: The status byte physically occupies bits [23:16] in memory.
48 * The following bit-offsets are expressed relative to the LSB of
49 * the status register bitfield.
51 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001)
52 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002)
53 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004)
54 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008)
55 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010)
56 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020)
57 #define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040)
58 #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080)
59 #define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F)
62 * The SGDMA controller buffer descriptor allocates
63 * 64 bits for each address. To support ANSI C, the
64 * struct implementing a descriptor places 32-bits
65 * of padding directly above each address; each pad must
66 * be cleared when initializing a descriptor.
70 * Buffer Descriptor data structure
73 struct alt_sgdma_descriptor {
74 unsigned int source; /* the address of data to be read. */
75 unsigned int source_pad;
77 unsigned int destination; /* the address to write data */
78 unsigned int destination_pad;
80 unsigned int next; /* the next descriptor in the list. */
81 unsigned int next_pad;
83 unsigned short bytes_to_transfer; /* the number of bytes to transfer */
84 unsigned char read_burst;
85 unsigned char write_burst;
87 unsigned short actual_bytes_transferred;/* bytes transferred by DMA */
88 unsigned char descriptor_status;
89 unsigned char descriptor_control;
93 /* SG-DMA Control/Status Slave registers map */
95 struct alt_sgdma_registers {
97 unsigned int status_pad[3];
99 unsigned int control_pad[3];
100 unsigned int next_descriptor_pointer;
101 unsigned int descriptor_pad[3];
105 #define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001)
106 #define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002)
107 #define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004)
108 #define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008)
109 #define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010)
110 #define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020)
111 #define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040)
112 #define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080)
113 #define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100)
114 #define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200)
115 #define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400)
116 #define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800)
117 #define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000)
118 #define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000)
119 #define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000)
120 #define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000)
121 /* Bits (18:16) = address select */
122 #define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000)
123 #define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000)
124 #define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000)
125 #define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000)
126 #define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000)
127 #define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000)
128 #define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000)
129 #define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000)
130 #define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000)
131 /* Bits (30..27) reserved */
132 #define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000)
134 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000)
135 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000)
137 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000)
139 #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
140 #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
142 /* MAC register Space */
145 unsigned int megacore_revision;
146 unsigned int scratch_pad;
147 unsigned int command_config;
148 unsigned int mac_addr_0;
149 unsigned int mac_addr_1;
150 unsigned int max_frame_length;
151 unsigned int pause_quanta;
152 unsigned int rx_sel_empty_threshold;
153 unsigned int rx_sel_full_threshold;
154 unsigned int tx_sel_empty_threshold;
155 unsigned int tx_sel_full_threshold;
156 unsigned int rx_almost_empty_threshold;
157 unsigned int rx_almost_full_threshold;
158 unsigned int tx_almost_empty_threshold;
159 unsigned int tx_almost_full_threshold;
160 unsigned int mdio_phy0_addr;
161 unsigned int mdio_phy1_addr;
163 /* only if 100/1000 BaseX PCS, reserved otherwise */
164 unsigned int reservedx44[5];
166 unsigned int reg_read_access_status;
167 unsigned int min_tx_ipg_length;
169 /* IEEE 802.3 oEntity Managed Object Support */
170 unsigned int aMACID_1; /*The MAC addresses */
171 unsigned int aMACID_2;
172 unsigned int aFramesTransmittedOK;
173 unsigned int aFramesReceivedOK;
174 unsigned int aFramesCheckSequenceErrors;
175 unsigned int aAlignmentErrors;
176 unsigned int aOctetsTransmittedOK;
177 unsigned int aOctetsReceivedOK;
179 /* IEEE 802.3 oPausedEntity Managed Object Support */
180 unsigned int aTxPAUSEMACCtrlFrames;
181 unsigned int aRxPAUSEMACCtrlFrames;
183 /* IETF MIB (MIB-II) Object Support */
184 unsigned int ifInErrors;
185 unsigned int ifOutErrors;
186 unsigned int ifInUcastPkts;
187 unsigned int ifInMulticastPkts;
188 unsigned int ifInBroadcastPkts;
189 unsigned int ifOutDiscards;
190 unsigned int ifOutUcastPkts;
191 unsigned int ifOutMulticastPkts;
192 unsigned int ifOutBroadcastPkts;
194 /* IETF RMON MIB Object Support */
195 unsigned int etherStatsDropEvent;
196 unsigned int etherStatsOctets;
197 unsigned int etherStatsPkts;
198 unsigned int etherStatsUndersizePkts;
199 unsigned int etherStatsOversizePkts;
200 unsigned int etherStatsPkts64Octets;
201 unsigned int etherStatsPkts65to127Octets;
202 unsigned int etherStatsPkts128to255Octets;
203 unsigned int etherStatsPkts256to511Octets;
204 unsigned int etherStatsPkts512to1023Octets;
205 unsigned int etherStatsPkts1024to1518Octets;
207 unsigned int etherStatsPkts1519toXOctets;
208 unsigned int etherStatsJabbers;
209 unsigned int etherStatsFragments;
211 unsigned int reservedxE4;
213 /*FIFO control register. */
214 unsigned int tx_cmd_stat;
215 unsigned int rx_cmd_stat;
217 unsigned int ipaccTxConf;
218 unsigned int ipaccRxConf;
219 unsigned int ipaccRxStat;
220 unsigned int ipaccRxStatSum;
222 /*Multicast address resolution table */
223 unsigned int hash_table[64];
225 /*Registers 0 to 31 within PHY device 0/1 */
226 unsigned int mdio_phy0[0x20];
227 unsigned int mdio_phy1[0x20];
229 /*4 Supplemental MAC Addresses */
230 unsigned int supp_mac_addr_0_0;
231 unsigned int supp_mac_addr_0_1;
232 unsigned int supp_mac_addr_1_0;
233 unsigned int supp_mac_addr_1_1;
234 unsigned int supp_mac_addr_2_0;
235 unsigned int supp_mac_addr_2_1;
236 unsigned int supp_mac_addr_3_0;
237 unsigned int supp_mac_addr_3_1;
239 unsigned int reservedx320[56];
242 struct altera_tse_priv {
243 struct alt_tse_mac *mac_dev;
244 struct alt_sgdma_registers *sgdma_rx;
245 struct alt_sgdma_registers *sgdma_tx;
246 unsigned int rx_fifo_depth;
247 unsigned int tx_fifo_depth;
248 struct alt_sgdma_descriptor *rx_desc;
249 struct alt_sgdma_descriptor *tx_desc;
250 unsigned char *rx_buf;
251 unsigned int phyaddr;
252 unsigned int interface;
253 struct phy_device *phydev;
257 #endif /* _ALTERA_TSE_H_ */