2 * Driver for Blackfin On-Chip MAC device
4 * Copyright (c) 2005-2008 Analog Device, Inc.
6 * Licensed under the GPL-2 or later.
16 #include <linux/mii.h>
18 #include <asm/blackfin.h>
19 #include <asm/portmux.h>
20 #include <asm/mach-common/bits/dma.h>
21 #include <asm/mach-common/bits/emac.h>
22 #include <asm/mach-common/bits/pll.h>
26 #ifndef CONFIG_PHY_ADDR
27 # define CONFIG_PHY_ADDR 1
29 #ifndef CONFIG_PHY_CLOCK_FREQ
30 # define CONFIG_PHY_CLOCK_FREQ 2500000
37 #define RXBUF_BASE_ADDR 0xFF900000
38 #define TXBUF_BASE_ADDR 0xFF800000
41 #define TOUT_LOOP 1000000
43 static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
44 static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
45 static u16 txIdx; /* index of the current RX buffer */
46 static u16 rxIdx; /* index of the current TX buffer */
48 /* DMAx_CONFIG values at DMA Restart */
51 ADI_DMA_CONFIG_REG reg;
54 .b_DMA_EN = 1, /* enabled */
55 .b_WNR = 0, /* read from memory */
56 .b_WDSIZE = 2, /* wordsize is 32 bits */
60 .b_DI_EN = 0, /* no interrupt */
61 .b_NDSIZE = 5, /* 5 half words is desc size */
62 .b_FLOW = 7 /* large desc flow */
66 static int bfin_miiphy_wait(void)
68 /* poll the STABUSY bit */
69 while (bfin_read_EMAC_STAADD() & STABUSY)
74 static int bfin_miiphy_read(const char *devname, uchar addr, uchar reg, ushort *val)
76 if (bfin_miiphy_wait())
78 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
79 if (bfin_miiphy_wait())
81 *val = bfin_read_EMAC_STADAT();
85 static int bfin_miiphy_write(const char *devname, uchar addr, uchar reg, ushort val)
87 if (bfin_miiphy_wait())
89 bfin_write_EMAC_STADAT(val);
90 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
94 int bfin_EMAC_initialize(bd_t *bis)
96 struct eth_device *dev;
97 dev = malloc(sizeof(*dev));
101 memset(dev, 0, sizeof(*dev));
102 strcpy(dev->name, "bfin_mac");
106 dev->init = bfin_EMAC_init;
107 dev->halt = bfin_EMAC_halt;
108 dev->send = bfin_EMAC_send;
109 dev->recv = bfin_EMAC_recv;
110 dev->write_hwaddr = bfin_EMAC_setup_addr;
114 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
115 miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
121 static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
126 buf = (unsigned int *)packet;
129 printf("Ethernet: bad packet size: %d\n", length);
133 if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
134 printf("Ethernet: tx DMA error\n");
138 for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
140 puts("Ethernet: tx time out\n");
144 txbuf[txIdx]->FrmData->NoBytes = length;
145 memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
146 txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
147 bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
148 bfin_write_DMA2_CONFIG(txdmacfg.data);
149 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
151 for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
153 puts("Ethernet: tx error\n");
157 result = txbuf[txIdx]->StatusWord;
158 txbuf[txIdx]->StatusWord = 0;
159 if ((txIdx + 1) >= TX_BUF_CNT)
164 debug("BFIN EMAC send: length = %d\n", length);
168 static int bfin_EMAC_recv(struct eth_device *dev)
173 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
177 if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
178 printf("Ethernet: rx dma overrun\n");
181 if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
182 printf("Ethernet: rx error\n");
185 length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
187 printf("Ethernet: bad frame\n");
191 debug("%s: len = %d\n", __func__, length - 4);
193 NetRxPackets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
194 NetReceive(NetRxPackets[rxIdx], length - 4);
195 bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
196 rxbuf[rxIdx]->StatusWord = 0x00000000;
197 if ((rxIdx + 1) >= PKTBUFSRX)
206 /**************************************************************
208 * Ethernet Initialization Routine
210 *************************************************************/
212 /* MDC = SCLK / MDC_freq / 2 - 1 */
213 #define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
215 #ifndef CONFIG_BFIN_MAC_PINS
217 # define CONFIG_BFIN_MAC_PINS P_RMII0
219 # define CONFIG_BFIN_MAC_PINS P_MII0
223 static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
225 const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
229 /* Enable PHY output */
230 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
232 /* Set all the pins to peripheral mode */
233 peripheral_request_list(pins, "bfin_mac");
235 /* Odd word alignment for Receive Frame DMA word */
236 /* Configure checksum support and rcve frame word alignment */
237 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
239 /* turn on auto-negotiation and wait for link to come up */
240 bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
244 if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
246 if (phydat & BMSR_LSTATUS)
249 printf("%s: link down, check cable\n", dev->name);
255 /* see what kind of link we have */
256 if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
258 if (phydat & LPA_DUPLEX)
263 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
265 /* Initialize the TX DMA channel registers */
266 bfin_write_DMA2_X_COUNT(0);
267 bfin_write_DMA2_X_MODIFY(4);
268 bfin_write_DMA2_Y_COUNT(0);
269 bfin_write_DMA2_Y_MODIFY(0);
271 /* Initialize the RX DMA channel registers */
272 bfin_write_DMA1_X_COUNT(0);
273 bfin_write_DMA1_X_MODIFY(4);
274 bfin_write_DMA1_Y_COUNT(0);
275 bfin_write_DMA1_Y_MODIFY(0);
280 static int bfin_EMAC_setup_addr(struct eth_device *dev)
282 bfin_write_EMAC_ADDRLO(
284 dev->enetaddr[1] << 8 |
285 dev->enetaddr[2] << 16 |
286 dev->enetaddr[3] << 24
288 bfin_write_EMAC_ADDRHI(
290 dev->enetaddr[5] << 8
295 static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
300 debug("Eth_init: ......\n");
305 /* Initialize System Register */
306 if (bfin_miiphy_init(dev, &dat) < 0)
309 /* Initialize EMAC address */
310 bfin_EMAC_setup_addr(dev);
312 /* Initialize TX and RX buffer */
313 for (i = 0; i < PKTBUFSRX; i++) {
314 rxbuf[i] = SetupRxBuffer(i);
316 rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
317 if (i == (PKTBUFSRX - 1))
318 rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
321 for (i = 0; i < TX_BUF_CNT; i++) {
322 txbuf[i] = SetupTxBuffer(i);
324 txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
325 if (i == (TX_BUF_CNT - 1))
326 txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
331 bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
332 bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
337 /* We enable only RX here */
338 /* ASTP : Enable Automatic Pad Stripping
339 PR : Promiscuous Mode for test
340 PSF : Receive frames with total length less than 64 bytes.
341 FDMODE : Full Duplex Mode
342 LB : Internal Loopback for test
343 RE : Receiver Enable */
345 opmode = ASTP | FDMODE | PSF;
352 /* Turn on the EMAC */
353 bfin_write_EMAC_OPMODE(opmode);
357 static void bfin_EMAC_halt(struct eth_device *dev)
359 debug("Eth_halt: ......\n");
360 /* Turn off the EMAC */
361 bfin_write_EMAC_OPMODE(0);
362 /* Turn off the EMAC RX DMA */
363 bfin_write_DMA1_CONFIG(0);
364 bfin_write_DMA2_CONFIG(0);
367 ADI_ETHER_BUFFER *SetupRxBuffer(int no)
369 ADI_ETHER_FRAME_BUFFER *frmbuf;
370 ADI_ETHER_BUFFER *buf;
371 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
372 int total_size = nobytes_buffer + RECV_BUFSIZE;
374 buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
375 frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
377 memset(buf, 0x00, nobytes_buffer);
378 buf->FrmData = frmbuf;
379 memset(frmbuf, 0xfe, RECV_BUFSIZE);
381 /* set up first desc to point to receive frame buffer */
382 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
383 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
384 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
385 buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
386 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
387 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
388 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
390 /* set up second desc to point to status word */
391 buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
392 buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
393 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
394 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
395 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
396 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
397 buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
398 buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
403 ADI_ETHER_BUFFER *SetupTxBuffer(int no)
405 ADI_ETHER_FRAME_BUFFER *frmbuf;
406 ADI_ETHER_BUFFER *buf;
407 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
408 int total_size = nobytes_buffer + RECV_BUFSIZE;
410 buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
411 frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
413 memset(buf, 0x00, nobytes_buffer);
414 buf->FrmData = frmbuf;
415 memset(frmbuf, 0x00, RECV_BUFSIZE);
417 /* set up first desc to point to receive frame buffer */
418 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
419 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
420 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
421 buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
422 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
423 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
424 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
426 /* set up second desc to point to status word */
427 buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
428 buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
429 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
430 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
431 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
432 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
433 buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
434 buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
439 #if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
440 int ether_post_test(int flags)
447 printf("\n--------");
448 bfin_EMAC_init(NULL, NULL);
449 /* construct the package */
450 addr = bfin_read_EMAC_ADDRLO();
451 buf[0] = buf[6] = addr;
452 buf[1] = buf[7] = addr >> 8;
453 buf[2] = buf[8] = addr >> 16;
454 buf[3] = buf[9] = addr >> 24;
455 addr = bfin_read_EMAC_ADDRHI();
456 buf[4] = buf[10] = addr;
457 buf[5] = buf[11] = addr >> 8;
458 buf[12] = 0x08; /* Type: ARP */
460 buf[14] = 0x00; /* Hardware type: Ethernet */
462 buf[16] = 0x08; /* Protocal type: IP */
464 buf[18] = 0x06; /* Hardware size */
465 buf[19] = 0x04; /* Protocol size */
466 buf[20] = 0x00; /* Opcode: request */
469 for (i = 0; i < 42; i++)
471 printf("--------Send 64 bytes......\n");
472 bfin_EMAC_send(NULL, buf, 64);
473 for (i = 0; i < 100; i++) {
475 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
481 printf("--------EMAC can't receive any data\n");
485 length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
486 for (i = 0; i < length; i++) {
487 if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
488 printf("--------EMAC receive error data!\n");
493 printf("--------receive %d bytes, matched\n", length);
494 bfin_EMAC_halt(NULL);