2 * Driver for Blackfin On-Chip MAC device
4 * Copyright (c) 2005-2008 Analog Device, Inc.
6 * Licensed under the GPL-2 or later.
16 #include <linux/mii.h>
18 #include <asm/blackfin.h>
19 #include <asm/mach-common/bits/dma.h>
20 #include <asm/mach-common/bits/emac.h>
21 #include <asm/mach-common/bits/pll.h>
32 #define DEBUGF(fmt, args...) printf(fmt, ##args)
34 #define DEBUGF(fmt, args...)
37 #define RXBUF_BASE_ADDR 0xFF900000
38 #define TXBUF_BASE_ADDR 0xFF800000
41 #define TOUT_LOOP 1000000
43 ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
44 ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
45 static u16 txIdx; /* index of the current RX buffer */
46 static u16 rxIdx; /* index of the current TX buffer */
48 /* DMAx_CONFIG values at DMA Restart */
49 const ADI_DMA_CONFIG_REG rxdmacfg = {
50 .b_DMA_EN = 1, /* enabled */
51 .b_WNR = 1, /* write to memory */
52 .b_WDSIZE = 2, /* wordsize is 32 bits */
56 .b_DI_EN = 0, /* no interrupt */
57 .b_NDSIZE = 5, /* 5 half words is desc size */
58 .b_FLOW = 7 /* large desc flow */
61 const ADI_DMA_CONFIG_REG txdmacfg = {
62 .b_DMA_EN = 1, /* enabled */
63 .b_WNR = 0, /* read from memory */
64 .b_WDSIZE = 2, /* wordsize is 32 bits */
68 .b_DI_EN = 0, /* no interrupt */
69 .b_NDSIZE = 5, /* 5 half words is desc size */
70 .b_FLOW = 7 /* large desc flow */
73 static int bfin_miiphy_wait(void)
75 /* poll the STABUSY bit */
76 while (bfin_read_EMAC_STAADD() & STABUSY)
81 static int bfin_miiphy_read(char *devname, uchar addr, uchar reg, ushort *val)
83 if (bfin_miiphy_wait())
85 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
86 if (bfin_miiphy_wait())
88 *val = bfin_read_EMAC_STADAT();
92 static int bfin_miiphy_write(char *devname, uchar addr, uchar reg, ushort val)
94 if (bfin_miiphy_wait())
96 bfin_write_EMAC_STADAT(val);
97 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
101 int bfin_EMAC_initialize(bd_t *bis)
103 struct eth_device *dev;
104 dev = malloc(sizeof(*dev));
108 memset(dev, 0, sizeof(*dev));
109 sprintf(dev->name, "Blackfin EMAC");
113 dev->init = bfin_EMAC_init;
114 dev->halt = bfin_EMAC_halt;
115 dev->send = bfin_EMAC_send;
116 dev->recv = bfin_EMAC_recv;
120 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
121 miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
127 static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
133 buf = (unsigned int *)packet;
136 printf("Ethernet: bad packet size: %d\n", length);
140 if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
141 printf("Ethernet: tx DMA error\n");
145 for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
147 puts("Ethernet: tx time out\n");
151 txbuf[txIdx]->FrmData->NoBytes = length;
152 memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
153 txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
154 *pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
155 *pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
158 for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
160 puts("Ethernet: tx error\n");
164 result = txbuf[txIdx]->StatusWord;
165 txbuf[txIdx]->StatusWord = 0;
166 if ((txIdx + 1) >= TX_BUF_CNT)
171 DEBUGF("BFIN EMAC send: length = %d\n", length);
175 static int bfin_EMAC_recv(struct eth_device *dev)
180 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
184 if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
185 printf("Ethernet: rx dma overrun\n");
188 if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
189 printf("Ethernet: rx error\n");
192 length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
194 printf("Ethernet: bad frame\n");
197 NetRxPackets[rxIdx] =
198 (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
199 NetReceive(NetRxPackets[rxIdx], length - 4);
200 *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
201 rxbuf[rxIdx]->StatusWord = 0x00000000;
202 if ((rxIdx + 1) >= PKTBUFSRX)
211 /**************************************************************
213 * Ethernet Initialization Routine
215 *************************************************************/
217 /* MDC = SCLK / MDC_freq / 2 - 1 */
218 #define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
220 static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
225 /* Enable PHY output */
226 *pVR_CTL |= CLKBUFOE;
228 /* Set all the pins to peripheral mode */
229 #ifdef CONFIG_BFIN_MAC_RMII
231 # if defined(__ADSPBF51x__)
232 *pPORTF_MUX = (*pPORTF_MUX & \
233 ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
234 PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
235 *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
236 *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
237 *pPORTG_FER |= PG0 | PG1 | PG2;
238 # elif defined(__ADSPBF52x__)
239 *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
240 *pPORTG_FER |= PG14 | PG15;
241 *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
242 PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
243 *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
245 *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
248 /* grab MII & RMII pins */
249 # if defined(__ADSPBF51x__)
250 *pPORTF_MUX = (*pPORTF_MUX & \
251 ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
252 PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
253 *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
254 *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
255 *pPORTG_FER |= PG0 | PG1 | PG2;
256 # elif defined(__ADSPBF52x__)
257 *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
258 *pPORTG_FER |= PG14 | PG15;
259 *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
260 *pPORTH_FER = -1; /* all pins */
262 *pPORTH_FER = -1; /* all pins */
266 /* Odd word alignment for Receive Frame DMA word */
267 /* Configure checksum support and rcve frame word alignment */
268 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(2500000)));
270 /* turn on auto-negotiation and wait for link to come up */
271 bfin_miiphy_write(dev->name, PHYADDR, MII_BMCR, BMCR_ANENABLE);
275 if (bfin_miiphy_read(dev->name, PHYADDR, MII_BMSR, &phydat))
277 if (phydat & BMSR_LSTATUS)
280 printf("%s: link down, check cable\n", dev->name);
286 /* see what kind of link we have */
287 if (bfin_miiphy_read(dev->name, PHYADDR, MII_LPA, &phydat))
289 if (phydat & LPA_DUPLEX)
294 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
296 /* Initialize the TX DMA channel registers */
302 /* Initialize the RX DMA channel registers */
311 static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
316 DEBUGF("Eth_init: ......\n");
321 /* Initialize System Register */
322 if (bfin_miiphy_init(dev, &dat) < 0)
325 /* Initialize EMAC address */
326 bfin_EMAC_setup_addr(bd);
328 /* Initialize TX and RX buffer */
329 for (i = 0; i < PKTBUFSRX; i++) {
330 rxbuf[i] = SetupRxBuffer(i);
332 rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
334 if (i == (PKTBUFSRX - 1))
335 rxbuf[i]->Dma[1].NEXT_DESC_PTR =
339 for (i = 0; i < TX_BUF_CNT; i++) {
340 txbuf[i] = SetupTxBuffer(i);
342 txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
344 if (i == (TX_BUF_CNT - 1))
345 txbuf[i]->Dma[1].NEXT_DESC_PTR =
351 *pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
352 *pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
357 /* We enable only RX here */
358 /* ASTP : Enable Automatic Pad Stripping
359 PR : Promiscuous Mode for test
360 PSF : Receive frames with total length less than 64 bytes.
361 FDMODE : Full Duplex Mode
362 LB : Internal Loopback for test
363 RE : Receiver Enable */
365 opmode = ASTP | FDMODE | PSF;
369 #ifdef CONFIG_BFIN_MAC_RMII
372 /* Turn on the EMAC */
373 *pEMAC_OPMODE = opmode;
377 static void bfin_EMAC_halt(struct eth_device *dev)
379 DEBUGF("Eth_halt: ......\n");
380 /* Turn off the EMAC */
381 *pEMAC_OPMODE = 0x00000000;
382 /* Turn off the EMAC RX DMA */
383 *pDMA1_CONFIG = 0x0000;
384 *pDMA2_CONFIG = 0x0000;
388 void bfin_EMAC_setup_addr(bd_t *bd)
392 bd->bi_enetaddr[1] << 8 |
393 bd->bi_enetaddr[2] << 16 |
394 bd->bi_enetaddr[3] << 24;
397 bd->bi_enetaddr[5] << 8;
400 ADI_ETHER_BUFFER *SetupRxBuffer(int no)
402 ADI_ETHER_FRAME_BUFFER *frmbuf;
403 ADI_ETHER_BUFFER *buf;
404 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
405 int total_size = nobytes_buffer + RECV_BUFSIZE;
407 buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
409 (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
412 memset(buf, 0x00, nobytes_buffer);
413 buf->FrmData = frmbuf;
414 memset(frmbuf, 0xfe, RECV_BUFSIZE);
416 /* set up first desc to point to receive frame buffer */
417 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
418 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
419 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
420 buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
421 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
422 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
423 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
425 /* set up second desc to point to status word */
426 buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
427 buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
428 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
429 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
430 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
431 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
432 buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
433 buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
438 ADI_ETHER_BUFFER *SetupTxBuffer(int no)
440 ADI_ETHER_FRAME_BUFFER *frmbuf;
441 ADI_ETHER_BUFFER *buf;
442 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
443 int total_size = nobytes_buffer + RECV_BUFSIZE;
445 buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
447 (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
450 memset(buf, 0x00, nobytes_buffer);
451 buf->FrmData = frmbuf;
452 memset(frmbuf, 0x00, RECV_BUFSIZE);
454 /* set up first desc to point to receive frame buffer */
455 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
456 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
457 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
458 buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
459 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
460 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
461 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
463 /* set up second desc to point to status word */
464 buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
465 buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
466 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
467 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
468 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
469 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
470 buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
471 buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
476 #if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
477 int ether_post_test(int flags)
483 printf("\n--------");
484 bfin_EMAC_init(NULL, NULL);
485 /* construct the package */
486 buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
487 buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
488 buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
489 buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
490 buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
491 buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
492 buf[12] = 0x08; /* Type: ARP */
494 buf[14] = 0x00; /* Hardware type: Ethernet */
496 buf[16] = 0x08; /* Protocal type: IP */
498 buf[18] = 0x06; /* Hardware size */
499 buf[19] = 0x04; /* Protocol size */
500 buf[20] = 0x00; /* Opcode: request */
503 for (i = 0; i < 42; i++)
505 printf("--------Send 64 bytes......\n");
506 bfin_EMAC_send(NULL, (volatile void *)buf, 64);
507 for (i = 0; i < 100; i++) {
509 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
515 printf("--------EMAC can't receive any data\n");
519 length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
520 for (i = 0; i < length; i++) {
521 if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
522 printf("--------EMAC receive error data!\n");
527 printf("--------receive %d bytes, matched\n", length);
528 bfin_EMAC_halt(NULL);