2 * CPSW Ethernet Switch Driver
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
24 #include <asm/errno.h>
27 #include <asm/arch/cpu.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define BITMASK(bits) (BIT(bits) - 1)
33 #define PHY_REG_MASK 0x1f
34 #define PHY_ID_MASK 0x1f
35 #define NUM_DESCS (PKTBUFSRX * 2)
37 #define PKT_MAX (1500 + 14 + 4 + 4)
39 #define GIGABITEN BIT(7)
40 #define FULLDUPLEXEN BIT(0)
44 #define CPSW_HOST_PORT_OFFSET 0x108
45 #define CPSW_SLAVE0_OFFSET 0x208
46 #define CPSW_SLAVE1_OFFSET 0x308
47 #define CPSW_SLAVE_SIZE 0x100
48 #define CPSW_CPDMA_OFFSET 0x800
49 #define CPSW_HW_STATS 0x900
50 #define CPSW_STATERAM_OFFSET 0xa00
51 #define CPSW_CPTS_OFFSET 0xc00
52 #define CPSW_ALE_OFFSET 0xd00
53 #define CPSW_SLIVER0_OFFSET 0xd80
54 #define CPSW_SLIVER1_OFFSET 0xdc0
55 #define CPSW_BD_OFFSET 0x2000
56 #define CPSW_MDIO_DIV 0xff
58 #define AM335X_GMII_SEL_OFFSET 0x630
61 #define CPDMA_TXCONTROL 0x004
62 #define CPDMA_RXCONTROL 0x014
63 #define CPDMA_SOFTRESET 0x01c
64 #define CPDMA_RXFREE 0x0e0
65 #define CPDMA_TXHDP_VER1 0x100
66 #define CPDMA_TXHDP_VER2 0x200
67 #define CPDMA_RXHDP_VER1 0x120
68 #define CPDMA_RXHDP_VER2 0x220
69 #define CPDMA_TXCP_VER1 0x140
70 #define CPDMA_TXCP_VER2 0x240
71 #define CPDMA_RXCP_VER1 0x160
72 #define CPDMA_RXCP_VER2 0x260
74 /* Descriptor mode bits */
75 #define CPDMA_DESC_SOP BIT(31)
76 #define CPDMA_DESC_EOP BIT(30)
77 #define CPDMA_DESC_OWNER BIT(29)
78 #define CPDMA_DESC_EOQ BIT(28)
81 * This timeout definition is a worst-case ultra defensive measure against
82 * unexpected controller lock ups. Ideally, we should never ever hit this
83 * scenario in practice.
85 #define MDIO_TIMEOUT 100 /* msecs */
86 #define CPDMA_TIMEOUT 100 /* msecs */
88 struct cpsw_mdio_regs {
91 #define CONTROL_IDLE BIT(31)
92 #define CONTROL_ENABLE BIT(30)
103 u32 __reserved_1[20];
108 #define USERACCESS_GO BIT(31)
109 #define USERACCESS_WRITE BIT(30)
110 #define USERACCESS_ACK BIT(29)
111 #define USERACCESS_READ (0)
112 #define USERACCESS_DATA (0xffff)
124 struct cpsw_slave_regs {
132 #elif defined(CONFIG_TI814X)
141 struct cpsw_host_regs {
147 u32 cpdma_tx_pri_map;
148 u32 cpdma_rx_chan_map;
151 struct cpsw_sliver_regs {
164 #define ALE_ENTRY_BITS 68
165 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
168 #define ALE_CONTROL 0x08
169 #define ALE_UNKNOWNVLAN 0x18
170 #define ALE_TABLE_CONTROL 0x20
171 #define ALE_TABLE 0x34
172 #define ALE_PORTCTL 0x40
174 #define ALE_TABLE_WRITE BIT(31)
176 #define ALE_TYPE_FREE 0
177 #define ALE_TYPE_ADDR 1
178 #define ALE_TYPE_VLAN 2
179 #define ALE_TYPE_VLAN_ADDR 3
181 #define ALE_UCAST_PERSISTANT 0
182 #define ALE_UCAST_UNTOUCHED 1
183 #define ALE_UCAST_OUI 2
184 #define ALE_UCAST_TOUCHED 3
186 #define ALE_MCAST_FWD 0
187 #define ALE_MCAST_BLOCK_LEARN_FWD 1
188 #define ALE_MCAST_FWD_LEARN 2
189 #define ALE_MCAST_FWD_2 3
191 enum cpsw_ale_port_state {
192 ALE_PORT_STATE_DISABLE = 0x00,
193 ALE_PORT_STATE_BLOCK = 0x01,
194 ALE_PORT_STATE_LEARN = 0x02,
195 ALE_PORT_STATE_FORWARD = 0x03,
198 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
200 #define ALE_BLOCKED 2
203 struct cpsw_slave_regs *regs;
204 struct cpsw_sliver_regs *sliver;
207 struct cpsw_slave_data *data;
211 /* hardware fields */
216 /* software fields */
222 struct cpdma_desc *head, *tail;
223 void *hdp, *cp, *rxfree;
226 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
227 #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
228 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
230 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
231 #define chan_read(chan, fld) __raw_readl((chan)->fld)
232 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
234 #define for_active_slave(slave, priv) \
235 slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
236 #define for_each_slave(slave, priv) \
237 for (slave = (priv)->slaves; slave != (priv)->slaves + \
238 (priv)->data.slaves; slave++)
244 struct eth_device *dev;
246 struct cpsw_platform_data data;
249 struct cpsw_regs *regs;
251 struct cpsw_host_regs *host_port_regs;
254 struct cpdma_desc *descs;
255 struct cpdma_desc *desc_free;
256 struct cpdma_chan rx_chan, tx_chan;
258 struct cpsw_slave *slaves;
259 struct phy_device *phydev;
265 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
271 idx = 2 - idx; /* flip */
272 return (ale_entry[idx] >> start) & BITMASK(bits);
275 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
280 value &= BITMASK(bits);
283 idx = 2 - idx; /* flip */
284 ale_entry[idx] &= ~(BITMASK(bits) << start);
285 ale_entry[idx] |= (value << start);
288 #define DEFINE_ALE_FIELD(name, start, bits) \
289 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
291 return cpsw_ale_get_field(ale_entry, start, bits); \
293 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
295 cpsw_ale_set_field(ale_entry, start, bits, value); \
298 DEFINE_ALE_FIELD(entry_type, 60, 2)
299 DEFINE_ALE_FIELD(mcast_state, 62, 2)
300 DEFINE_ALE_FIELD(port_mask, 66, 3)
301 DEFINE_ALE_FIELD(ucast_type, 62, 2)
302 DEFINE_ALE_FIELD(port_num, 66, 2)
303 DEFINE_ALE_FIELD(blocked, 65, 1)
304 DEFINE_ALE_FIELD(secure, 64, 1)
305 DEFINE_ALE_FIELD(mcast, 40, 1)
307 /* The MAC address field in the ALE entry cannot be macroized as above */
308 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
312 for (i = 0; i < 6; i++)
313 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
316 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
320 for (i = 0; i < 6; i++)
321 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
324 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
328 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
330 for (i = 0; i < ALE_ENTRY_WORDS; i++)
331 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
336 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
340 for (i = 0; i < ALE_ENTRY_WORDS; i++)
341 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
343 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
348 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
350 u32 ale_entry[ALE_ENTRY_WORDS];
353 for (idx = 0; idx < priv->data.ale_entries; idx++) {
356 cpsw_ale_read(priv, idx, ale_entry);
357 type = cpsw_ale_get_entry_type(ale_entry);
358 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
360 cpsw_ale_get_addr(ale_entry, entry_addr);
361 if (memcmp(entry_addr, addr, 6) == 0)
367 static int cpsw_ale_match_free(struct cpsw_priv *priv)
369 u32 ale_entry[ALE_ENTRY_WORDS];
372 for (idx = 0; idx < priv->data.ale_entries; idx++) {
373 cpsw_ale_read(priv, idx, ale_entry);
374 type = cpsw_ale_get_entry_type(ale_entry);
375 if (type == ALE_TYPE_FREE)
381 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
383 u32 ale_entry[ALE_ENTRY_WORDS];
386 for (idx = 0; idx < priv->data.ale_entries; idx++) {
387 cpsw_ale_read(priv, idx, ale_entry);
388 type = cpsw_ale_get_entry_type(ale_entry);
389 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
391 if (cpsw_ale_get_mcast(ale_entry))
393 type = cpsw_ale_get_ucast_type(ale_entry);
394 if (type != ALE_UCAST_PERSISTANT &&
395 type != ALE_UCAST_OUI)
401 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
404 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
407 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
408 cpsw_ale_set_addr(ale_entry, addr);
409 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
410 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
411 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
412 cpsw_ale_set_port_num(ale_entry, port);
414 idx = cpsw_ale_match_addr(priv, addr);
416 idx = cpsw_ale_match_free(priv);
418 idx = cpsw_ale_find_ageable(priv);
422 cpsw_ale_write(priv, idx, ale_entry);
426 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
429 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
432 idx = cpsw_ale_match_addr(priv, addr);
434 cpsw_ale_read(priv, idx, ale_entry);
436 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
437 cpsw_ale_set_addr(ale_entry, addr);
438 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
440 mask = cpsw_ale_get_port_mask(ale_entry);
442 cpsw_ale_set_port_mask(ale_entry, port_mask);
445 idx = cpsw_ale_match_free(priv);
447 idx = cpsw_ale_find_ageable(priv);
451 cpsw_ale_write(priv, idx, ale_entry);
455 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
457 u32 tmp, mask = BIT(bit);
459 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
461 tmp |= val ? mask : 0;
462 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
465 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
466 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
467 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
469 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
472 int offset = ALE_PORTCTL + 4 * port;
475 tmp = __raw_readl(priv->ale_regs + offset);
478 __raw_writel(tmp, priv->ale_regs + offset);
481 static struct cpsw_mdio_regs *mdio_regs;
483 /* wait until hardware is ready for another user access */
484 static inline u32 wait_for_user_access(void)
487 int timeout = MDIO_TIMEOUT;
490 ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO))
494 printf("wait_for_user_access Timeout\n");
500 /* wait until hardware state machine is idle */
501 static inline void wait_for_idle(void)
503 int timeout = MDIO_TIMEOUT;
506 ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0))
510 printf("wait_for_idle Timeout\n");
513 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
514 int dev_addr, int phy_reg)
519 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
522 wait_for_user_access();
523 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
525 __raw_writel(reg, &mdio_regs->user[0].access);
526 reg = wait_for_user_access();
528 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
532 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
533 int phy_reg, u16 data)
537 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
540 wait_for_user_access();
541 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
542 (phy_id << 16) | (data & USERACCESS_DATA));
543 __raw_writel(reg, &mdio_regs->user[0].access);
544 wait_for_user_access();
549 static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div)
551 struct mii_dev *bus = mdio_alloc();
553 mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
555 /* set enable and clock divider */
556 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
559 * wait for scan logic to settle:
560 * the scan time consists of (a) a large fixed component, and (b) a
561 * small component that varies with the mii bus frequency. These
562 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
563 * silicon. Since the effect of (b) was found to be largely
564 * negligible, we keep things simple here.
568 bus->read = cpsw_mdio_read;
569 bus->write = cpsw_mdio_write;
570 sprintf(bus->name, name);
575 /* Set a self-clearing bit in a register, and wait for it to clear */
576 static inline void setbit_and_wait_for_clear32(void *addr)
578 __raw_writel(CLEAR_BIT, addr);
579 while (__raw_readl(addr) & CLEAR_BIT)
583 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
584 ((mac)[2] << 16) | ((mac)[3] << 24))
585 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
587 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
588 struct cpsw_priv *priv)
591 struct eth_pdata *pdata = dev_get_platdata(priv->dev);
593 writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
594 writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
596 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
597 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
601 static void cpsw_slave_update_link(struct cpsw_slave *slave,
602 struct cpsw_priv *priv, int *link)
604 struct phy_device *phy;
615 if (*link) { /* link up */
616 mac_control = priv->data.mac_control;
617 if (phy->speed == 1000)
618 mac_control |= GIGABITEN;
619 if (phy->duplex == DUPLEX_FULL)
620 mac_control |= FULLDUPLEXEN;
621 if (phy->speed == 100)
622 mac_control |= MIIEN;
625 if (mac_control == slave->mac_control)
629 printf("link up on port %d, speed %d, %s duplex\n",
630 slave->slave_num, phy->speed,
631 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
633 printf("link down on port %d\n", slave->slave_num);
636 __raw_writel(mac_control, &slave->sliver->mac_control);
637 slave->mac_control = mac_control;
640 static int cpsw_update_link(struct cpsw_priv *priv)
643 struct cpsw_slave *slave;
645 for_active_slave(slave, priv)
646 cpsw_slave_update_link(slave, priv, &link);
651 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
653 if (priv->host_port == 0)
654 return slave_num + 1;
659 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
663 setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
665 /* setup priority mapping */
666 __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
667 __raw_writel(0x33221100, &slave->regs->tx_pri_map);
669 /* setup max packet size, and mac address */
670 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
671 cpsw_set_slave_mac(slave, priv);
673 slave->mac_control = 0; /* no link yet */
675 /* enable forwarding */
676 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
677 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
679 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
681 priv->phy_mask |= 1 << slave->data->phy_addr;
684 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
686 struct cpdma_desc *desc = priv->desc_free;
689 priv->desc_free = desc_read_ptr(desc, hw_next);
693 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
696 desc_write(desc, hw_next, priv->desc_free);
697 priv->desc_free = desc;
701 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
702 void *buffer, int len)
704 struct cpdma_desc *desc, *prev;
707 desc = cpdma_desc_alloc(priv);
714 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
716 desc_write(desc, hw_next, 0);
717 desc_write(desc, hw_buffer, buffer);
718 desc_write(desc, hw_len, len);
719 desc_write(desc, hw_mode, mode | len);
720 desc_write(desc, sw_buffer, buffer);
721 desc_write(desc, sw_len, len);
724 /* simple case - first packet enqueued */
727 chan_write(chan, hdp, desc);
731 /* not the first packet - enqueue at the tail */
733 desc_write(prev, hw_next, desc);
736 /* next check if EOQ has been triggered already */
737 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
738 chan_write(chan, hdp, desc);
742 chan_write(chan, rxfree, 1);
746 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
747 void **buffer, int *len)
749 struct cpdma_desc *desc = chan->head;
755 status = desc_read(desc, hw_mode);
758 *len = status & 0x7ff;
761 *buffer = desc_read_ptr(desc, sw_buffer);
763 if (status & CPDMA_DESC_OWNER) {
764 if (chan_read(chan, hdp) == 0) {
765 if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
766 chan_write(chan, hdp, desc);
772 chan->head = desc_read_ptr(desc, hw_next);
773 chan_write(chan, cp, desc);
775 cpdma_desc_free(priv, desc);
779 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
781 struct cpsw_slave *slave;
784 /* soft reset the controller and initialize priv */
785 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
787 /* initialize and reset the address lookup engine */
788 cpsw_ale_enable(priv, 1);
789 cpsw_ale_clear(priv, 1);
790 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
792 /* setup host port priority mapping */
793 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
794 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
796 /* disable priority elevation and enable statistics on all ports */
797 __raw_writel(0, &priv->regs->ptype);
799 /* enable statistics collection only on the host port */
800 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
801 __raw_writel(0x7, &priv->regs->stat_port_en);
803 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
805 cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
806 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
808 for_active_slave(slave, priv)
809 cpsw_slave_init(slave, priv);
811 cpsw_update_link(priv);
813 /* init descriptor pool */
814 for (i = 0; i < NUM_DESCS; i++) {
815 desc_write(&priv->descs[i], hw_next,
816 (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
818 priv->desc_free = &priv->descs[0];
820 /* initialize channels */
821 if (priv->data.version == CPSW_CTRL_VERSION_2) {
822 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
823 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
824 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
825 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
827 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
828 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
829 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
831 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
832 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
833 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
834 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
836 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
837 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
838 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
841 /* clear dma state */
842 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
844 if (priv->data.version == CPSW_CTRL_VERSION_2) {
845 for (i = 0; i < priv->data.channels; i++) {
846 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
848 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
850 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
852 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
854 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
858 for (i = 0; i < priv->data.channels; i++) {
859 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
861 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
863 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
865 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
867 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
873 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
874 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
876 /* submit rx descs */
877 for (i = 0; i < PKTBUFSRX; i++) {
878 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
881 printf("error %d submitting rx desc\n", ret);
889 static void _cpsw_halt(struct cpsw_priv *priv)
891 writel(0, priv->dma_regs + CPDMA_TXCONTROL);
892 writel(0, priv->dma_regs + CPDMA_RXCONTROL);
894 /* soft reset the controller and initialize priv */
895 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
897 /* clear dma state */
898 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
902 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
906 int timeout = CPDMA_TIMEOUT;
908 flush_dcache_range((unsigned long)packet,
909 (unsigned long)packet + length);
911 /* first reap completed packets */
913 (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0))
917 printf("cpdma_process timeout\n");
921 return cpdma_submit(priv, &priv->tx_chan, packet, length);
924 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
930 ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
934 invalidate_dcache_range((unsigned long)buffer,
935 (unsigned long)buffer + PKTSIZE_ALIGN);
941 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
942 struct cpsw_priv *priv)
944 void *regs = priv->regs;
945 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
946 slave->slave_num = slave_num;
948 slave->regs = regs + data->slave_reg_ofs;
949 slave->sliver = regs + data->sliver_reg_ofs;
952 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
954 struct phy_device *phydev;
955 u32 supported = PHY_GBIT_FEATURES;
957 phydev = phy_connect(priv->bus,
958 slave->data->phy_addr,
960 slave->data->phy_if);
965 phydev->supported &= supported;
966 phydev->advertising = phydev->supported;
968 priv->phydev = phydev;
974 int _cpsw_register(struct cpsw_priv *priv)
976 struct cpsw_slave *slave;
977 struct cpsw_platform_data *data = &priv->data;
978 void *regs = (void *)data->cpsw_base;
980 priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
985 priv->host_port = data->host_port_num;
987 priv->host_port_regs = regs + data->host_port_reg_ofs;
988 priv->dma_regs = regs + data->cpdma_reg_ofs;
989 priv->ale_regs = regs + data->ale_reg_ofs;
990 priv->descs = (void *)regs + data->bd_ram_ofs;
994 for_each_slave(slave, priv) {
995 cpsw_slave_setup(slave, idx, priv);
999 cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div);
1000 priv->bus = miiphy_get_dev_by_name(priv->dev->name);
1001 for_active_slave(slave, priv)
1002 cpsw_phy_init(priv, slave);
1007 #ifndef CONFIG_DM_ETH
1008 static int cpsw_init(struct eth_device *dev, bd_t *bis)
1010 struct cpsw_priv *priv = dev->priv;
1012 return _cpsw_init(priv, dev->enetaddr);
1015 static void cpsw_halt(struct eth_device *dev)
1017 struct cpsw_priv *priv = dev->priv;
1019 return _cpsw_halt(priv);
1022 static int cpsw_send(struct eth_device *dev, void *packet, int length)
1024 struct cpsw_priv *priv = dev->priv;
1026 return _cpsw_send(priv, packet, length);
1029 static int cpsw_recv(struct eth_device *dev)
1031 struct cpsw_priv *priv = dev->priv;
1035 len = _cpsw_recv(priv, &pkt);
1038 net_process_received_packet(pkt, len);
1039 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
1045 int cpsw_register(struct cpsw_platform_data *data)
1047 struct cpsw_priv *priv;
1048 struct eth_device *dev;
1051 dev = calloc(sizeof(*dev), 1);
1055 priv = calloc(sizeof(*priv), 1);
1064 strcpy(dev->name, "cpsw");
1066 dev->init = cpsw_init;
1067 dev->halt = cpsw_halt;
1068 dev->send = cpsw_send;
1069 dev->recv = cpsw_recv;
1074 ret = _cpsw_register(priv);
1076 eth_unregister(dev);
1085 static int cpsw_eth_start(struct udevice *dev)
1087 struct eth_pdata *pdata = dev_get_platdata(dev);
1088 struct cpsw_priv *priv = dev_get_priv(dev);
1090 return _cpsw_init(priv, pdata->enetaddr);
1093 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
1095 struct cpsw_priv *priv = dev_get_priv(dev);
1097 return _cpsw_send(priv, packet, length);
1100 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1102 struct cpsw_priv *priv = dev_get_priv(dev);
1104 return _cpsw_recv(priv, packetp);
1107 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
1110 struct cpsw_priv *priv = dev_get_priv(dev);
1112 return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
1115 static void cpsw_eth_stop(struct udevice *dev)
1117 struct cpsw_priv *priv = dev_get_priv(dev);
1119 return _cpsw_halt(priv);
1123 static int cpsw_eth_probe(struct udevice *dev)
1125 struct cpsw_priv *priv = dev_get_priv(dev);
1129 return _cpsw_register(priv);
1132 static const struct eth_ops cpsw_eth_ops = {
1133 .start = cpsw_eth_start,
1134 .send = cpsw_eth_send,
1135 .recv = cpsw_eth_recv,
1136 .free_pkt = cpsw_eth_free_pkt,
1137 .stop = cpsw_eth_stop,
1140 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
1142 struct eth_pdata *pdata = dev_get_platdata(dev);
1143 struct cpsw_priv *priv = dev_get_priv(dev);
1144 const char *phy_mode;
1145 const void *fdt = gd->fdt_blob;
1146 int node = dev->of_offset;
1148 int slave_index = 0;
1149 uint32_t mac_hi, mac_lo;
1153 pdata->iobase = dev_get_addr(dev);
1154 priv->data.version = CPSW_CTRL_VERSION_2;
1155 priv->data.bd_ram_ofs = CPSW_BD_OFFSET;
1156 priv->data.ale_reg_ofs = CPSW_ALE_OFFSET;
1157 priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1158 priv->data.mdio_div = CPSW_MDIO_DIV;
1159 priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1161 pdata->phy_interface = -1;
1163 priv->data.cpsw_base = pdata->iobase;
1164 priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1);
1165 if (priv->data.channels <= 0) {
1166 printf("error: cpdma_channels not found in dt\n");
1170 priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1);
1171 if (priv->data.slaves <= 0) {
1172 printf("error: slaves not found in dt\n");
1175 priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) *
1178 priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1);
1179 if (priv->data.ale_entries <= 0) {
1180 printf("error: ale_entries not found in dt\n");
1184 priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1);
1185 if (priv->data.bd_ram_ofs <= 0) {
1186 printf("error: bd_ram_size not found in dt\n");
1190 priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1);
1191 if (priv->data.mac_control <= 0) {
1192 printf("error: ale_entries not found in dt\n");
1196 active_slave = fdtdec_get_int(fdt, node, "active_slave", 0);
1197 priv->data.active_slave = active_slave;
1199 fdt_for_each_subnode(fdt, subnode, node) {
1203 name = fdt_get_name(fdt, subnode, &len);
1204 if (!strncmp(name, "mdio", 4)) {
1205 priv->data.mdio_base = fdtdec_get_addr(fdt, subnode,
1209 if (!strncmp(name, "slave", 5)) {
1212 if (slave_index >= priv->data.slaves) {
1213 printf("error: num slaves and slave nodes did not match\n");
1216 phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
1218 priv->data.slave_data[slave_index].phy_if =
1219 phy_get_interface_by_name(phy_mode);
1220 fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2);
1221 priv->data.slave_data[slave_index].phy_addr = phy_id[1];
1225 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1226 priv->data.gmii_sel = fdtdec_get_addr(fdt, subnode,
1231 priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1232 priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1234 if (priv->data.slaves == 2) {
1235 priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1236 priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1239 subnode = fdtdec_lookup_phandle(fdt, node, "syscon");
1240 priv->data.mac_id = fdt_translate_address((void *)fdt, subnode, &gmii);
1241 priv->data.mac_id += AM335X_GMII_SEL_OFFSET;
1242 priv->data.mac_id += active_slave * 8;
1244 /* try reading mac address from efuse */
1245 mac_lo = readl(priv->data.mac_id);
1246 mac_hi = readl(priv->data.mac_id + 4);
1247 pdata->enetaddr[0] = mac_hi & 0xFF;
1248 pdata->enetaddr[1] = (mac_hi & 0xFF00) >> 8;
1249 pdata->enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
1250 pdata->enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
1251 pdata->enetaddr[4] = mac_lo & 0xFF;
1252 pdata->enetaddr[5] = (mac_lo & 0xFF00) >> 8;
1254 pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
1255 if (pdata->phy_interface == -1) {
1256 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1259 switch (pdata->phy_interface) {
1260 case PHY_INTERFACE_MODE_MII:
1261 writel(MII_MODE_ENABLE, priv->data.gmii_sel);
1263 case PHY_INTERFACE_MODE_RMII:
1264 writel(RMII_MODE_ENABLE, priv->data.gmii_sel);
1266 case PHY_INTERFACE_MODE_RGMII:
1267 case PHY_INTERFACE_MODE_RGMII_ID:
1268 case PHY_INTERFACE_MODE_RGMII_RXID:
1269 case PHY_INTERFACE_MODE_RGMII_TXID:
1270 writel(RGMII_MODE_ENABLE, priv->data.gmii_sel);
1277 static const struct udevice_id cpsw_eth_ids[] = {
1278 { .compatible = "ti,cpsw" },
1279 { .compatible = "ti,am335x-cpsw" },
1283 U_BOOT_DRIVER(eth_cpsw) = {
1286 .of_match = cpsw_eth_ids,
1287 .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
1288 .probe = cpsw_eth_probe,
1289 .ops = &cpsw_eth_ops,
1290 .priv_auto_alloc_size = sizeof(struct cpsw_priv),
1291 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1292 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1294 #endif /* CONFIG_DM_ETH */