git.sur5r.net Git - u-boot/blob - drivers/net/cpsw.c

   1 /*
   2  * CPSW Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <common.h>
  17 #include <command.h>
  18 #include <net.h>
  19 #include <miiphy.h>
  20 #include <malloc.h>
  21 #include <net.h>
  22 #include <netdev.h>
  23 #include <cpsw.h>
  24 #include <linux/errno.h>
  25 #include <asm/gpio.h>
  26 #include <asm/io.h>
  27 #include <phy.h>
  28 #include <asm/arch/cpu.h>
  29 #include <dm.h>
  30 #include <fdt_support.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define BITMASK(bits)           (BIT(bits) - 1)
  35 #define PHY_REG_MASK            0x1f
  36 #define PHY_ID_MASK             0x1f
  37 #define NUM_DESCS               (PKTBUFSRX * 2)
  38 #define PKT_MIN                 60
  39 #define PKT_MAX                 (1500 + 14 + 4 + 4)
  40 #define CLEAR_BIT               1
  41 #define GIGABITEN               BIT(7)
  42 #define FULLDUPLEXEN            BIT(0)
  43 #define MIIEN                   BIT(15)
  44
  45 /* reg offset */
  46 #define CPSW_HOST_PORT_OFFSET   0x108
  47 #define CPSW_SLAVE0_OFFSET      0x208
  48 #define CPSW_SLAVE1_OFFSET      0x308
  49 #define CPSW_SLAVE_SIZE         0x100
  50 #define CPSW_CPDMA_OFFSET       0x800
  51 #define CPSW_HW_STATS           0x900
  52 #define CPSW_STATERAM_OFFSET    0xa00
  53 #define CPSW_CPTS_OFFSET        0xc00
  54 #define CPSW_ALE_OFFSET         0xd00
  55 #define CPSW_SLIVER0_OFFSET     0xd80
  56 #define CPSW_SLIVER1_OFFSET     0xdc0
  57 #define CPSW_BD_OFFSET          0x2000
  58 #define CPSW_MDIO_DIV           0xff
  59
  60 #define AM335X_GMII_SEL_OFFSET  0x630
  61
  62 /* DMA Registers */
  63 #define CPDMA_TXCONTROL         0x004
  64 #define CPDMA_RXCONTROL         0x014
  65 #define CPDMA_SOFTRESET         0x01c
  66 #define CPDMA_RXFREE            0x0e0
  67 #define CPDMA_TXHDP_VER1        0x100
  68 #define CPDMA_TXHDP_VER2        0x200
  69 #define CPDMA_RXHDP_VER1        0x120
  70 #define CPDMA_RXHDP_VER2        0x220
  71 #define CPDMA_TXCP_VER1         0x140
  72 #define CPDMA_TXCP_VER2         0x240
  73 #define CPDMA_RXCP_VER1         0x160
  74 #define CPDMA_RXCP_VER2         0x260
  75
  76 /* Descriptor mode bits */
  77 #define CPDMA_DESC_SOP          BIT(31)
  78 #define CPDMA_DESC_EOP          BIT(30)
  79 #define CPDMA_DESC_OWNER        BIT(29)
  80 #define CPDMA_DESC_EOQ          BIT(28)
  81
  82 /*
  83  * This timeout definition is a worst-case ultra defensive measure against
  84  * unexpected controller lock ups.  Ideally, we should never ever hit this
  85  * scenario in practice.
  86  */
  87 #define MDIO_TIMEOUT            100 /* msecs */
  88 #define CPDMA_TIMEOUT           100 /* msecs */
  89
  90 struct cpsw_mdio_regs {
  91         u32     version;
  92         u32     control;
  93 #define CONTROL_IDLE            BIT(31)
  94 #define CONTROL_ENABLE          BIT(30)
  95
  96         u32     alive;
  97         u32     link;
  98         u32     linkintraw;
  99         u32     linkintmasked;
 100         u32     __reserved_0[2];
 101         u32     userintraw;
 102         u32     userintmasked;
 103         u32     userintmaskset;
 104         u32     userintmaskclr;
 105         u32     __reserved_1[20];
 106
 107         struct {
 108                 u32             access;
 109                 u32             physel;
 110 #define USERACCESS_GO           BIT(31)
 111 #define USERACCESS_WRITE        BIT(30)
 112 #define USERACCESS_ACK          BIT(29)
 113 #define USERACCESS_READ         (0)
 114 #define USERACCESS_DATA         (0xffff)
 115         } user[0];
 116 };
 117
 118 struct cpsw_regs {
 119         u32     id_ver;
 120         u32     control;
 121         u32     soft_reset;
 122         u32     stat_port_en;
 123         u32     ptype;
 124 };
 125
 126 struct cpsw_slave_regs {
 127         u32     max_blks;
 128         u32     blk_cnt;
 129         u32     flow_thresh;
 130         u32     port_vlan;
 131         u32     tx_pri_map;
 132 #ifdef CONFIG_AM33XX
 133         u32     gap_thresh;
 134 #elif defined(CONFIG_TI814X)
 135         u32     ts_ctl;
 136         u32     ts_seq_ltype;
 137         u32     ts_vlan;
 138 #endif
 139         u32     sa_lo;
 140         u32     sa_hi;
 141 };
 142
 143 struct cpsw_host_regs {
 144         u32     max_blks;
 145         u32     blk_cnt;
 146         u32     flow_thresh;
 147         u32     port_vlan;
 148         u32     tx_pri_map;
 149         u32     cpdma_tx_pri_map;
 150         u32     cpdma_rx_chan_map;
 151 };
 152
 153 struct cpsw_sliver_regs {
 154         u32     id_ver;
 155         u32     mac_control;
 156         u32     mac_status;
 157         u32     soft_reset;
 158         u32     rx_maxlen;
 159         u32     __reserved_0;
 160         u32     rx_pause;
 161         u32     tx_pause;
 162         u32     __reserved_1;
 163         u32     rx_pri_map;
 164 };
 165
 166 #define ALE_ENTRY_BITS          68
 167 #define ALE_ENTRY_WORDS         DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
 168
 169 /* ALE Registers */
 170 #define ALE_CONTROL             0x08
 171 #define ALE_UNKNOWNVLAN         0x18
 172 #define ALE_TABLE_CONTROL       0x20
 173 #define ALE_TABLE               0x34
 174 #define ALE_PORTCTL             0x40
 175
 176 #define ALE_TABLE_WRITE         BIT(31)
 177
 178 #define ALE_TYPE_FREE                   0
 179 #define ALE_TYPE_ADDR                   1
 180 #define ALE_TYPE_VLAN                   2
 181 #define ALE_TYPE_VLAN_ADDR              3
 182
 183 #define ALE_UCAST_PERSISTANT            0
 184 #define ALE_UCAST_UNTOUCHED             1
 185 #define ALE_UCAST_OUI                   2
 186 #define ALE_UCAST_TOUCHED               3
 187
 188 #define ALE_MCAST_FWD                   0
 189 #define ALE_MCAST_BLOCK_LEARN_FWD       1
 190 #define ALE_MCAST_FWD_LEARN             2
 191 #define ALE_MCAST_FWD_2                 3
 192
 193 enum cpsw_ale_port_state {
 194         ALE_PORT_STATE_DISABLE  = 0x00,
 195         ALE_PORT_STATE_BLOCK    = 0x01,
 196         ALE_PORT_STATE_LEARN    = 0x02,
 197         ALE_PORT_STATE_FORWARD  = 0x03,
 198 };
 199
 200 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
 201 #define ALE_SECURE      1
 202 #define ALE_BLOCKED     2
 203
 204 struct cpsw_slave {
 205         struct cpsw_slave_regs          *regs;
 206         struct cpsw_sliver_regs         *sliver;
 207         int                             slave_num;
 208         u32                             mac_control;
 209         struct cpsw_slave_data          *data;
 210 };
 211
 212 struct cpdma_desc {
 213         /* hardware fields */
 214         u32                     hw_next;
 215         u32                     hw_buffer;
 216         u32                     hw_len;
 217         u32                     hw_mode;
 218         /* software fields */
 219         u32                     sw_buffer;
 220         u32                     sw_len;
 221 };
 222
 223 struct cpdma_chan {
 224         struct cpdma_desc       *head, *tail;
 225         void                    *hdp, *cp, *rxfree;
 226 };
 227
 228 /* AM33xx SoC specific definitions for the CONTROL port */
 229 #define AM33XX_GMII_SEL_MODE_MII        0
 230 #define AM33XX_GMII_SEL_MODE_RMII       1
 231 #define AM33XX_GMII_SEL_MODE_RGMII      2
 232
 233 #define AM33XX_GMII_SEL_RGMII1_IDMODE   BIT(4)
 234 #define AM33XX_GMII_SEL_RGMII2_IDMODE   BIT(5)
 235 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
 236 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
 237
 238 #define GMII_SEL_MODE_MASK              0x3
 239
 240 #define desc_write(desc, fld, val)      __raw_writel((u32)(val), &(desc)->fld)
 241 #define desc_read(desc, fld)            __raw_readl(&(desc)->fld)
 242 #define desc_read_ptr(desc, fld)        ((void *)__raw_readl(&(desc)->fld))
 243
 244 #define chan_write(chan, fld, val)      __raw_writel((u32)(val), (chan)->fld)
 245 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 246 #define chan_read_ptr(chan, fld)        ((void *)__raw_readl((chan)->fld))
 247
 248 #define for_active_slave(slave, priv) \
 249         slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
 250 #define for_each_slave(slave, priv) \
 251         for (slave = (priv)->slaves; slave != (priv)->slaves + \
 252                                 (priv)->data.slaves; slave++)
 253
 254 struct cpsw_priv {
 255 #ifdef CONFIG_DM_ETH
 256         struct udevice                  *dev;
 257 #else
 258         struct eth_device               *dev;
 259 #endif
 260         struct cpsw_platform_data       data;
 261         int                             host_port;
 262
 263         struct cpsw_regs                *regs;
 264         void                            *dma_regs;
 265         struct cpsw_host_regs           *host_port_regs;
 266         void                            *ale_regs;
 267
 268         struct cpdma_desc               *descs;
 269         struct cpdma_desc               *desc_free;
 270         struct cpdma_chan               rx_chan, tx_chan;
 271
 272         struct cpsw_slave               *slaves;
 273         struct phy_device               *phydev;
 274         struct mii_dev                  *bus;
 275
 276         u32                             phy_mask;
 277 };
 278
 279 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 280 {
 281         int idx;
 282
 283         idx    = start / 32;
 284         start -= idx * 32;
 285         idx    = 2 - idx; /* flip */
 286         return (ale_entry[idx] >> start) & BITMASK(bits);
 287 }
 288
 289 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 290                                       u32 value)
 291 {
 292         int idx;
 293
 294         value &= BITMASK(bits);
 295         idx    = start / 32;
 296         start -= idx * 32;
 297         idx    = 2 - idx; /* flip */
 298         ale_entry[idx] &= ~(BITMASK(bits) << start);
 299         ale_entry[idx] |=  (value << start);
 300 }
 301
 302 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 303 static inline int cpsw_ale_get_##name(u32 *ale_entry)                   \
 304 {                                                                       \
 305         return cpsw_ale_get_field(ale_entry, start, bits);              \
 306 }                                                                       \
 307 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)       \
 308 {                                                                       \
 309         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 310 }
 311
 312 DEFINE_ALE_FIELD(entry_type,            60,     2)
 313 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 314 DEFINE_ALE_FIELD(port_mask,             66,     3)
 315 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 316 DEFINE_ALE_FIELD(port_num,              66,     2)
 317 DEFINE_ALE_FIELD(blocked,               65,     1)
 318 DEFINE_ALE_FIELD(secure,                64,     1)
 319 DEFINE_ALE_FIELD(mcast,                 40,     1)
 320
 321 /* The MAC address field in the ALE entry cannot be macroized as above */
 322 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 323 {
 324         int i;
 325
 326         for (i = 0; i < 6; i++)
 327                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 328 }
 329
 330 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
 331 {
 332         int i;
 333
 334         for (i = 0; i < 6; i++)
 335                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 336 }
 337
 338 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 339 {
 340         int i;
 341
 342         __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
 343
 344         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 345                 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
 346
 347         return idx;
 348 }
 349
 350 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 351 {
 352         int i;
 353
 354         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 355                 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
 356
 357         __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
 358
 359         return idx;
 360 }
 361
 362 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
 363 {
 364         u32 ale_entry[ALE_ENTRY_WORDS];
 365         int type, idx;
 366
 367         for (idx = 0; idx < priv->data.ale_entries; idx++) {
 368                 u8 entry_addr[6];
 369
 370                 cpsw_ale_read(priv, idx, ale_entry);
 371                 type = cpsw_ale_get_entry_type(ale_entry);
 372                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 373                         continue;
 374                 cpsw_ale_get_addr(ale_entry, entry_addr);
 375                 if (memcmp(entry_addr, addr, 6) == 0)
 376                         return idx;
 377         }
 378         return -ENOENT;
 379 }
 380
 381 static int cpsw_ale_match_free(struct cpsw_priv *priv)
 382 {
 383         u32 ale_entry[ALE_ENTRY_WORDS];
 384         int type, idx;
 385
 386         for (idx = 0; idx < priv->data.ale_entries; idx++) {
 387                 cpsw_ale_read(priv, idx, ale_entry);
 388                 type = cpsw_ale_get_entry_type(ale_entry);
 389                 if (type == ALE_TYPE_FREE)
 390                         return idx;
 391         }
 392         return -ENOENT;
 393 }
 394
 395 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
 396 {
 397         u32 ale_entry[ALE_ENTRY_WORDS];
 398         int type, idx;
 399
 400         for (idx = 0; idx < priv->data.ale_entries; idx++) {
 401                 cpsw_ale_read(priv, idx, ale_entry);
 402                 type = cpsw_ale_get_entry_type(ale_entry);
 403                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 404                         continue;
 405                 if (cpsw_ale_get_mcast(ale_entry))
 406                         continue;
 407                 type = cpsw_ale_get_ucast_type(ale_entry);
 408                 if (type != ALE_UCAST_PERSISTANT &&
 409                     type != ALE_UCAST_OUI)
 410                         return idx;
 411         }
 412         return -ENOENT;
 413 }
 414
 415 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
 416                               int port, int flags)
 417 {
 418         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 419         int idx;
 420
 421         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 422         cpsw_ale_set_addr(ale_entry, addr);
 423         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 424         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 425         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 426         cpsw_ale_set_port_num(ale_entry, port);
 427
 428         idx = cpsw_ale_match_addr(priv, addr);
 429         if (idx < 0)
 430                 idx = cpsw_ale_match_free(priv);
 431         if (idx < 0)
 432                 idx = cpsw_ale_find_ageable(priv);
 433         if (idx < 0)
 434                 return -ENOMEM;
 435
 436         cpsw_ale_write(priv, idx, ale_entry);
 437         return 0;
 438 }
 439
 440 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
 441                               int port_mask)
 442 {
 443         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 444         int idx, mask;
 445
 446         idx = cpsw_ale_match_addr(priv, addr);
 447         if (idx >= 0)
 448                 cpsw_ale_read(priv, idx, ale_entry);
 449
 450         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 451         cpsw_ale_set_addr(ale_entry, addr);
 452         cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
 453
 454         mask = cpsw_ale_get_port_mask(ale_entry);
 455         port_mask |= mask;
 456         cpsw_ale_set_port_mask(ale_entry, port_mask);
 457
 458         if (idx < 0)
 459                 idx = cpsw_ale_match_free(priv);
 460         if (idx < 0)
 461                 idx = cpsw_ale_find_ageable(priv);
 462         if (idx < 0)
 463                 return -ENOMEM;
 464
 465         cpsw_ale_write(priv, idx, ale_entry);
 466         return 0;
 467 }
 468
 469 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
 470 {
 471         u32 tmp, mask = BIT(bit);
 472
 473         tmp  = __raw_readl(priv->ale_regs + ALE_CONTROL);
 474         tmp &= ~mask;
 475         tmp |= val ? mask : 0;
 476         __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
 477 }
 478
 479 #define cpsw_ale_enable(priv, val)      cpsw_ale_control(priv, 31, val)
 480 #define cpsw_ale_clear(priv, val)       cpsw_ale_control(priv, 30, val)
 481 #define cpsw_ale_vlan_aware(priv, val)  cpsw_ale_control(priv,  2, val)
 482
 483 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 484                                        int val)
 485 {
 486         int offset = ALE_PORTCTL + 4 * port;
 487         u32 tmp, mask = 0x3;
 488
 489         tmp  = __raw_readl(priv->ale_regs + offset);
 490         tmp &= ~mask;
 491         tmp |= val & mask;
 492         __raw_writel(tmp, priv->ale_regs + offset);
 493 }
 494
 495 static struct cpsw_mdio_regs *mdio_regs;
 496
 497 /* wait until hardware is ready for another user access */
 498 static inline u32 wait_for_user_access(void)
 499 {
 500         u32 reg = 0;
 501         int timeout = MDIO_TIMEOUT;
 502
 503         while (timeout-- &&
 504         ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO))
 505                 udelay(10);
 506
 507         if (timeout == -1) {
 508                 printf("wait_for_user_access Timeout\n");
 509                 return -ETIMEDOUT;
 510         }
 511         return reg;
 512 }
 513
 514 /* wait until hardware state machine is idle */
 515 static inline void wait_for_idle(void)
 516 {
 517         int timeout = MDIO_TIMEOUT;
 518
 519         while (timeout-- &&
 520                 ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0))
 521                 udelay(10);
 522
 523         if (timeout == -1)
 524                 printf("wait_for_idle Timeout\n");
 525 }
 526
 527 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
 528                                 int dev_addr, int phy_reg)
 529 {
 530         int data;
 531         u32 reg;
 532
 533         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 534                 return -EINVAL;
 535
 536         wait_for_user_access();
 537         reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
 538                (phy_id << 16));
 539         __raw_writel(reg, &mdio_regs->user[0].access);
 540         reg = wait_for_user_access();
 541
 542         data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
 543         return data;
 544 }
 545
 546 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
 547                                 int phy_reg, u16 data)
 548 {
 549         u32 reg;
 550
 551         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 552                 return -EINVAL;
 553
 554         wait_for_user_access();
 555         reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
 556                    (phy_id << 16) | (data & USERACCESS_DATA));
 557         __raw_writel(reg, &mdio_regs->user[0].access);
 558         wait_for_user_access();
 559
 560         return 0;
 561 }
 562
 563 static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div)
 564 {
 565         struct mii_dev *bus = mdio_alloc();
 566
 567         mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
 568
 569         /* set enable and clock divider */
 570         __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
 571
 572         /*
 573          * wait for scan logic to settle:
 574          * the scan time consists of (a) a large fixed component, and (b) a
 575          * small component that varies with the mii bus frequency.  These
 576          * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
 577          * silicon.  Since the effect of (b) was found to be largely
 578          * negligible, we keep things simple here.
 579          */
 580         udelay(1000);
 581
 582         bus->read = cpsw_mdio_read;
 583         bus->write = cpsw_mdio_write;
 584         strcpy(bus->name, name);
 585
 586         mdio_register(bus);
 587 }
 588
 589 /* Set a self-clearing bit in a register, and wait for it to clear */
 590 static inline void setbit_and_wait_for_clear32(void *addr)
 591 {
 592         __raw_writel(CLEAR_BIT, addr);
 593         while (__raw_readl(addr) & CLEAR_BIT)
 594                 ;
 595 }
 596
 597 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 598                          ((mac)[2] << 16) | ((mac)[3] << 24))
 599 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 600
 601 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 602                                struct cpsw_priv *priv)
 603 {
 604 #ifdef CONFIG_DM_ETH
 605         struct eth_pdata *pdata = dev_get_platdata(priv->dev);
 606
 607         writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
 608         writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
 609 #else
 610         __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
 611         __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
 612 #endif
 613 }
 614
 615 static void cpsw_slave_update_link(struct cpsw_slave *slave,
 616                                    struct cpsw_priv *priv, int *link)
 617 {
 618         struct phy_device *phy;
 619         u32 mac_control = 0;
 620
 621         phy = priv->phydev;
 622
 623         if (!phy)
 624                 return;
 625
 626         phy_startup(phy);
 627         *link = phy->link;
 628
 629         if (*link) { /* link up */
 630                 mac_control = priv->data.mac_control;
 631                 if (phy->speed == 1000)
 632                         mac_control |= GIGABITEN;
 633                 if (phy->duplex == DUPLEX_FULL)
 634                         mac_control |= FULLDUPLEXEN;
 635                 if (phy->speed == 100)
 636                         mac_control |= MIIEN;
 637         }
 638
 639         if (mac_control == slave->mac_control)
 640                 return;
 641
 642         if (mac_control) {
 643                 printf("link up on port %d, speed %d, %s duplex\n",
 644                                 slave->slave_num, phy->speed,
 645                                 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 646         } else {
 647                 printf("link down on port %d\n", slave->slave_num);
 648         }
 649
 650         __raw_writel(mac_control, &slave->sliver->mac_control);
 651         slave->mac_control = mac_control;
 652 }
 653
 654 static int cpsw_update_link(struct cpsw_priv *priv)
 655 {
 656         int link = 0;
 657         struct cpsw_slave *slave;
 658
 659         for_active_slave(slave, priv)
 660                 cpsw_slave_update_link(slave, priv, &link);
 661
 662         return link;
 663 }
 664
 665 static inline u32  cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 666 {
 667         if (priv->host_port == 0)
 668                 return slave_num + 1;
 669         else
 670                 return slave_num;
 671 }
 672
 673 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 674 {
 675         u32     slave_port;
 676
 677         setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
 678
 679         /* setup priority mapping */
 680         __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
 681         __raw_writel(0x33221100, &slave->regs->tx_pri_map);
 682
 683         /* setup max packet size, and mac address */
 684         __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
 685         cpsw_set_slave_mac(slave, priv);
 686
 687         slave->mac_control = 0; /* no link yet */
 688
 689         /* enable forwarding */
 690         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 691         cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
 692
 693         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
 694
 695         priv->phy_mask |= 1 << slave->data->phy_addr;
 696 }
 697
 698 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
 699 {
 700         struct cpdma_desc *desc = priv->desc_free;
 701
 702         if (desc)
 703                 priv->desc_free = desc_read_ptr(desc, hw_next);
 704         return desc;
 705 }
 706
 707 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
 708 {
 709         if (desc) {
 710                 desc_write(desc, hw_next, priv->desc_free);
 711                 priv->desc_free = desc;
 712         }
 713 }
 714
 715 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
 716                         void *buffer, int len)
 717 {
 718         struct cpdma_desc *desc, *prev;
 719         u32 mode;
 720
 721         desc = cpdma_desc_alloc(priv);
 722         if (!desc)
 723                 return -ENOMEM;
 724
 725         if (len < PKT_MIN)
 726                 len = PKT_MIN;
 727
 728         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 729
 730         desc_write(desc, hw_next,   0);
 731         desc_write(desc, hw_buffer, buffer);
 732         desc_write(desc, hw_len,    len);
 733         desc_write(desc, hw_mode,   mode | len);
 734         desc_write(desc, sw_buffer, buffer);
 735         desc_write(desc, sw_len,    len);
 736
 737         if (!chan->head) {
 738                 /* simple case - first packet enqueued */
 739                 chan->head = desc;
 740                 chan->tail = desc;
 741                 chan_write(chan, hdp, desc);
 742                 goto done;
 743         }
 744
 745         /* not the first packet - enqueue at the tail */
 746         prev = chan->tail;
 747         desc_write(prev, hw_next, desc);
 748         chan->tail = desc;
 749
 750         /* next check if EOQ has been triggered already */
 751         if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
 752                 chan_write(chan, hdp, desc);
 753
 754 done:
 755         if (chan->rxfree)
 756                 chan_write(chan, rxfree, 1);
 757         return 0;
 758 }
 759
 760 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
 761                          void **buffer, int *len)
 762 {
 763         struct cpdma_desc *desc = chan->head;
 764         u32 status;
 765
 766         if (!desc)
 767                 return -ENOENT;
 768
 769         status = desc_read(desc, hw_mode);
 770
 771         if (len)
 772                 *len = status & 0x7ff;
 773
 774         if (buffer)
 775                 *buffer = desc_read_ptr(desc, sw_buffer);
 776
 777         if (status & CPDMA_DESC_OWNER) {
 778                 if (chan_read(chan, hdp) == 0) {
 779                         if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
 780                                 chan_write(chan, hdp, desc);
 781                 }
 782
 783                 return -EBUSY;
 784         }
 785
 786         chan->head = desc_read_ptr(desc, hw_next);
 787         chan_write(chan, cp, desc);
 788
 789         cpdma_desc_free(priv, desc);
 790         return 0;
 791 }
 792
 793 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
 794 {
 795         struct cpsw_slave       *slave;
 796         int i, ret;
 797
 798         /* soft reset the controller and initialize priv */
 799         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 800
 801         /* initialize and reset the address lookup engine */
 802         cpsw_ale_enable(priv, 1);
 803         cpsw_ale_clear(priv, 1);
 804         cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
 805
 806         /* setup host port priority mapping */
 807         __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
 808         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 809
 810         /* disable priority elevation and enable statistics on all ports */
 811         __raw_writel(0, &priv->regs->ptype);
 812
 813         /* enable statistics collection only on the host port */
 814         __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
 815         __raw_writel(0x7, &priv->regs->stat_port_en);
 816
 817         cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 818
 819         cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
 820         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
 821
 822         for_active_slave(slave, priv)
 823                 cpsw_slave_init(slave, priv);
 824
 825         cpsw_update_link(priv);
 826
 827         /* init descriptor pool */
 828         for (i = 0; i < NUM_DESCS; i++) {
 829                 desc_write(&priv->descs[i], hw_next,
 830                            (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
 831         }
 832         priv->desc_free = &priv->descs[0];
 833
 834         /* initialize channels */
 835         if (priv->data.version == CPSW_CTRL_VERSION_2) {
 836                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 837                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER2;
 838                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER2;
 839                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 840
 841                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 842                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER2;
 843                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER2;
 844         } else {
 845                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 846                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER1;
 847                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER1;
 848                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 849
 850                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 851                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER1;
 852                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER1;
 853         }
 854
 855         /* clear dma state */
 856         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 857
 858         if (priv->data.version == CPSW_CTRL_VERSION_2) {
 859                 for (i = 0; i < priv->data.channels; i++) {
 860                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
 861                                         * i);
 862                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 863                                         * i);
 864                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
 865                                         * i);
 866                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
 867                                         * i);
 868                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
 869                                         * i);
 870                 }
 871         } else {
 872                 for (i = 0; i < priv->data.channels; i++) {
 873                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
 874                                         * i);
 875                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 876                                         * i);
 877                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
 878                                         * i);
 879                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
 880                                         * i);
 881                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
 882                                         * i);
 883
 884                 }
 885         }
 886
 887         __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
 888         __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
 889
 890         /* submit rx descs */
 891         for (i = 0; i < PKTBUFSRX; i++) {
 892                 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
 893                                    PKTSIZE);
 894                 if (ret < 0) {
 895                         printf("error %d submitting rx desc\n", ret);
 896                         break;
 897                 }
 898         }
 899
 900         return 0;
 901 }
 902
 903 static void _cpsw_halt(struct cpsw_priv *priv)
 904 {
 905         writel(0, priv->dma_regs + CPDMA_TXCONTROL);
 906         writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 907
 908         /* soft reset the controller and initialize priv */
 909         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 910
 911         /* clear dma state */
 912         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 913
 914 }
 915
 916 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 917 {
 918         void *buffer;
 919         int len;
 920         int timeout = CPDMA_TIMEOUT;
 921
 922         flush_dcache_range((unsigned long)packet,
 923                            (unsigned long)packet + ALIGN(length, PKTALIGN));
 924
 925         /* first reap completed packets */
 926         while (timeout-- &&
 927                 (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0))
 928                 ;
 929
 930         if (timeout == -1) {
 931                 printf("cpdma_process timeout\n");
 932                 return -ETIMEDOUT;
 933         }
 934
 935         return cpdma_submit(priv, &priv->tx_chan, packet, length);
 936 }
 937
 938 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
 939 {
 940         void *buffer;
 941         int len;
 942         int ret = -EAGAIN;
 943
 944         ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
 945         if (ret < 0)
 946                 return ret;
 947
 948         invalidate_dcache_range((unsigned long)buffer,
 949                                 (unsigned long)buffer + PKTSIZE_ALIGN);
 950         *pkt = buffer;
 951
 952         return len;
 953 }
 954
 955 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
 956                             struct cpsw_priv *priv)
 957 {
 958         void                    *regs = priv->regs;
 959         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
 960         slave->slave_num = slave_num;
 961         slave->data     = data;
 962         slave->regs     = regs + data->slave_reg_ofs;
 963         slave->sliver   = regs + data->sliver_reg_ofs;
 964 }
 965
 966 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 967 {
 968         struct phy_device *phydev;
 969         u32 supported = PHY_GBIT_FEATURES;
 970
 971         phydev = phy_connect(priv->bus,
 972                         slave->data->phy_addr,
 973                         priv->dev,
 974                         slave->data->phy_if);
 975
 976         if (!phydev)
 977                 return -1;
 978
 979         phydev->supported &= supported;
 980         phydev->advertising = phydev->supported;
 981
 982 #ifdef CONFIG_DM_ETH
 983         if (slave->data->phy_of_handle)
 984                 phydev->dev->of_offset = slave->data->phy_of_handle;
 985 #endif
 986
 987         priv->phydev = phydev;
 988         phy_config(phydev);
 989
 990         return 1;
 991 }
 992
 993 int _cpsw_register(struct cpsw_priv *priv)
 994 {
 995         struct cpsw_slave       *slave;
 996         struct cpsw_platform_data *data = &priv->data;
 997         void                    *regs = (void *)data->cpsw_base;
 998
 999         priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
1000         if (!priv->slaves) {
1001                 return -ENOMEM;
1002         }
1003
1004         priv->host_port         = data->host_port_num;
1005         priv->regs              = regs;
1006         priv->host_port_regs    = regs + data->host_port_reg_ofs;
1007         priv->dma_regs          = regs + data->cpdma_reg_ofs;
1008         priv->ale_regs          = regs + data->ale_reg_ofs;
1009         priv->descs             = (void *)regs + data->bd_ram_ofs;
1010
1011         int idx = 0;
1012
1013         for_each_slave(slave, priv) {
1014                 cpsw_slave_setup(slave, idx, priv);
1015                 idx = idx + 1;
1016         }
1017
1018         cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div);
1019         priv->bus = miiphy_get_dev_by_name(priv->dev->name);
1020         for_active_slave(slave, priv)
1021                 cpsw_phy_init(priv, slave);
1022
1023         return 0;
1024 }
1025
1026 #ifndef CONFIG_DM_ETH
1027 static int cpsw_init(struct eth_device *dev, bd_t *bis)
1028 {
1029         struct cpsw_priv        *priv = dev->priv;
1030
1031         return _cpsw_init(priv, dev->enetaddr);
1032 }
1033
1034 static void cpsw_halt(struct eth_device *dev)
1035 {
1036         struct cpsw_priv *priv = dev->priv;
1037
1038         return _cpsw_halt(priv);
1039 }
1040
1041 static int cpsw_send(struct eth_device *dev, void *packet, int length)
1042 {
1043         struct cpsw_priv        *priv = dev->priv;
1044
1045         return _cpsw_send(priv, packet, length);
1046 }
1047
1048 static int cpsw_recv(struct eth_device *dev)
1049 {
1050         struct cpsw_priv *priv = dev->priv;
1051         uchar *pkt = NULL;
1052         int len;
1053
1054         len = _cpsw_recv(priv, &pkt);
1055
1056         if (len > 0) {
1057                 net_process_received_packet(pkt, len);
1058                 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
1059         }
1060
1061         return len;
1062 }
1063
1064 int cpsw_register(struct cpsw_platform_data *data)
1065 {
1066         struct cpsw_priv        *priv;
1067         struct eth_device       *dev;
1068         int ret;
1069
1070         dev = calloc(sizeof(*dev), 1);
1071         if (!dev)
1072                 return -ENOMEM;
1073
1074         priv = calloc(sizeof(*priv), 1);
1075         if (!priv) {
1076                 free(dev);
1077                 return -ENOMEM;
1078         }
1079
1080         priv->dev = dev;
1081         priv->data = *data;
1082
1083         strcpy(dev->name, "cpsw");
1084         dev->iobase     = 0;
1085         dev->init       = cpsw_init;
1086         dev->halt       = cpsw_halt;
1087         dev->send       = cpsw_send;
1088         dev->recv       = cpsw_recv;
1089         dev->priv       = priv;
1090
1091         eth_register(dev);
1092
1093         ret = _cpsw_register(priv);
1094         if (ret < 0) {
1095                 eth_unregister(dev);
1096                 free(dev);
1097                 free(priv);
1098                 return ret;
1099         }
1100
1101         return 1;
1102 }
1103 #else
1104 static int cpsw_eth_start(struct udevice *dev)
1105 {
1106         struct eth_pdata *pdata = dev_get_platdata(dev);
1107         struct cpsw_priv *priv = dev_get_priv(dev);
1108
1109         return _cpsw_init(priv, pdata->enetaddr);
1110 }
1111
1112 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
1113 {
1114         struct cpsw_priv *priv = dev_get_priv(dev);
1115
1116         return _cpsw_send(priv, packet, length);
1117 }
1118
1119 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1120 {
1121         struct cpsw_priv *priv = dev_get_priv(dev);
1122
1123         return _cpsw_recv(priv, packetp);
1124 }
1125
1126 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
1127                                    int length)
1128 {
1129         struct cpsw_priv *priv = dev_get_priv(dev);
1130
1131         return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
1132 }
1133
1134 static void cpsw_eth_stop(struct udevice *dev)
1135 {
1136         struct cpsw_priv *priv = dev_get_priv(dev);
1137
1138         return _cpsw_halt(priv);
1139 }
1140
1141
1142 static int cpsw_eth_probe(struct udevice *dev)
1143 {
1144         struct cpsw_priv *priv = dev_get_priv(dev);
1145
1146         priv->dev = dev;
1147
1148         return _cpsw_register(priv);
1149 }
1150
1151 static const struct eth_ops cpsw_eth_ops = {
1152         .start          = cpsw_eth_start,
1153         .send           = cpsw_eth_send,
1154         .recv           = cpsw_eth_recv,
1155         .free_pkt       = cpsw_eth_free_pkt,
1156         .stop           = cpsw_eth_stop,
1157 };
1158
1159 static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
1160 {
1161         return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL,
1162                                                   false);
1163 }
1164
1165 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
1166                                  phy_interface_t phy_mode)
1167 {
1168         u32 reg;
1169         u32 mask;
1170         u32 mode = 0;
1171         bool rgmii_id = false;
1172         int slave = priv->data.active_slave;
1173
1174         reg = readl(priv->data.gmii_sel);
1175
1176         switch (phy_mode) {
1177         case PHY_INTERFACE_MODE_RMII:
1178                 mode = AM33XX_GMII_SEL_MODE_RMII;
1179                 break;
1180
1181         case PHY_INTERFACE_MODE_RGMII:
1182                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1183                 break;
1184         case PHY_INTERFACE_MODE_RGMII_ID:
1185         case PHY_INTERFACE_MODE_RGMII_RXID:
1186         case PHY_INTERFACE_MODE_RGMII_TXID:
1187                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1188                 rgmii_id = true;
1189                 break;
1190
1191         case PHY_INTERFACE_MODE_MII:
1192         default:
1193                 mode = AM33XX_GMII_SEL_MODE_MII;
1194                 break;
1195         };
1196
1197         mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
1198         mode <<= slave * 2;
1199
1200         if (priv->data.rmii_clock_external) {
1201                 if (slave == 0)
1202                         mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
1203                 else
1204                         mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
1205         }
1206
1207         if (rgmii_id) {
1208                 if (slave == 0)
1209                         mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
1210                 else
1211                         mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
1212         }
1213
1214         reg &= ~mask;
1215         reg |= mode;
1216
1217         writel(reg, priv->data.gmii_sel);
1218 }
1219
1220 static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
1221                                  phy_interface_t phy_mode)
1222 {
1223         u32 reg;
1224         u32 mask;
1225         u32 mode = 0;
1226         int slave = priv->data.active_slave;
1227
1228         reg = readl(priv->data.gmii_sel);
1229
1230         switch (phy_mode) {
1231         case PHY_INTERFACE_MODE_RMII:
1232                 mode = AM33XX_GMII_SEL_MODE_RMII;
1233                 break;
1234
1235         case PHY_INTERFACE_MODE_RGMII:
1236         case PHY_INTERFACE_MODE_RGMII_ID:
1237         case PHY_INTERFACE_MODE_RGMII_RXID:
1238         case PHY_INTERFACE_MODE_RGMII_TXID:
1239                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1240                 break;
1241
1242         case PHY_INTERFACE_MODE_MII:
1243         default:
1244                 mode = AM33XX_GMII_SEL_MODE_MII;
1245                 break;
1246         };
1247
1248         switch (slave) {
1249         case 0:
1250                 mask = GMII_SEL_MODE_MASK;
1251                 break;
1252         case 1:
1253                 mask = GMII_SEL_MODE_MASK << 4;
1254                 mode <<= 4;
1255                 break;
1256         default:
1257                 dev_err(priv->dev, "invalid slave number...\n");
1258                 return;
1259         }
1260
1261         if (priv->data.rmii_clock_external)
1262                 dev_err(priv->dev, "RMII External clock is not supported\n");
1263
1264         reg &= ~mask;
1265         reg |= mode;
1266
1267         writel(reg, priv->data.gmii_sel);
1268 }
1269
1270 static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
1271                          phy_interface_t phy_mode)
1272 {
1273         if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
1274                 cpsw_gmii_sel_am3352(priv, phy_mode);
1275         if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
1276                 cpsw_gmii_sel_am3352(priv, phy_mode);
1277         else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
1278                 cpsw_gmii_sel_dra7xx(priv, phy_mode);
1279 }
1280
1281 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
1282 {
1283         struct eth_pdata *pdata = dev_get_platdata(dev);
1284         struct cpsw_priv *priv = dev_get_priv(dev);
1285         struct gpio_desc *mode_gpios;
1286         const char *phy_mode;
1287         const char *phy_sel_compat = NULL;
1288         const void *fdt = gd->fdt_blob;
1289         int node = dev->of_offset;
1290         int subnode;
1291         int slave_index = 0;
1292         int active_slave;
1293         int num_mode_gpios;
1294         int ret;
1295
1296         pdata->iobase = dev_get_addr(dev);
1297         priv->data.version = CPSW_CTRL_VERSION_2;
1298         priv->data.bd_ram_ofs = CPSW_BD_OFFSET;
1299         priv->data.ale_reg_ofs = CPSW_ALE_OFFSET;
1300         priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1301         priv->data.mdio_div = CPSW_MDIO_DIV;
1302         priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1303
1304         pdata->phy_interface = -1;
1305
1306         priv->data.cpsw_base = pdata->iobase;
1307         priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1);
1308         if (priv->data.channels <= 0) {
1309                 printf("error: cpdma_channels not found in dt\n");
1310                 return -ENOENT;
1311         }
1312
1313         priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1);
1314         if (priv->data.slaves <= 0) {
1315                 printf("error: slaves not found in dt\n");
1316                 return -ENOENT;
1317         }
1318         priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) *
1319                                        priv->data.slaves);
1320
1321         priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1);
1322         if (priv->data.ale_entries <= 0) {
1323                 printf("error: ale_entries not found in dt\n");
1324                 return -ENOENT;
1325         }
1326
1327         priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1);
1328         if (priv->data.bd_ram_ofs <= 0) {
1329                 printf("error: bd_ram_size not found in dt\n");
1330                 return -ENOENT;
1331         }
1332
1333         priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1);
1334         if (priv->data.mac_control <= 0) {
1335                 printf("error: ale_entries not found in dt\n");
1336                 return -ENOENT;
1337         }
1338
1339         num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
1340         if (num_mode_gpios > 0) {
1341                 mode_gpios = malloc(sizeof(struct gpio_desc) *
1342                                     num_mode_gpios);
1343                 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
1344                                           num_mode_gpios, GPIOD_IS_OUT);
1345                 free(mode_gpios);
1346         }
1347
1348         active_slave = fdtdec_get_int(fdt, node, "active_slave", 0);
1349         priv->data.active_slave = active_slave;
1350
1351         fdt_for_each_subnode(subnode, fdt, node) {
1352                 int len;
1353                 const char *name;
1354
1355                 name = fdt_get_name(fdt, subnode, &len);
1356                 if (!strncmp(name, "mdio", 4)) {
1357                         u32 mdio_base;
1358
1359                         mdio_base = cpsw_get_addr_by_node(fdt, subnode);
1360                         if (mdio_base == FDT_ADDR_T_NONE) {
1361                                 error("Not able to get MDIO address space\n");
1362                                 return -ENOENT;
1363                         }
1364                         priv->data.mdio_base = mdio_base;
1365                 }
1366
1367                 if (!strncmp(name, "slave", 5)) {
1368                         u32 phy_id[2];
1369
1370                         if (slave_index >= priv->data.slaves)
1371                                 continue;
1372                         phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
1373                         if (phy_mode)
1374                                 priv->data.slave_data[slave_index].phy_if =
1375                                         phy_get_interface_by_name(phy_mode);
1376
1377                         priv->data.slave_data[slave_index].phy_of_handle =
1378                                 fdtdec_lookup_phandle(fdt, subnode,
1379                                                       "phy-handle");
1380
1381                         if (priv->data.slave_data[slave_index].phy_of_handle >= 0) {
1382                                 priv->data.slave_data[slave_index].phy_addr =
1383                                                 fdtdec_get_int(gd->fdt_blob,
1384                                                                priv->data.slave_data[slave_index].phy_of_handle,
1385                                                                "reg", -1);
1386                         } else {
1387                                 fdtdec_get_int_array(fdt, subnode, "phy_id",
1388                                                      phy_id, 2);
1389                                 priv->data.slave_data[slave_index].phy_addr =
1390                                                 phy_id[1];
1391                         }
1392                         slave_index++;
1393                 }
1394
1395                 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1396                         priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
1397                                                                     subnode);
1398
1399                         if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
1400                                 error("Not able to get gmii_sel reg address\n");
1401                                 return -ENOENT;
1402                         }
1403
1404                         if (fdt_get_property(fdt, subnode, "rmii-clock-ext",
1405                                              NULL))
1406                                 priv->data.rmii_clock_external = true;
1407
1408                         phy_sel_compat = fdt_getprop(fdt, subnode, "compatible",
1409                                                      NULL);
1410                         if (!phy_sel_compat) {
1411                                 error("Not able to get gmii_sel compatible\n");
1412                                 return -ENOENT;
1413                         }
1414                 }
1415         }
1416
1417         priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1418         priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1419
1420         if (priv->data.slaves == 2) {
1421                 priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1422                 priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1423         }
1424
1425         ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr);
1426         if (ret < 0) {
1427                 error("cpsw read efuse mac failed\n");
1428                 return ret;
1429         }
1430
1431         pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
1432         if (pdata->phy_interface == -1) {
1433                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1434                 return -EINVAL;
1435         }
1436
1437         /* Select phy interface in control module */
1438         cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface);
1439
1440         return 0;
1441 }
1442
1443
1444 static const struct udevice_id cpsw_eth_ids[] = {
1445         { .compatible = "ti,cpsw" },
1446         { .compatible = "ti,am335x-cpsw" },
1447         { }
1448 };
1449
1450 U_BOOT_DRIVER(eth_cpsw) = {
1451         .name   = "eth_cpsw",
1452         .id     = UCLASS_ETH,
1453         .of_match = cpsw_eth_ids,
1454         .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
1455         .probe  = cpsw_eth_probe,
1456         .ops    = &cpsw_eth_ops,
1457         .priv_auto_alloc_size = sizeof(struct cpsw_priv),
1458         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1459         .flags = DM_FLAG_ALLOC_PRIV_DMA,
1460 };
1461 #endif /* CONFIG_DM_ETH */