1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
8 * Designware ethernet IP driver for U-Boot
18 #include <linux/compiler.h>
19 #include <linux/err.h>
20 #include <linux/kernel.h>
22 #include <power/regulator.h>
23 #include "designware.h"
25 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
28 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
29 struct eth_mac_regs *mac_p = priv->mac_regs_p;
31 struct eth_mac_regs *mac_p = bus->priv;
35 int timeout = CONFIG_MDIO_TIMEOUT;
37 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
38 ((reg << MIIREGSHIFT) & MII_REGMSK);
40 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
43 while (get_timer(start) < timeout) {
44 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
45 return readl(&mac_p->miidata);
52 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
56 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
57 struct eth_mac_regs *mac_p = priv->mac_regs_p;
59 struct eth_mac_regs *mac_p = bus->priv;
63 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
65 writel(val, &mac_p->miidata);
66 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
67 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
69 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
72 while (get_timer(start) < timeout) {
73 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
83 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
84 static int dw_mdio_reset(struct mii_dev *bus)
86 struct udevice *dev = bus->priv;
87 struct dw_eth_dev *priv = dev_get_priv(dev);
88 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
91 if (!dm_gpio_is_valid(&priv->reset_gpio))
95 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
99 udelay(pdata->reset_delays[0]);
101 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
105 udelay(pdata->reset_delays[1]);
107 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
111 udelay(pdata->reset_delays[2]);
117 static int dw_mdio_init(const char *name, void *priv)
119 struct mii_dev *bus = mdio_alloc();
122 printf("Failed to allocate MDIO bus\n");
126 bus->read = dw_mdio_read;
127 bus->write = dw_mdio_write;
128 snprintf(bus->name, sizeof(bus->name), "%s", name);
129 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
130 bus->reset = dw_mdio_reset;
135 return mdio_register(bus);
138 static void tx_descs_init(struct dw_eth_dev *priv)
140 struct eth_dma_regs *dma_p = priv->dma_regs_p;
141 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
142 char *txbuffs = &priv->txbuffs[0];
143 struct dmamacdescr *desc_p;
146 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
147 desc_p = &desc_table_p[idx];
148 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
149 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
151 #if defined(CONFIG_DW_ALTDESCRIPTOR)
152 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
153 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
154 DESC_TXSTS_TXCHECKINSCTRL |
155 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
157 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
158 desc_p->dmamac_cntl = 0;
159 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
161 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
162 desc_p->txrx_status = 0;
166 /* Correcting the last pointer of the chain */
167 desc_p->dmamac_next = (ulong)&desc_table_p[0];
169 /* Flush all Tx buffer descriptors at once */
170 flush_dcache_range((ulong)priv->tx_mac_descrtable,
171 (ulong)priv->tx_mac_descrtable +
172 sizeof(priv->tx_mac_descrtable));
174 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
175 priv->tx_currdescnum = 0;
178 static void rx_descs_init(struct dw_eth_dev *priv)
180 struct eth_dma_regs *dma_p = priv->dma_regs_p;
181 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
182 char *rxbuffs = &priv->rxbuffs[0];
183 struct dmamacdescr *desc_p;
186 /* Before passing buffers to GMAC we need to make sure zeros
187 * written there right after "priv" structure allocation were
189 * Otherwise there's a chance to get some of them flushed in RAM when
190 * GMAC is already pushing data to RAM via DMA. This way incoming from
191 * GMAC data will be corrupted. */
192 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
194 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
195 desc_p = &desc_table_p[idx];
196 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
197 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
199 desc_p->dmamac_cntl =
200 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
203 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
206 /* Correcting the last pointer of the chain */
207 desc_p->dmamac_next = (ulong)&desc_table_p[0];
209 /* Flush all Rx buffer descriptors at once */
210 flush_dcache_range((ulong)priv->rx_mac_descrtable,
211 (ulong)priv->rx_mac_descrtable +
212 sizeof(priv->rx_mac_descrtable));
214 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
215 priv->rx_currdescnum = 0;
218 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
220 struct eth_mac_regs *mac_p = priv->mac_regs_p;
221 u32 macid_lo, macid_hi;
223 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
225 macid_hi = mac_id[4] + (mac_id[5] << 8);
227 writel(macid_hi, &mac_p->macaddr0hi);
228 writel(macid_lo, &mac_p->macaddr0lo);
233 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
234 struct phy_device *phydev)
236 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
239 printf("%s: No link.\n", phydev->dev->name);
243 if (phydev->speed != 1000)
244 conf |= MII_PORTSELECT;
246 conf &= ~MII_PORTSELECT;
248 if (phydev->speed == 100)
252 conf |= FULLDPLXMODE;
254 writel(conf, &mac_p->conf);
256 printf("Speed: %d, %s duplex%s\n", phydev->speed,
257 (phydev->duplex) ? "full" : "half",
258 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
263 static void _dw_eth_halt(struct dw_eth_dev *priv)
265 struct eth_mac_regs *mac_p = priv->mac_regs_p;
266 struct eth_dma_regs *dma_p = priv->dma_regs_p;
268 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
269 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
271 phy_shutdown(priv->phydev);
274 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
276 struct eth_mac_regs *mac_p = priv->mac_regs_p;
277 struct eth_dma_regs *dma_p = priv->dma_regs_p;
281 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
284 * When a MII PHY is used, we must set the PS bit for the DMA
287 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
288 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
290 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
292 start = get_timer(0);
293 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
294 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
295 printf("DMA reset timeout\n");
303 * Soft reset above clears HW address registers.
304 * So we have to set it here once again.
306 _dw_write_hwaddr(priv, enetaddr);
311 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
313 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
314 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
317 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
321 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
323 #ifdef CONFIG_DW_AXI_BURST_LEN
324 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
327 /* Start up the PHY */
328 ret = phy_startup(priv->phydev);
330 printf("Could not initialize PHY %s\n",
331 priv->phydev->dev->name);
335 ret = dw_adjust_link(priv, mac_p, priv->phydev);
342 int designware_eth_enable(struct dw_eth_dev *priv)
344 struct eth_mac_regs *mac_p = priv->mac_regs_p;
346 if (!priv->phydev->link)
349 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
356 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
358 struct eth_dma_regs *dma_p = priv->dma_regs_p;
359 u32 desc_num = priv->tx_currdescnum;
360 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
361 ulong desc_start = (ulong)desc_p;
362 ulong desc_end = desc_start +
363 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
364 ulong data_start = desc_p->dmamac_addr;
365 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
367 * Strictly we only need to invalidate the "txrx_status" field
368 * for the following check, but on some platforms we cannot
369 * invalidate only 4 bytes, so we flush the entire descriptor,
370 * which is 16 bytes in total. This is safe because the
371 * individual descriptors in the array are each aligned to
372 * ARCH_DMA_MINALIGN and padded appropriately.
374 invalidate_dcache_range(desc_start, desc_end);
376 /* Check if the descriptor is owned by CPU */
377 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
378 printf("CPU not owner of tx frame\n");
382 length = max(length, ETH_ZLEN);
384 memcpy((void *)data_start, packet, length);
386 /* Flush data to be sent */
387 flush_dcache_range(data_start, data_end);
389 #if defined(CONFIG_DW_ALTDESCRIPTOR)
390 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
391 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
392 DESC_TXCTRL_SIZE1MASK;
394 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
395 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
397 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
398 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
401 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
404 /* Flush modified buffer descriptor */
405 flush_dcache_range(desc_start, desc_end);
407 /* Test the wrap-around condition. */
408 if (++desc_num >= CONFIG_TX_DESCR_NUM)
411 priv->tx_currdescnum = desc_num;
413 /* Start the transmission */
414 writel(POLL_DATA, &dma_p->txpolldemand);
419 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
421 u32 status, desc_num = priv->rx_currdescnum;
422 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
423 int length = -EAGAIN;
424 ulong desc_start = (ulong)desc_p;
425 ulong desc_end = desc_start +
426 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
427 ulong data_start = desc_p->dmamac_addr;
430 /* Invalidate entire buffer descriptor */
431 invalidate_dcache_range(desc_start, desc_end);
433 status = desc_p->txrx_status;
435 /* Check if the owner is the CPU */
436 if (!(status & DESC_RXSTS_OWNBYDMA)) {
438 length = (status & DESC_RXSTS_FRMLENMSK) >>
439 DESC_RXSTS_FRMLENSHFT;
441 /* Invalidate received data */
442 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
443 invalidate_dcache_range(data_start, data_end);
444 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
450 static int _dw_free_pkt(struct dw_eth_dev *priv)
452 u32 desc_num = priv->rx_currdescnum;
453 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
454 ulong desc_start = (ulong)desc_p;
455 ulong desc_end = desc_start +
456 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
459 * Make the current descriptor valid again and go to
462 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
464 /* Flush only status field - others weren't changed */
465 flush_dcache_range(desc_start, desc_end);
467 /* Test the wrap-around condition. */
468 if (++desc_num >= CONFIG_RX_DESCR_NUM)
470 priv->rx_currdescnum = desc_num;
475 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
477 struct phy_device *phydev;
478 int mask = 0xffffffff, ret;
480 #ifdef CONFIG_PHY_ADDR
481 mask = 1 << CONFIG_PHY_ADDR;
484 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
488 phy_connect_dev(phydev, dev);
490 phydev->supported &= PHY_GBIT_FEATURES;
491 if (priv->max_speed) {
492 ret = phy_set_supported(phydev, priv->max_speed);
496 phydev->advertising = phydev->supported;
498 priv->phydev = phydev;
504 #ifndef CONFIG_DM_ETH
505 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
509 ret = designware_eth_init(dev->priv, dev->enetaddr);
511 ret = designware_eth_enable(dev->priv);
516 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
518 return _dw_eth_send(dev->priv, packet, length);
521 static int dw_eth_recv(struct eth_device *dev)
526 length = _dw_eth_recv(dev->priv, &packet);
527 if (length == -EAGAIN)
529 net_process_received_packet(packet, length);
531 _dw_free_pkt(dev->priv);
536 static void dw_eth_halt(struct eth_device *dev)
538 return _dw_eth_halt(dev->priv);
541 static int dw_write_hwaddr(struct eth_device *dev)
543 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
546 int designware_initialize(ulong base_addr, u32 interface)
548 struct eth_device *dev;
549 struct dw_eth_dev *priv;
551 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
556 * Since the priv structure contains the descriptors which need a strict
557 * buswidth alignment, memalign is used to allocate memory
559 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
560 sizeof(struct dw_eth_dev));
566 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
567 printf("designware: buffers are outside DMA memory\n");
571 memset(dev, 0, sizeof(struct eth_device));
572 memset(priv, 0, sizeof(struct dw_eth_dev));
574 sprintf(dev->name, "dwmac.%lx", base_addr);
575 dev->iobase = (int)base_addr;
579 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
580 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
583 dev->init = dw_eth_init;
584 dev->send = dw_eth_send;
585 dev->recv = dw_eth_recv;
586 dev->halt = dw_eth_halt;
587 dev->write_hwaddr = dw_write_hwaddr;
591 priv->interface = interface;
593 dw_mdio_init(dev->name, priv->mac_regs_p);
594 priv->bus = miiphy_get_dev_by_name(dev->name);
596 return dw_phy_init(priv, dev);
601 static int designware_eth_start(struct udevice *dev)
603 struct eth_pdata *pdata = dev_get_platdata(dev);
604 struct dw_eth_dev *priv = dev_get_priv(dev);
607 ret = designware_eth_init(priv, pdata->enetaddr);
610 ret = designware_eth_enable(priv);
617 int designware_eth_send(struct udevice *dev, void *packet, int length)
619 struct dw_eth_dev *priv = dev_get_priv(dev);
621 return _dw_eth_send(priv, packet, length);
624 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
626 struct dw_eth_dev *priv = dev_get_priv(dev);
628 return _dw_eth_recv(priv, packetp);
631 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
633 struct dw_eth_dev *priv = dev_get_priv(dev);
635 return _dw_free_pkt(priv);
638 void designware_eth_stop(struct udevice *dev)
640 struct dw_eth_dev *priv = dev_get_priv(dev);
642 return _dw_eth_halt(priv);
645 int designware_eth_write_hwaddr(struct udevice *dev)
647 struct eth_pdata *pdata = dev_get_platdata(dev);
648 struct dw_eth_dev *priv = dev_get_priv(dev);
650 return _dw_write_hwaddr(priv, pdata->enetaddr);
653 static int designware_eth_bind(struct udevice *dev)
656 static int num_cards;
659 /* Create a unique device name for PCI type devices */
660 if (device_is_on_pci_bus(dev)) {
661 sprintf(name, "eth_designware#%u", num_cards++);
662 device_set_name(dev, name);
669 int designware_eth_probe(struct udevice *dev)
671 struct eth_pdata *pdata = dev_get_platdata(dev);
672 struct dw_eth_dev *priv = dev_get_priv(dev);
673 u32 iobase = pdata->iobase;
677 int i, err, clock_nb;
679 priv->clock_count = 0;
680 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
682 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
687 for (i = 0; i < clock_nb; i++) {
688 err = clk_get_by_index(dev, i, &priv->clocks[i]);
692 err = clk_enable(&priv->clocks[i]);
693 if (err && err != -ENOSYS && err != -ENOTSUPP) {
694 pr_err("failed to enable clock %d\n", i);
695 clk_free(&priv->clocks[i]);
700 } else if (clock_nb != -ENOENT) {
701 pr_err("failed to get clock phandle(%d)\n", clock_nb);
706 #if defined(CONFIG_DM_REGULATOR)
707 struct udevice *phy_supply;
709 ret = device_get_supply_regulator(dev, "phy-supply",
712 debug("%s: No phy supply\n", dev->name);
714 ret = regulator_set_enable(phy_supply, true);
716 puts("Error enabling phy supply\n");
724 * If we are on PCI bus, either directly attached to a PCI root port,
725 * or via a PCI bridge, fill in platdata before we probe the hardware.
727 if (device_is_on_pci_bus(dev)) {
728 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
729 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
730 iobase = dm_pci_mem_to_phys(dev, iobase);
732 pdata->iobase = iobase;
733 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
737 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
739 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
740 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
741 priv->interface = pdata->phy_interface;
742 priv->max_speed = pdata->max_speed;
744 dw_mdio_init(dev->name, dev);
745 priv->bus = miiphy_get_dev_by_name(dev->name);
747 ret = dw_phy_init(priv, dev);
748 debug("%s, ret=%d\n", __func__, ret);
754 ret = clk_release_all(priv->clocks, priv->clock_count);
756 pr_err("failed to disable all clocks\n");
762 static int designware_eth_remove(struct udevice *dev)
764 struct dw_eth_dev *priv = dev_get_priv(dev);
767 mdio_unregister(priv->bus);
768 mdio_free(priv->bus);
771 return clk_release_all(priv->clocks, priv->clock_count);
777 const struct eth_ops designware_eth_ops = {
778 .start = designware_eth_start,
779 .send = designware_eth_send,
780 .recv = designware_eth_recv,
781 .free_pkt = designware_eth_free_pkt,
782 .stop = designware_eth_stop,
783 .write_hwaddr = designware_eth_write_hwaddr,
786 int designware_eth_ofdata_to_platdata(struct udevice *dev)
788 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
789 #ifdef CONFIG_DM_GPIO
790 struct dw_eth_dev *priv = dev_get_priv(dev);
792 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
793 const char *phy_mode;
794 #ifdef CONFIG_DM_GPIO
795 int reset_flags = GPIOD_IS_OUT;
799 pdata->iobase = dev_read_addr(dev);
800 pdata->phy_interface = -1;
801 phy_mode = dev_read_string(dev, "phy-mode");
803 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
804 if (pdata->phy_interface == -1) {
805 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
809 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
811 #ifdef CONFIG_DM_GPIO
812 if (dev_read_bool(dev, "snps,reset-active-low"))
813 reset_flags |= GPIOD_ACTIVE_LOW;
815 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
816 &priv->reset_gpio, reset_flags);
818 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
819 dw_pdata->reset_delays, 3);
820 } else if (ret == -ENOENT) {
828 static const struct udevice_id designware_eth_ids[] = {
829 { .compatible = "allwinner,sun7i-a20-gmac" },
830 { .compatible = "altr,socfpga-stmmac" },
831 { .compatible = "amlogic,meson6-dwmac" },
832 { .compatible = "amlogic,meson-gx-dwmac" },
833 { .compatible = "st,stm32-dwmac" },
837 U_BOOT_DRIVER(eth_designware) = {
838 .name = "eth_designware",
840 .of_match = designware_eth_ids,
841 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
842 .bind = designware_eth_bind,
843 .probe = designware_eth_probe,
844 .remove = designware_eth_remove,
845 .ops = &designware_eth_ops,
846 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
847 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
848 .flags = DM_FLAG_ALLOC_PRIV_DMA,
851 static struct pci_device_id supported[] = {
852 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
856 U_BOOT_PCI_DEVICE(eth_designware, supported);