3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Designware ethernet IP driver for U-Boot
19 #include <linux/compiler.h>
20 #include <linux/err.h>
22 #include <power/regulator.h>
23 #include "designware.h"
25 DECLARE_GLOBAL_DATA_PTR;
27 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
30 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
31 struct eth_mac_regs *mac_p = priv->mac_regs_p;
33 struct eth_mac_regs *mac_p = bus->priv;
37 int timeout = CONFIG_MDIO_TIMEOUT;
39 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
40 ((reg << MIIREGSHIFT) & MII_REGMSK);
42 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
45 while (get_timer(start) < timeout) {
46 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
47 return readl(&mac_p->miidata);
54 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
58 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
59 struct eth_mac_regs *mac_p = priv->mac_regs_p;
61 struct eth_mac_regs *mac_p = bus->priv;
65 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
67 writel(val, &mac_p->miidata);
68 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
69 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
71 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
74 while (get_timer(start) < timeout) {
75 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
85 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
86 static int dw_mdio_reset(struct mii_dev *bus)
88 struct udevice *dev = bus->priv;
89 struct dw_eth_dev *priv = dev_get_priv(dev);
90 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
93 if (!dm_gpio_is_valid(&priv->reset_gpio))
97 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
101 udelay(pdata->reset_delays[0]);
103 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
107 udelay(pdata->reset_delays[1]);
109 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
113 udelay(pdata->reset_delays[2]);
119 static int dw_mdio_init(const char *name, void *priv)
121 struct mii_dev *bus = mdio_alloc();
124 printf("Failed to allocate MDIO bus\n");
128 bus->read = dw_mdio_read;
129 bus->write = dw_mdio_write;
130 snprintf(bus->name, sizeof(bus->name), "%s", name);
131 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
132 bus->reset = dw_mdio_reset;
137 return mdio_register(bus);
140 static void tx_descs_init(struct dw_eth_dev *priv)
142 struct eth_dma_regs *dma_p = priv->dma_regs_p;
143 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
144 char *txbuffs = &priv->txbuffs[0];
145 struct dmamacdescr *desc_p;
148 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
149 desc_p = &desc_table_p[idx];
150 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
151 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
153 #if defined(CONFIG_DW_ALTDESCRIPTOR)
154 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
155 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
156 DESC_TXSTS_TXCHECKINSCTRL |
157 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
159 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
160 desc_p->dmamac_cntl = 0;
161 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
163 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
164 desc_p->txrx_status = 0;
168 /* Correcting the last pointer of the chain */
169 desc_p->dmamac_next = (ulong)&desc_table_p[0];
171 /* Flush all Tx buffer descriptors at once */
172 flush_dcache_range((ulong)priv->tx_mac_descrtable,
173 (ulong)priv->tx_mac_descrtable +
174 sizeof(priv->tx_mac_descrtable));
176 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
177 priv->tx_currdescnum = 0;
180 static void rx_descs_init(struct dw_eth_dev *priv)
182 struct eth_dma_regs *dma_p = priv->dma_regs_p;
183 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
184 char *rxbuffs = &priv->rxbuffs[0];
185 struct dmamacdescr *desc_p;
188 /* Before passing buffers to GMAC we need to make sure zeros
189 * written there right after "priv" structure allocation were
191 * Otherwise there's a chance to get some of them flushed in RAM when
192 * GMAC is already pushing data to RAM via DMA. This way incoming from
193 * GMAC data will be corrupted. */
194 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
196 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
197 desc_p = &desc_table_p[idx];
198 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
199 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
201 desc_p->dmamac_cntl =
202 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
205 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
208 /* Correcting the last pointer of the chain */
209 desc_p->dmamac_next = (ulong)&desc_table_p[0];
211 /* Flush all Rx buffer descriptors at once */
212 flush_dcache_range((ulong)priv->rx_mac_descrtable,
213 (ulong)priv->rx_mac_descrtable +
214 sizeof(priv->rx_mac_descrtable));
216 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
217 priv->rx_currdescnum = 0;
220 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
222 struct eth_mac_regs *mac_p = priv->mac_regs_p;
223 u32 macid_lo, macid_hi;
225 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
227 macid_hi = mac_id[4] + (mac_id[5] << 8);
229 writel(macid_hi, &mac_p->macaddr0hi);
230 writel(macid_lo, &mac_p->macaddr0lo);
235 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
236 struct phy_device *phydev)
238 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
241 printf("%s: No link.\n", phydev->dev->name);
245 if (phydev->speed != 1000)
246 conf |= MII_PORTSELECT;
248 conf &= ~MII_PORTSELECT;
250 if (phydev->speed == 100)
254 conf |= FULLDPLXMODE;
256 writel(conf, &mac_p->conf);
258 printf("Speed: %d, %s duplex%s\n", phydev->speed,
259 (phydev->duplex) ? "full" : "half",
260 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
265 static void _dw_eth_halt(struct dw_eth_dev *priv)
267 struct eth_mac_regs *mac_p = priv->mac_regs_p;
268 struct eth_dma_regs *dma_p = priv->dma_regs_p;
270 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
271 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
273 phy_shutdown(priv->phydev);
276 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
278 struct eth_mac_regs *mac_p = priv->mac_regs_p;
279 struct eth_dma_regs *dma_p = priv->dma_regs_p;
283 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
285 start = get_timer(0);
286 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
287 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
288 printf("DMA reset timeout\n");
296 * Soft reset above clears HW address registers.
297 * So we have to set it here once again.
299 _dw_write_hwaddr(priv, enetaddr);
304 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
306 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
307 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
310 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
314 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
316 #ifdef CONFIG_DW_AXI_BURST_LEN
317 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
320 /* Start up the PHY */
321 ret = phy_startup(priv->phydev);
323 printf("Could not initialize PHY %s\n",
324 priv->phydev->dev->name);
328 ret = dw_adjust_link(priv, mac_p, priv->phydev);
335 int designware_eth_enable(struct dw_eth_dev *priv)
337 struct eth_mac_regs *mac_p = priv->mac_regs_p;
339 if (!priv->phydev->link)
342 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
347 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
349 struct eth_dma_regs *dma_p = priv->dma_regs_p;
350 u32 desc_num = priv->tx_currdescnum;
351 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
352 ulong desc_start = (ulong)desc_p;
353 ulong desc_end = desc_start +
354 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
355 ulong data_start = desc_p->dmamac_addr;
356 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
358 * Strictly we only need to invalidate the "txrx_status" field
359 * for the following check, but on some platforms we cannot
360 * invalidate only 4 bytes, so we flush the entire descriptor,
361 * which is 16 bytes in total. This is safe because the
362 * individual descriptors in the array are each aligned to
363 * ARCH_DMA_MINALIGN and padded appropriately.
365 invalidate_dcache_range(desc_start, desc_end);
367 /* Check if the descriptor is owned by CPU */
368 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
369 printf("CPU not owner of tx frame\n");
373 memcpy((void *)data_start, packet, length);
375 /* Flush data to be sent */
376 flush_dcache_range(data_start, data_end);
378 #if defined(CONFIG_DW_ALTDESCRIPTOR)
379 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
380 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
381 DESC_TXCTRL_SIZE1MASK;
383 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
384 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
386 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
387 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
390 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
393 /* Flush modified buffer descriptor */
394 flush_dcache_range(desc_start, desc_end);
396 /* Test the wrap-around condition. */
397 if (++desc_num >= CONFIG_TX_DESCR_NUM)
400 priv->tx_currdescnum = desc_num;
402 /* Start the transmission */
403 writel(POLL_DATA, &dma_p->txpolldemand);
408 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
410 u32 status, desc_num = priv->rx_currdescnum;
411 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
412 int length = -EAGAIN;
413 ulong desc_start = (ulong)desc_p;
414 ulong desc_end = desc_start +
415 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
416 ulong data_start = desc_p->dmamac_addr;
419 /* Invalidate entire buffer descriptor */
420 invalidate_dcache_range(desc_start, desc_end);
422 status = desc_p->txrx_status;
424 /* Check if the owner is the CPU */
425 if (!(status & DESC_RXSTS_OWNBYDMA)) {
427 length = (status & DESC_RXSTS_FRMLENMSK) >>
428 DESC_RXSTS_FRMLENSHFT;
430 /* Invalidate received data */
431 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
432 invalidate_dcache_range(data_start, data_end);
433 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
439 static int _dw_free_pkt(struct dw_eth_dev *priv)
441 u32 desc_num = priv->rx_currdescnum;
442 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
443 ulong desc_start = (ulong)desc_p;
444 ulong desc_end = desc_start +
445 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
448 * Make the current descriptor valid again and go to
451 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
453 /* Flush only status field - others weren't changed */
454 flush_dcache_range(desc_start, desc_end);
456 /* Test the wrap-around condition. */
457 if (++desc_num >= CONFIG_RX_DESCR_NUM)
459 priv->rx_currdescnum = desc_num;
464 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
466 struct phy_device *phydev;
467 int mask = 0xffffffff, ret;
469 #ifdef CONFIG_PHY_ADDR
470 mask = 1 << CONFIG_PHY_ADDR;
473 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
477 phy_connect_dev(phydev, dev);
479 phydev->supported &= PHY_GBIT_FEATURES;
480 if (priv->max_speed) {
481 ret = phy_set_supported(phydev, priv->max_speed);
485 phydev->advertising = phydev->supported;
487 priv->phydev = phydev;
493 #ifndef CONFIG_DM_ETH
494 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
498 ret = designware_eth_init(dev->priv, dev->enetaddr);
500 ret = designware_eth_enable(dev->priv);
505 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
507 return _dw_eth_send(dev->priv, packet, length);
510 static int dw_eth_recv(struct eth_device *dev)
515 length = _dw_eth_recv(dev->priv, &packet);
516 if (length == -EAGAIN)
518 net_process_received_packet(packet, length);
520 _dw_free_pkt(dev->priv);
525 static void dw_eth_halt(struct eth_device *dev)
527 return _dw_eth_halt(dev->priv);
530 static int dw_write_hwaddr(struct eth_device *dev)
532 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
535 int designware_initialize(ulong base_addr, u32 interface)
537 struct eth_device *dev;
538 struct dw_eth_dev *priv;
540 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
545 * Since the priv structure contains the descriptors which need a strict
546 * buswidth alignment, memalign is used to allocate memory
548 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
549 sizeof(struct dw_eth_dev));
555 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
556 printf("designware: buffers are outside DMA memory\n");
560 memset(dev, 0, sizeof(struct eth_device));
561 memset(priv, 0, sizeof(struct dw_eth_dev));
563 sprintf(dev->name, "dwmac.%lx", base_addr);
564 dev->iobase = (int)base_addr;
568 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
569 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
572 dev->init = dw_eth_init;
573 dev->send = dw_eth_send;
574 dev->recv = dw_eth_recv;
575 dev->halt = dw_eth_halt;
576 dev->write_hwaddr = dw_write_hwaddr;
580 priv->interface = interface;
582 dw_mdio_init(dev->name, priv->mac_regs_p);
583 priv->bus = miiphy_get_dev_by_name(dev->name);
585 return dw_phy_init(priv, dev);
590 static int designware_eth_start(struct udevice *dev)
592 struct eth_pdata *pdata = dev_get_platdata(dev);
593 struct dw_eth_dev *priv = dev_get_priv(dev);
596 ret = designware_eth_init(priv, pdata->enetaddr);
599 ret = designware_eth_enable(priv);
606 int designware_eth_send(struct udevice *dev, void *packet, int length)
608 struct dw_eth_dev *priv = dev_get_priv(dev);
610 return _dw_eth_send(priv, packet, length);
613 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
615 struct dw_eth_dev *priv = dev_get_priv(dev);
617 return _dw_eth_recv(priv, packetp);
620 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
622 struct dw_eth_dev *priv = dev_get_priv(dev);
624 return _dw_free_pkt(priv);
627 void designware_eth_stop(struct udevice *dev)
629 struct dw_eth_dev *priv = dev_get_priv(dev);
631 return _dw_eth_halt(priv);
634 int designware_eth_write_hwaddr(struct udevice *dev)
636 struct eth_pdata *pdata = dev_get_platdata(dev);
637 struct dw_eth_dev *priv = dev_get_priv(dev);
639 return _dw_write_hwaddr(priv, pdata->enetaddr);
642 static int designware_eth_bind(struct udevice *dev)
645 static int num_cards;
648 /* Create a unique device name for PCI type devices */
649 if (device_is_on_pci_bus(dev)) {
650 sprintf(name, "eth_designware#%u", num_cards++);
651 device_set_name(dev, name);
658 int designware_eth_probe(struct udevice *dev)
660 struct eth_pdata *pdata = dev_get_platdata(dev);
661 struct dw_eth_dev *priv = dev_get_priv(dev);
662 u32 iobase = pdata->iobase;
666 int i, err, clock_nb;
668 priv->clock_count = 0;
669 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
671 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
676 for (i = 0; i < clock_nb; i++) {
677 err = clk_get_by_index(dev, i, &priv->clocks[i]);
681 err = clk_enable(&priv->clocks[i]);
683 pr_err("failed to enable clock %d\n", i);
684 clk_free(&priv->clocks[i]);
689 } else if (clock_nb != -ENOENT) {
690 pr_err("failed to get clock phandle(%d)\n", clock_nb);
695 #if defined(CONFIG_DM_REGULATOR)
696 struct udevice *phy_supply;
698 ret = device_get_supply_regulator(dev, "phy-supply",
701 debug("%s: No phy supply\n", dev->name);
703 ret = regulator_set_enable(phy_supply, true);
705 puts("Error enabling phy supply\n");
713 * If we are on PCI bus, either directly attached to a PCI root port,
714 * or via a PCI bridge, fill in platdata before we probe the hardware.
716 if (device_is_on_pci_bus(dev)) {
717 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
718 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
719 iobase = dm_pci_mem_to_phys(dev, iobase);
721 pdata->iobase = iobase;
722 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
726 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
728 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
729 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
730 priv->interface = pdata->phy_interface;
731 priv->max_speed = pdata->max_speed;
733 dw_mdio_init(dev->name, dev);
734 priv->bus = miiphy_get_dev_by_name(dev->name);
736 ret = dw_phy_init(priv, dev);
737 debug("%s, ret=%d\n", __func__, ret);
743 ret = clk_release_all(priv->clocks, priv->clock_count);
745 pr_err("failed to disable all clocks\n");
751 static int designware_eth_remove(struct udevice *dev)
753 struct dw_eth_dev *priv = dev_get_priv(dev);
756 mdio_unregister(priv->bus);
757 mdio_free(priv->bus);
760 return clk_release_all(priv->clocks, priv->clock_count);
766 const struct eth_ops designware_eth_ops = {
767 .start = designware_eth_start,
768 .send = designware_eth_send,
769 .recv = designware_eth_recv,
770 .free_pkt = designware_eth_free_pkt,
771 .stop = designware_eth_stop,
772 .write_hwaddr = designware_eth_write_hwaddr,
775 int designware_eth_ofdata_to_platdata(struct udevice *dev)
777 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
778 #ifdef CONFIG_DM_GPIO
779 struct dw_eth_dev *priv = dev_get_priv(dev);
781 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
782 const char *phy_mode;
783 #ifdef CONFIG_DM_GPIO
784 int reset_flags = GPIOD_IS_OUT;
788 pdata->iobase = dev_read_addr(dev);
789 pdata->phy_interface = -1;
790 phy_mode = dev_read_string(dev, "phy-mode");
792 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
793 if (pdata->phy_interface == -1) {
794 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
798 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
800 #ifdef CONFIG_DM_GPIO
801 if (dev_read_bool(dev, "snps,reset-active-low"))
802 reset_flags |= GPIOD_ACTIVE_LOW;
804 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
805 &priv->reset_gpio, reset_flags);
807 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
808 dw_pdata->reset_delays, 3);
809 } else if (ret == -ENOENT) {
817 static const struct udevice_id designware_eth_ids[] = {
818 { .compatible = "allwinner,sun7i-a20-gmac" },
819 { .compatible = "altr,socfpga-stmmac" },
820 { .compatible = "amlogic,meson6-dwmac" },
821 { .compatible = "amlogic,meson-gx-dwmac" },
822 { .compatible = "st,stm32-dwmac" },
826 U_BOOT_DRIVER(eth_designware) = {
827 .name = "eth_designware",
829 .of_match = designware_eth_ids,
830 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
831 .bind = designware_eth_bind,
832 .probe = designware_eth_probe,
833 .remove = designware_eth_remove,
834 .ops = &designware_eth_ops,
835 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
836 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
837 .flags = DM_FLAG_ALLOC_PRIV_DMA,
840 static struct pci_device_id supported[] = {
841 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
845 U_BOOT_PCI_DEVICE(eth_designware, supported);