3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Designware ethernet IP driver for u-boot
31 #include <linux/err.h>
33 #include "designware.h"
35 static int configure_phy(struct eth_device *dev);
37 static void tx_descs_init(struct eth_device *dev)
39 struct dw_eth_dev *priv = dev->priv;
40 struct eth_dma_regs *dma_p = priv->dma_regs_p;
41 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
42 char *txbuffs = &priv->txbuffs[0];
43 struct dmamacdescr *desc_p;
46 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
47 desc_p = &desc_table_p[idx];
48 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
49 desc_p->dmamac_next = &desc_table_p[idx + 1];
51 #if defined(CONFIG_DW_ALTDESCRIPTOR)
52 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
53 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
54 DESC_TXSTS_TXCHECKINSCTRL | \
55 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
57 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
58 desc_p->dmamac_cntl = 0;
59 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
61 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
62 desc_p->txrx_status = 0;
66 /* Correcting the last pointer of the chain */
67 desc_p->dmamac_next = &desc_table_p[0];
69 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
72 static void rx_descs_init(struct eth_device *dev)
74 struct dw_eth_dev *priv = dev->priv;
75 struct eth_dma_regs *dma_p = priv->dma_regs_p;
76 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
77 char *rxbuffs = &priv->rxbuffs[0];
78 struct dmamacdescr *desc_p;
81 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
82 desc_p = &desc_table_p[idx];
83 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
84 desc_p->dmamac_next = &desc_table_p[idx + 1];
87 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
90 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
93 /* Correcting the last pointer of the chain */
94 desc_p->dmamac_next = &desc_table_p[0];
96 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
99 static void descs_init(struct eth_device *dev)
105 static int mac_reset(struct eth_device *dev)
107 struct dw_eth_dev *priv = dev->priv;
108 struct eth_mac_regs *mac_p = priv->mac_regs_p;
109 struct eth_dma_regs *dma_p = priv->dma_regs_p;
112 int timeout = CONFIG_MACRESET_TIMEOUT;
114 writel(DMAMAC_SRST, &dma_p->busmode);
115 writel(MII_PORTSELECT, &mac_p->conf);
117 start = get_timer(0);
118 while (get_timer(start) < timeout) {
119 if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
122 /* Try again after 10usec */
129 static int dw_write_hwaddr(struct eth_device *dev)
131 struct dw_eth_dev *priv = dev->priv;
132 struct eth_mac_regs *mac_p = priv->mac_regs_p;
133 u32 macid_lo, macid_hi;
134 u8 *mac_id = &dev->enetaddr[0];
136 macid_lo = mac_id[0] + (mac_id[1] << 8) + \
137 (mac_id[2] << 16) + (mac_id[3] << 24);
138 macid_hi = mac_id[4] + (mac_id[5] << 8);
140 writel(macid_hi, &mac_p->macaddr0hi);
141 writel(macid_lo, &mac_p->macaddr0lo);
146 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
148 struct dw_eth_dev *priv = dev->priv;
149 struct eth_mac_regs *mac_p = priv->mac_regs_p;
150 struct eth_dma_regs *dma_p = priv->dma_regs_p;
153 if (priv->phy_configured != 1)
156 /* Reset ethernet hardware */
157 if (mac_reset(dev) < 0)
160 /* Resore the HW MAC address as it has been lost during MAC reset */
161 dw_write_hwaddr(dev);
163 writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
166 writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
167 writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
169 conf = FRAMEBURSTENABLE | DISABLERXOWN;
171 if (priv->speed != SPEED_1000M)
172 conf |= MII_PORTSELECT;
174 if (priv->duplex == FULL_DUPLEX)
175 conf |= FULLDPLXMODE;
177 writel(conf, &mac_p->conf);
182 * Start/Enable xfer at dma as well as mac level
184 writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
185 writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
187 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
192 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
194 struct dw_eth_dev *priv = dev->priv;
195 struct eth_dma_regs *dma_p = priv->dma_regs_p;
196 u32 desc_num = priv->tx_currdescnum;
197 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
199 /* Check if the descriptor is owned by CPU */
200 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
201 printf("CPU not owner of tx frame\n");
205 memcpy((void *)desc_p->dmamac_addr, packet, length);
207 #if defined(CONFIG_DW_ALTDESCRIPTOR)
208 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
209 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
210 DESC_TXCTRL_SIZE1MASK;
212 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
213 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
215 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
216 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
219 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
222 /* Test the wrap-around condition. */
223 if (++desc_num >= CONFIG_TX_DESCR_NUM)
226 priv->tx_currdescnum = desc_num;
228 /* Start the transmission */
229 writel(POLL_DATA, &dma_p->txpolldemand);
234 static int dw_eth_recv(struct eth_device *dev)
236 struct dw_eth_dev *priv = dev->priv;
237 u32 desc_num = priv->rx_currdescnum;
238 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
240 u32 status = desc_p->txrx_status;
243 /* Check if the owner is the CPU */
244 if (!(status & DESC_RXSTS_OWNBYDMA)) {
246 length = (status & DESC_RXSTS_FRMLENMSK) >> \
247 DESC_RXSTS_FRMLENSHFT;
249 NetReceive(desc_p->dmamac_addr, length);
252 * Make the current descriptor valid again and go to
255 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
257 /* Test the wrap-around condition. */
258 if (++desc_num >= CONFIG_RX_DESCR_NUM)
262 priv->rx_currdescnum = desc_num;
267 static void dw_eth_halt(struct eth_device *dev)
269 struct dw_eth_dev *priv = dev->priv;
272 priv->tx_currdescnum = priv->rx_currdescnum = 0;
275 static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
277 struct dw_eth_dev *priv = dev->priv;
278 struct eth_mac_regs *mac_p = priv->mac_regs_p;
281 int timeout = CONFIG_MDIO_TIMEOUT;
283 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
284 ((reg << MIIREGSHIFT) & MII_REGMSK);
286 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
288 start = get_timer(0);
289 while (get_timer(start) < timeout) {
290 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
291 *val = readl(&mac_p->miidata);
295 /* Try again after 10usec */
302 static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
304 struct dw_eth_dev *priv = dev->priv;
305 struct eth_mac_regs *mac_p = priv->mac_regs_p;
308 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
311 writel(val, &mac_p->miidata);
312 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
313 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
315 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
317 start = get_timer(0);
318 while (get_timer(start) < timeout) {
319 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
324 /* Try again after 10usec */
328 /* Needed as a fix for ST-Phy */
329 eth_mdio_read(dev, addr, reg, &value);
334 #if defined(CONFIG_DW_SEARCH_PHY)
335 static int find_phy(struct eth_device *dev)
341 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
342 oldctrl = ctrl & BMCR_ANENABLE;
344 ctrl ^= BMCR_ANENABLE;
345 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
346 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
347 ctrl &= BMCR_ANENABLE;
349 if (ctrl == oldctrl) {
352 ctrl ^= BMCR_ANENABLE;
353 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
357 } while (phy_addr < 32);
363 static int dw_reset_phy(struct eth_device *dev)
365 struct dw_eth_dev *priv = dev->priv;
368 int timeout = CONFIG_PHYRESET_TIMEOUT;
369 u32 phy_addr = priv->address;
371 eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
373 start = get_timer(0);
374 while (get_timer(start) < timeout) {
375 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
376 if (!(ctrl & BMCR_RESET))
379 /* Try again after 10usec */
383 if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
386 #ifdef CONFIG_PHY_RESET_DELAY
387 udelay(CONFIG_PHY_RESET_DELAY);
392 static int configure_phy(struct eth_device *dev)
394 struct dw_eth_dev *priv = dev->priv;
397 #if defined(CONFIG_DW_AUTONEG)
406 #if defined(CONFIG_DW_SEARCH_PHY)
407 phy_addr = find_phy(dev);
409 priv->address = phy_addr;
413 phy_addr = priv->address;
415 if (dw_reset_phy(dev) < 0)
418 #if defined(CONFIG_DW_AUTONEG)
419 /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
420 eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
422 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
424 bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
426 #if defined(CONFIG_DW_SPEED10M)
427 bmcr &= ~BMCR_SPEED100;
429 #if defined(CONFIG_DW_DUPLEXHALF)
430 bmcr &= ~BMCR_FULLDPLX;
433 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
436 /* Read the phy status register and populate priv structure */
437 #if defined(CONFIG_DW_AUTONEG)
438 timeout = CONFIG_AUTONEG_TIMEOUT;
439 start = get_timer(0);
441 while (get_timer(start) < timeout) {
442 eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
443 if (bmsr & BMSR_ANEGCOMPLETE)
446 /* Try again after 10usec */
450 eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar);
451 eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr);
453 if (bmsr & BMSR_ANEGCOMPLETE) {
454 if (btsr & PHY_1000BTSR_1000FD) {
455 priv->speed = SPEED_1000M;
456 bmcr |= BMCR_SPEED1000;
457 priv->duplex = FULL_DUPLEX;
458 bmcr |= BMCR_FULLDPLX;
459 } else if (btsr & PHY_1000BTSR_1000HD) {
460 priv->speed = SPEED_1000M;
461 bmcr |= BMCR_SPEED1000;
462 priv->duplex = HALF_DUPLEX;
463 bmcr &= ~BMCR_FULLDPLX;
464 } else if (anlpar & LPA_100FULL) {
465 priv->speed = SPEED_100M;
466 bmcr |= BMCR_SPEED100;
467 priv->duplex = FULL_DUPLEX;
468 bmcr |= BMCR_FULLDPLX;
469 } else if (anlpar & LPA_100HALF) {
470 priv->speed = SPEED_100M;
471 bmcr |= BMCR_SPEED100;
472 priv->duplex = HALF_DUPLEX;
473 bmcr &= ~BMCR_FULLDPLX;
474 } else if (anlpar & LPA_10FULL) {
475 priv->speed = SPEED_10M;
476 bmcr &= ~BMCR_SPEED100;
477 priv->duplex = FULL_DUPLEX;
478 bmcr |= BMCR_FULLDPLX;
480 priv->speed = SPEED_10M;
481 bmcr &= ~BMCR_SPEED100;
482 priv->duplex = HALF_DUPLEX;
483 bmcr &= ~BMCR_FULLDPLX;
485 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
490 if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0)
493 if (ctrl & BMCR_FULLDPLX)
494 priv->duplex = FULL_DUPLEX;
496 priv->duplex = HALF_DUPLEX;
498 if (ctrl & BMCR_SPEED1000)
499 priv->speed = SPEED_1000M;
500 else if (ctrl & BMCR_SPEED100)
501 priv->speed = SPEED_100M;
503 priv->speed = SPEED_10M;
505 priv->phy_configured = 1;
510 #if defined(CONFIG_MII)
511 static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
513 struct eth_device *dev;
515 dev = eth_get_dev_by_name(devname);
517 eth_mdio_read(dev, addr, reg, val);
522 static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
524 struct eth_device *dev;
526 dev = eth_get_dev_by_name(devname);
528 eth_mdio_write(dev, addr, reg, val);
534 int designware_initialize(u32 id, ulong base_addr, u32 phy_addr)
536 struct eth_device *dev;
537 struct dw_eth_dev *priv;
539 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
544 * Since the priv structure contains the descriptors which need a strict
545 * buswidth alignment, memalign is used to allocate memory
547 priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
553 memset(dev, 0, sizeof(struct eth_device));
554 memset(priv, 0, sizeof(struct dw_eth_dev));
556 sprintf(dev->name, "mii%d", id);
557 dev->iobase = (int)base_addr;
560 eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
563 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
564 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
566 priv->address = phy_addr;
567 priv->phy_configured = 0;
569 if (mac_reset(dev) < 0)
574 dev->init = dw_eth_init;
575 dev->send = dw_eth_send;
576 dev->recv = dw_eth_recv;
577 dev->halt = dw_eth_halt;
578 dev->write_hwaddr = dw_write_hwaddr;
582 #if defined(CONFIG_MII)
583 miiphy_register(dev->name, dw_mii_read, dw_mii_write);