3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Designware ethernet IP driver for U-Boot
18 #include <linux/compiler.h>
19 #include <linux/err.h>
21 #include "designware.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
28 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
29 struct eth_mac_regs *mac_p = priv->mac_regs_p;
31 struct eth_mac_regs *mac_p = bus->priv;
35 int timeout = CONFIG_MDIO_TIMEOUT;
37 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
38 ((reg << MIIREGSHIFT) & MII_REGMSK);
40 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
43 while (get_timer(start) < timeout) {
44 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
45 return readl(&mac_p->miidata);
52 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
56 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
57 struct eth_mac_regs *mac_p = priv->mac_regs_p;
59 struct eth_mac_regs *mac_p = bus->priv;
63 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
65 writel(val, &mac_p->miidata);
66 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
67 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
69 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
72 while (get_timer(start) < timeout) {
73 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
83 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
84 static int dw_mdio_reset(struct mii_dev *bus)
86 struct udevice *dev = bus->priv;
87 struct dw_eth_dev *priv = dev_get_priv(dev);
88 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
91 if (!dm_gpio_is_valid(&priv->reset_gpio))
95 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
99 udelay(pdata->reset_delays[0]);
101 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
105 udelay(pdata->reset_delays[1]);
107 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
111 udelay(pdata->reset_delays[2]);
117 static int dw_mdio_init(const char *name, void *priv)
119 struct mii_dev *bus = mdio_alloc();
122 printf("Failed to allocate MDIO bus\n");
126 bus->read = dw_mdio_read;
127 bus->write = dw_mdio_write;
128 snprintf(bus->name, sizeof(bus->name), "%s", name);
129 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
130 bus->reset = dw_mdio_reset;
135 return mdio_register(bus);
138 static void tx_descs_init(struct dw_eth_dev *priv)
140 struct eth_dma_regs *dma_p = priv->dma_regs_p;
141 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
142 char *txbuffs = &priv->txbuffs[0];
143 struct dmamacdescr *desc_p;
146 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
147 desc_p = &desc_table_p[idx];
148 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
149 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
151 #if defined(CONFIG_DW_ALTDESCRIPTOR)
152 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
153 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
154 DESC_TXSTS_TXCHECKINSCTRL |
155 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
157 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
158 desc_p->dmamac_cntl = 0;
159 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
161 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
162 desc_p->txrx_status = 0;
166 /* Correcting the last pointer of the chain */
167 desc_p->dmamac_next = (ulong)&desc_table_p[0];
169 /* Flush all Tx buffer descriptors at once */
170 flush_dcache_range((ulong)priv->tx_mac_descrtable,
171 (ulong)priv->tx_mac_descrtable +
172 sizeof(priv->tx_mac_descrtable));
174 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
175 priv->tx_currdescnum = 0;
178 static void rx_descs_init(struct dw_eth_dev *priv)
180 struct eth_dma_regs *dma_p = priv->dma_regs_p;
181 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
182 char *rxbuffs = &priv->rxbuffs[0];
183 struct dmamacdescr *desc_p;
186 /* Before passing buffers to GMAC we need to make sure zeros
187 * written there right after "priv" structure allocation were
189 * Otherwise there's a chance to get some of them flushed in RAM when
190 * GMAC is already pushing data to RAM via DMA. This way incoming from
191 * GMAC data will be corrupted. */
192 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
194 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
195 desc_p = &desc_table_p[idx];
196 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
197 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
199 desc_p->dmamac_cntl =
200 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
203 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
206 /* Correcting the last pointer of the chain */
207 desc_p->dmamac_next = (ulong)&desc_table_p[0];
209 /* Flush all Rx buffer descriptors at once */
210 flush_dcache_range((ulong)priv->rx_mac_descrtable,
211 (ulong)priv->rx_mac_descrtable +
212 sizeof(priv->rx_mac_descrtable));
214 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
215 priv->rx_currdescnum = 0;
218 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
220 struct eth_mac_regs *mac_p = priv->mac_regs_p;
221 u32 macid_lo, macid_hi;
223 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
225 macid_hi = mac_id[4] + (mac_id[5] << 8);
227 writel(macid_hi, &mac_p->macaddr0hi);
228 writel(macid_lo, &mac_p->macaddr0lo);
233 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
234 struct phy_device *phydev)
236 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
239 printf("%s: No link.\n", phydev->dev->name);
243 if (phydev->speed != 1000)
244 conf |= MII_PORTSELECT;
246 conf &= ~MII_PORTSELECT;
248 if (phydev->speed == 100)
252 conf |= FULLDPLXMODE;
254 writel(conf, &mac_p->conf);
256 printf("Speed: %d, %s duplex%s\n", phydev->speed,
257 (phydev->duplex) ? "full" : "half",
258 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
263 static void _dw_eth_halt(struct dw_eth_dev *priv)
265 struct eth_mac_regs *mac_p = priv->mac_regs_p;
266 struct eth_dma_regs *dma_p = priv->dma_regs_p;
268 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
269 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
271 phy_shutdown(priv->phydev);
274 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
276 struct eth_mac_regs *mac_p = priv->mac_regs_p;
277 struct eth_dma_regs *dma_p = priv->dma_regs_p;
281 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
283 start = get_timer(0);
284 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
285 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
286 printf("DMA reset timeout\n");
294 * Soft reset above clears HW address registers.
295 * So we have to set it here once again.
297 _dw_write_hwaddr(priv, enetaddr);
302 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
304 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
305 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
308 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
312 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
314 #ifdef CONFIG_DW_AXI_BURST_LEN
315 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
318 /* Start up the PHY */
319 ret = phy_startup(priv->phydev);
321 printf("Could not initialize PHY %s\n",
322 priv->phydev->dev->name);
326 ret = dw_adjust_link(priv, mac_p, priv->phydev);
333 int designware_eth_enable(struct dw_eth_dev *priv)
335 struct eth_mac_regs *mac_p = priv->mac_regs_p;
337 if (!priv->phydev->link)
340 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
345 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
347 struct eth_dma_regs *dma_p = priv->dma_regs_p;
348 u32 desc_num = priv->tx_currdescnum;
349 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
350 ulong desc_start = (ulong)desc_p;
351 ulong desc_end = desc_start +
352 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
353 ulong data_start = desc_p->dmamac_addr;
354 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
356 * Strictly we only need to invalidate the "txrx_status" field
357 * for the following check, but on some platforms we cannot
358 * invalidate only 4 bytes, so we flush the entire descriptor,
359 * which is 16 bytes in total. This is safe because the
360 * individual descriptors in the array are each aligned to
361 * ARCH_DMA_MINALIGN and padded appropriately.
363 invalidate_dcache_range(desc_start, desc_end);
365 /* Check if the descriptor is owned by CPU */
366 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
367 printf("CPU not owner of tx frame\n");
371 memcpy((void *)data_start, packet, length);
373 /* Flush data to be sent */
374 flush_dcache_range(data_start, data_end);
376 #if defined(CONFIG_DW_ALTDESCRIPTOR)
377 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
378 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
379 DESC_TXCTRL_SIZE1MASK;
381 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
382 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
384 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
385 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
388 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
391 /* Flush modified buffer descriptor */
392 flush_dcache_range(desc_start, desc_end);
394 /* Test the wrap-around condition. */
395 if (++desc_num >= CONFIG_TX_DESCR_NUM)
398 priv->tx_currdescnum = desc_num;
400 /* Start the transmission */
401 writel(POLL_DATA, &dma_p->txpolldemand);
406 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
408 u32 status, desc_num = priv->rx_currdescnum;
409 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
410 int length = -EAGAIN;
411 ulong desc_start = (ulong)desc_p;
412 ulong desc_end = desc_start +
413 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
414 ulong data_start = desc_p->dmamac_addr;
417 /* Invalidate entire buffer descriptor */
418 invalidate_dcache_range(desc_start, desc_end);
420 status = desc_p->txrx_status;
422 /* Check if the owner is the CPU */
423 if (!(status & DESC_RXSTS_OWNBYDMA)) {
425 length = (status & DESC_RXSTS_FRMLENMSK) >>
426 DESC_RXSTS_FRMLENSHFT;
428 /* Invalidate received data */
429 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
430 invalidate_dcache_range(data_start, data_end);
431 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
437 static int _dw_free_pkt(struct dw_eth_dev *priv)
439 u32 desc_num = priv->rx_currdescnum;
440 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
441 ulong desc_start = (ulong)desc_p;
442 ulong desc_end = desc_start +
443 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
446 * Make the current descriptor valid again and go to
449 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
451 /* Flush only status field - others weren't changed */
452 flush_dcache_range(desc_start, desc_end);
454 /* Test the wrap-around condition. */
455 if (++desc_num >= CONFIG_RX_DESCR_NUM)
457 priv->rx_currdescnum = desc_num;
462 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
464 struct phy_device *phydev;
465 int mask = 0xffffffff, ret;
467 #ifdef CONFIG_PHY_ADDR
468 mask = 1 << CONFIG_PHY_ADDR;
471 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
475 phy_connect_dev(phydev, dev);
477 phydev->supported &= PHY_GBIT_FEATURES;
478 if (priv->max_speed) {
479 ret = phy_set_supported(phydev, priv->max_speed);
483 phydev->advertising = phydev->supported;
485 priv->phydev = phydev;
491 #ifndef CONFIG_DM_ETH
492 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
496 ret = designware_eth_init(dev->priv, dev->enetaddr);
498 ret = designware_eth_enable(dev->priv);
503 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
505 return _dw_eth_send(dev->priv, packet, length);
508 static int dw_eth_recv(struct eth_device *dev)
513 length = _dw_eth_recv(dev->priv, &packet);
514 if (length == -EAGAIN)
516 net_process_received_packet(packet, length);
518 _dw_free_pkt(dev->priv);
523 static void dw_eth_halt(struct eth_device *dev)
525 return _dw_eth_halt(dev->priv);
528 static int dw_write_hwaddr(struct eth_device *dev)
530 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
533 int designware_initialize(ulong base_addr, u32 interface)
535 struct eth_device *dev;
536 struct dw_eth_dev *priv;
538 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
543 * Since the priv structure contains the descriptors which need a strict
544 * buswidth alignment, memalign is used to allocate memory
546 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
547 sizeof(struct dw_eth_dev));
553 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
554 printf("designware: buffers are outside DMA memory\n");
558 memset(dev, 0, sizeof(struct eth_device));
559 memset(priv, 0, sizeof(struct dw_eth_dev));
561 sprintf(dev->name, "dwmac.%lx", base_addr);
562 dev->iobase = (int)base_addr;
566 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
567 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
570 dev->init = dw_eth_init;
571 dev->send = dw_eth_send;
572 dev->recv = dw_eth_recv;
573 dev->halt = dw_eth_halt;
574 dev->write_hwaddr = dw_write_hwaddr;
578 priv->interface = interface;
580 dw_mdio_init(dev->name, priv->mac_regs_p);
581 priv->bus = miiphy_get_dev_by_name(dev->name);
583 return dw_phy_init(priv, dev);
588 static int designware_eth_start(struct udevice *dev)
590 struct eth_pdata *pdata = dev_get_platdata(dev);
591 struct dw_eth_dev *priv = dev_get_priv(dev);
594 ret = designware_eth_init(priv, pdata->enetaddr);
597 ret = designware_eth_enable(priv);
604 int designware_eth_send(struct udevice *dev, void *packet, int length)
606 struct dw_eth_dev *priv = dev_get_priv(dev);
608 return _dw_eth_send(priv, packet, length);
611 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
613 struct dw_eth_dev *priv = dev_get_priv(dev);
615 return _dw_eth_recv(priv, packetp);
618 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
620 struct dw_eth_dev *priv = dev_get_priv(dev);
622 return _dw_free_pkt(priv);
625 void designware_eth_stop(struct udevice *dev)
627 struct dw_eth_dev *priv = dev_get_priv(dev);
629 return _dw_eth_halt(priv);
632 int designware_eth_write_hwaddr(struct udevice *dev)
634 struct eth_pdata *pdata = dev_get_platdata(dev);
635 struct dw_eth_dev *priv = dev_get_priv(dev);
637 return _dw_write_hwaddr(priv, pdata->enetaddr);
640 static int designware_eth_bind(struct udevice *dev)
643 static int num_cards;
646 /* Create a unique device name for PCI type devices */
647 if (device_is_on_pci_bus(dev)) {
648 sprintf(name, "eth_designware#%u", num_cards++);
649 device_set_name(dev, name);
656 int designware_eth_probe(struct udevice *dev)
658 struct eth_pdata *pdata = dev_get_platdata(dev);
659 struct dw_eth_dev *priv = dev_get_priv(dev);
660 u32 iobase = pdata->iobase;
666 * If we are on PCI bus, either directly attached to a PCI root port,
667 * or via a PCI bridge, fill in platdata before we probe the hardware.
669 if (device_is_on_pci_bus(dev)) {
670 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
671 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
672 iobase = dm_pci_mem_to_phys(dev, iobase);
674 pdata->iobase = iobase;
675 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
679 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
681 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
682 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
683 priv->interface = pdata->phy_interface;
684 priv->max_speed = pdata->max_speed;
686 dw_mdio_init(dev->name, dev);
687 priv->bus = miiphy_get_dev_by_name(dev->name);
689 ret = dw_phy_init(priv, dev);
690 debug("%s, ret=%d\n", __func__, ret);
695 static int designware_eth_remove(struct udevice *dev)
697 struct dw_eth_dev *priv = dev_get_priv(dev);
700 mdio_unregister(priv->bus);
701 mdio_free(priv->bus);
706 const struct eth_ops designware_eth_ops = {
707 .start = designware_eth_start,
708 .send = designware_eth_send,
709 .recv = designware_eth_recv,
710 .free_pkt = designware_eth_free_pkt,
711 .stop = designware_eth_stop,
712 .write_hwaddr = designware_eth_write_hwaddr,
715 int designware_eth_ofdata_to_platdata(struct udevice *dev)
717 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
718 #ifdef CONFIG_DM_GPIO
719 struct dw_eth_dev *priv = dev_get_priv(dev);
721 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
722 const char *phy_mode;
724 #ifdef CONFIG_DM_GPIO
725 int reset_flags = GPIOD_IS_OUT;
729 pdata->iobase = dev_get_addr(dev);
730 pdata->phy_interface = -1;
731 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
733 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
734 if (pdata->phy_interface == -1) {
735 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
739 pdata->max_speed = 0;
740 cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL);
742 pdata->max_speed = fdt32_to_cpu(*cell);
744 #ifdef CONFIG_DM_GPIO
745 if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
746 "snps,reset-active-low"))
747 reset_flags |= GPIOD_ACTIVE_LOW;
749 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
750 &priv->reset_gpio, reset_flags);
752 ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
753 "snps,reset-delays-us", dw_pdata->reset_delays, 3);
754 } else if (ret == -ENOENT) {
762 static const struct udevice_id designware_eth_ids[] = {
763 { .compatible = "allwinner,sun7i-a20-gmac" },
764 { .compatible = "altr,socfpga-stmmac" },
765 { .compatible = "amlogic,meson6-dwmac" },
766 { .compatible = "st,stm32-dwmac" },
770 U_BOOT_DRIVER(eth_designware) = {
771 .name = "eth_designware",
773 .of_match = designware_eth_ids,
774 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
775 .bind = designware_eth_bind,
776 .probe = designware_eth_probe,
777 .remove = designware_eth_remove,
778 .ops = &designware_eth_ops,
779 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
780 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
781 .flags = DM_FLAG_ALLOC_PRIV_DMA,
784 static struct pci_device_id supported[] = {
785 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
789 U_BOOT_PCI_DEVICE(eth_designware, supported);