3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Designware ethernet IP driver for U-Boot
19 #include <linux/compiler.h>
20 #include <linux/err.h>
21 #include <linux/kernel.h>
23 #include <power/regulator.h>
24 #include "designware.h"
26 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
29 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
30 struct eth_mac_regs *mac_p = priv->mac_regs_p;
32 struct eth_mac_regs *mac_p = bus->priv;
36 int timeout = CONFIG_MDIO_TIMEOUT;
38 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
39 ((reg << MIIREGSHIFT) & MII_REGMSK);
41 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
44 while (get_timer(start) < timeout) {
45 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
46 return readl(&mac_p->miidata);
53 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
57 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
58 struct eth_mac_regs *mac_p = priv->mac_regs_p;
60 struct eth_mac_regs *mac_p = bus->priv;
64 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
66 writel(val, &mac_p->miidata);
67 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
68 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
70 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
73 while (get_timer(start) < timeout) {
74 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
84 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
85 static int dw_mdio_reset(struct mii_dev *bus)
87 struct udevice *dev = bus->priv;
88 struct dw_eth_dev *priv = dev_get_priv(dev);
89 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
92 if (!dm_gpio_is_valid(&priv->reset_gpio))
96 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
100 udelay(pdata->reset_delays[0]);
102 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
106 udelay(pdata->reset_delays[1]);
108 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
112 udelay(pdata->reset_delays[2]);
118 static int dw_mdio_init(const char *name, void *priv)
120 struct mii_dev *bus = mdio_alloc();
123 printf("Failed to allocate MDIO bus\n");
127 bus->read = dw_mdio_read;
128 bus->write = dw_mdio_write;
129 snprintf(bus->name, sizeof(bus->name), "%s", name);
130 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
131 bus->reset = dw_mdio_reset;
136 return mdio_register(bus);
139 static void tx_descs_init(struct dw_eth_dev *priv)
141 struct eth_dma_regs *dma_p = priv->dma_regs_p;
142 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
143 char *txbuffs = &priv->txbuffs[0];
144 struct dmamacdescr *desc_p;
147 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
148 desc_p = &desc_table_p[idx];
149 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
150 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
152 #if defined(CONFIG_DW_ALTDESCRIPTOR)
153 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
154 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
155 DESC_TXSTS_TXCHECKINSCTRL |
156 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
158 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
159 desc_p->dmamac_cntl = 0;
160 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
162 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
163 desc_p->txrx_status = 0;
167 /* Correcting the last pointer of the chain */
168 desc_p->dmamac_next = (ulong)&desc_table_p[0];
170 /* Flush all Tx buffer descriptors at once */
171 flush_dcache_range((ulong)priv->tx_mac_descrtable,
172 (ulong)priv->tx_mac_descrtable +
173 sizeof(priv->tx_mac_descrtable));
175 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
176 priv->tx_currdescnum = 0;
179 static void rx_descs_init(struct dw_eth_dev *priv)
181 struct eth_dma_regs *dma_p = priv->dma_regs_p;
182 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
183 char *rxbuffs = &priv->rxbuffs[0];
184 struct dmamacdescr *desc_p;
187 /* Before passing buffers to GMAC we need to make sure zeros
188 * written there right after "priv" structure allocation were
190 * Otherwise there's a chance to get some of them flushed in RAM when
191 * GMAC is already pushing data to RAM via DMA. This way incoming from
192 * GMAC data will be corrupted. */
193 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
195 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
196 desc_p = &desc_table_p[idx];
197 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
198 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
200 desc_p->dmamac_cntl =
201 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
204 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
207 /* Correcting the last pointer of the chain */
208 desc_p->dmamac_next = (ulong)&desc_table_p[0];
210 /* Flush all Rx buffer descriptors at once */
211 flush_dcache_range((ulong)priv->rx_mac_descrtable,
212 (ulong)priv->rx_mac_descrtable +
213 sizeof(priv->rx_mac_descrtable));
215 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
216 priv->rx_currdescnum = 0;
219 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
221 struct eth_mac_regs *mac_p = priv->mac_regs_p;
222 u32 macid_lo, macid_hi;
224 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
226 macid_hi = mac_id[4] + (mac_id[5] << 8);
228 writel(macid_hi, &mac_p->macaddr0hi);
229 writel(macid_lo, &mac_p->macaddr0lo);
234 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
235 struct phy_device *phydev)
237 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
240 printf("%s: No link.\n", phydev->dev->name);
244 if (phydev->speed != 1000)
245 conf |= MII_PORTSELECT;
247 conf &= ~MII_PORTSELECT;
249 if (phydev->speed == 100)
253 conf |= FULLDPLXMODE;
255 writel(conf, &mac_p->conf);
257 printf("Speed: %d, %s duplex%s\n", phydev->speed,
258 (phydev->duplex) ? "full" : "half",
259 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
264 static void _dw_eth_halt(struct dw_eth_dev *priv)
266 struct eth_mac_regs *mac_p = priv->mac_regs_p;
267 struct eth_dma_regs *dma_p = priv->dma_regs_p;
269 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
270 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
272 phy_shutdown(priv->phydev);
275 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
277 struct eth_mac_regs *mac_p = priv->mac_regs_p;
278 struct eth_dma_regs *dma_p = priv->dma_regs_p;
282 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
284 start = get_timer(0);
285 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
286 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
287 printf("DMA reset timeout\n");
295 * Soft reset above clears HW address registers.
296 * So we have to set it here once again.
298 _dw_write_hwaddr(priv, enetaddr);
303 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
305 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
306 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
309 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
313 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
315 #ifdef CONFIG_DW_AXI_BURST_LEN
316 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
319 /* Start up the PHY */
320 ret = phy_startup(priv->phydev);
322 printf("Could not initialize PHY %s\n",
323 priv->phydev->dev->name);
327 ret = dw_adjust_link(priv, mac_p, priv->phydev);
334 int designware_eth_enable(struct dw_eth_dev *priv)
336 struct eth_mac_regs *mac_p = priv->mac_regs_p;
338 if (!priv->phydev->link)
341 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
348 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
350 struct eth_dma_regs *dma_p = priv->dma_regs_p;
351 u32 desc_num = priv->tx_currdescnum;
352 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
353 ulong desc_start = (ulong)desc_p;
354 ulong desc_end = desc_start +
355 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
356 ulong data_start = desc_p->dmamac_addr;
357 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
359 * Strictly we only need to invalidate the "txrx_status" field
360 * for the following check, but on some platforms we cannot
361 * invalidate only 4 bytes, so we flush the entire descriptor,
362 * which is 16 bytes in total. This is safe because the
363 * individual descriptors in the array are each aligned to
364 * ARCH_DMA_MINALIGN and padded appropriately.
366 invalidate_dcache_range(desc_start, desc_end);
368 /* Check if the descriptor is owned by CPU */
369 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
370 printf("CPU not owner of tx frame\n");
374 length = max(length, ETH_ZLEN);
376 memcpy((void *)data_start, packet, length);
378 /* Flush data to be sent */
379 flush_dcache_range(data_start, data_end);
381 #if defined(CONFIG_DW_ALTDESCRIPTOR)
382 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
383 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
384 DESC_TXCTRL_SIZE1MASK;
386 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
387 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
389 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
390 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
393 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
396 /* Flush modified buffer descriptor */
397 flush_dcache_range(desc_start, desc_end);
399 /* Test the wrap-around condition. */
400 if (++desc_num >= CONFIG_TX_DESCR_NUM)
403 priv->tx_currdescnum = desc_num;
405 /* Start the transmission */
406 writel(POLL_DATA, &dma_p->txpolldemand);
411 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
413 u32 status, desc_num = priv->rx_currdescnum;
414 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
415 int length = -EAGAIN;
416 ulong desc_start = (ulong)desc_p;
417 ulong desc_end = desc_start +
418 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
419 ulong data_start = desc_p->dmamac_addr;
422 /* Invalidate entire buffer descriptor */
423 invalidate_dcache_range(desc_start, desc_end);
425 status = desc_p->txrx_status;
427 /* Check if the owner is the CPU */
428 if (!(status & DESC_RXSTS_OWNBYDMA)) {
430 length = (status & DESC_RXSTS_FRMLENMSK) >>
431 DESC_RXSTS_FRMLENSHFT;
433 /* Invalidate received data */
434 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
435 invalidate_dcache_range(data_start, data_end);
436 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
442 static int _dw_free_pkt(struct dw_eth_dev *priv)
444 u32 desc_num = priv->rx_currdescnum;
445 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
446 ulong desc_start = (ulong)desc_p;
447 ulong desc_end = desc_start +
448 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
451 * Make the current descriptor valid again and go to
454 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
456 /* Flush only status field - others weren't changed */
457 flush_dcache_range(desc_start, desc_end);
459 /* Test the wrap-around condition. */
460 if (++desc_num >= CONFIG_RX_DESCR_NUM)
462 priv->rx_currdescnum = desc_num;
467 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
469 struct phy_device *phydev;
470 int mask = 0xffffffff, ret;
472 #ifdef CONFIG_PHY_ADDR
473 mask = 1 << CONFIG_PHY_ADDR;
476 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
480 phy_connect_dev(phydev, dev);
482 phydev->supported &= PHY_GBIT_FEATURES;
483 if (priv->max_speed) {
484 ret = phy_set_supported(phydev, priv->max_speed);
488 phydev->advertising = phydev->supported;
490 priv->phydev = phydev;
496 #ifndef CONFIG_DM_ETH
497 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
501 ret = designware_eth_init(dev->priv, dev->enetaddr);
503 ret = designware_eth_enable(dev->priv);
508 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
510 return _dw_eth_send(dev->priv, packet, length);
513 static int dw_eth_recv(struct eth_device *dev)
518 length = _dw_eth_recv(dev->priv, &packet);
519 if (length == -EAGAIN)
521 net_process_received_packet(packet, length);
523 _dw_free_pkt(dev->priv);
528 static void dw_eth_halt(struct eth_device *dev)
530 return _dw_eth_halt(dev->priv);
533 static int dw_write_hwaddr(struct eth_device *dev)
535 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
538 int designware_initialize(ulong base_addr, u32 interface)
540 struct eth_device *dev;
541 struct dw_eth_dev *priv;
543 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
548 * Since the priv structure contains the descriptors which need a strict
549 * buswidth alignment, memalign is used to allocate memory
551 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
552 sizeof(struct dw_eth_dev));
558 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
559 printf("designware: buffers are outside DMA memory\n");
563 memset(dev, 0, sizeof(struct eth_device));
564 memset(priv, 0, sizeof(struct dw_eth_dev));
566 sprintf(dev->name, "dwmac.%lx", base_addr);
567 dev->iobase = (int)base_addr;
571 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
572 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
575 dev->init = dw_eth_init;
576 dev->send = dw_eth_send;
577 dev->recv = dw_eth_recv;
578 dev->halt = dw_eth_halt;
579 dev->write_hwaddr = dw_write_hwaddr;
583 priv->interface = interface;
585 dw_mdio_init(dev->name, priv->mac_regs_p);
586 priv->bus = miiphy_get_dev_by_name(dev->name);
588 return dw_phy_init(priv, dev);
593 static int designware_eth_start(struct udevice *dev)
595 struct eth_pdata *pdata = dev_get_platdata(dev);
596 struct dw_eth_dev *priv = dev_get_priv(dev);
599 ret = designware_eth_init(priv, pdata->enetaddr);
602 ret = designware_eth_enable(priv);
609 int designware_eth_send(struct udevice *dev, void *packet, int length)
611 struct dw_eth_dev *priv = dev_get_priv(dev);
613 return _dw_eth_send(priv, packet, length);
616 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
618 struct dw_eth_dev *priv = dev_get_priv(dev);
620 return _dw_eth_recv(priv, packetp);
623 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
625 struct dw_eth_dev *priv = dev_get_priv(dev);
627 return _dw_free_pkt(priv);
630 void designware_eth_stop(struct udevice *dev)
632 struct dw_eth_dev *priv = dev_get_priv(dev);
634 return _dw_eth_halt(priv);
637 int designware_eth_write_hwaddr(struct udevice *dev)
639 struct eth_pdata *pdata = dev_get_platdata(dev);
640 struct dw_eth_dev *priv = dev_get_priv(dev);
642 return _dw_write_hwaddr(priv, pdata->enetaddr);
645 static int designware_eth_bind(struct udevice *dev)
648 static int num_cards;
651 /* Create a unique device name for PCI type devices */
652 if (device_is_on_pci_bus(dev)) {
653 sprintf(name, "eth_designware#%u", num_cards++);
654 device_set_name(dev, name);
661 int designware_eth_probe(struct udevice *dev)
663 struct eth_pdata *pdata = dev_get_platdata(dev);
664 struct dw_eth_dev *priv = dev_get_priv(dev);
665 u32 iobase = pdata->iobase;
669 int i, err, clock_nb;
671 priv->clock_count = 0;
672 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
674 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
679 for (i = 0; i < clock_nb; i++) {
680 err = clk_get_by_index(dev, i, &priv->clocks[i]);
684 err = clk_enable(&priv->clocks[i]);
685 if (err && err != -ENOSYS && err != -ENOTSUPP) {
686 pr_err("failed to enable clock %d\n", i);
687 clk_free(&priv->clocks[i]);
692 } else if (clock_nb != -ENOENT) {
693 pr_err("failed to get clock phandle(%d)\n", clock_nb);
698 #if defined(CONFIG_DM_REGULATOR)
699 struct udevice *phy_supply;
701 ret = device_get_supply_regulator(dev, "phy-supply",
704 debug("%s: No phy supply\n", dev->name);
706 ret = regulator_set_enable(phy_supply, true);
708 puts("Error enabling phy supply\n");
716 * If we are on PCI bus, either directly attached to a PCI root port,
717 * or via a PCI bridge, fill in platdata before we probe the hardware.
719 if (device_is_on_pci_bus(dev)) {
720 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
721 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
722 iobase = dm_pci_mem_to_phys(dev, iobase);
724 pdata->iobase = iobase;
725 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
729 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
731 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
732 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
733 priv->interface = pdata->phy_interface;
734 priv->max_speed = pdata->max_speed;
736 dw_mdio_init(dev->name, dev);
737 priv->bus = miiphy_get_dev_by_name(dev->name);
739 ret = dw_phy_init(priv, dev);
740 debug("%s, ret=%d\n", __func__, ret);
746 ret = clk_release_all(priv->clocks, priv->clock_count);
748 pr_err("failed to disable all clocks\n");
754 static int designware_eth_remove(struct udevice *dev)
756 struct dw_eth_dev *priv = dev_get_priv(dev);
759 mdio_unregister(priv->bus);
760 mdio_free(priv->bus);
763 return clk_release_all(priv->clocks, priv->clock_count);
769 const struct eth_ops designware_eth_ops = {
770 .start = designware_eth_start,
771 .send = designware_eth_send,
772 .recv = designware_eth_recv,
773 .free_pkt = designware_eth_free_pkt,
774 .stop = designware_eth_stop,
775 .write_hwaddr = designware_eth_write_hwaddr,
778 int designware_eth_ofdata_to_platdata(struct udevice *dev)
780 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
781 #ifdef CONFIG_DM_GPIO
782 struct dw_eth_dev *priv = dev_get_priv(dev);
784 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
785 const char *phy_mode;
786 #ifdef CONFIG_DM_GPIO
787 int reset_flags = GPIOD_IS_OUT;
791 pdata->iobase = dev_read_addr(dev);
792 pdata->phy_interface = -1;
793 phy_mode = dev_read_string(dev, "phy-mode");
795 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
796 if (pdata->phy_interface == -1) {
797 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
801 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
803 #ifdef CONFIG_DM_GPIO
804 if (dev_read_bool(dev, "snps,reset-active-low"))
805 reset_flags |= GPIOD_ACTIVE_LOW;
807 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
808 &priv->reset_gpio, reset_flags);
810 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
811 dw_pdata->reset_delays, 3);
812 } else if (ret == -ENOENT) {
820 static const struct udevice_id designware_eth_ids[] = {
821 { .compatible = "allwinner,sun7i-a20-gmac" },
822 { .compatible = "altr,socfpga-stmmac" },
823 { .compatible = "amlogic,meson6-dwmac" },
824 { .compatible = "amlogic,meson-gx-dwmac" },
825 { .compatible = "st,stm32-dwmac" },
829 U_BOOT_DRIVER(eth_designware) = {
830 .name = "eth_designware",
832 .of_match = designware_eth_ids,
833 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
834 .bind = designware_eth_bind,
835 .probe = designware_eth_probe,
836 .remove = designware_eth_remove,
837 .ops = &designware_eth_ops,
838 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
839 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
840 .flags = DM_FLAG_ALLOC_PRIV_DMA,
843 static struct pci_device_id supported[] = {
844 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
848 U_BOOT_PCI_DEVICE(eth_designware, supported);