git.sur5r.net Git - u-boot/blob - drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12  * SPDX-License-Identifier:     GPL-2.0+
  13
  14   Contact Information:
  15   Linux NICS <linux.nics@intel.com>
  16   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  17
  18 *******************************************************************************/
  19 /*
  20  *  Copyright (C) Archway Digital Solutions.
  21  *
  22  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  23  *  2/9/2002
  24  *
  25  *  Copyright (C) Linux Networx.
  26  *  Massive upgrade to work with the new intel gigabit NICs.
  27  *  <ebiederman at lnxi dot com>
  28  *
  29  *  Copyright 2011 Freescale Semiconductor, Inc.
  30  */
  31
  32 #include <common.h>
  33 #include <dm.h>
  34 #include <errno.h>
  35 #include <memalign.h>
  36 #include <pci.h>
  37 #include "e1000.h"
  38
  39 #define TOUT_LOOP   100000
  40
  41 #ifdef CONFIG_DM_ETH
  42 #define virt_to_bus(devno, v)   dm_pci_virt_to_mem(devno, (void *) (v))
  43 #define bus_to_phys(devno, a)   dm_pci_mem_to_phys(devno, a)
  44 #else
  45 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  46 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  47 #endif
  48
  49 #define E1000_DEFAULT_PCI_PBA   0x00000030
  50 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  51
  52 /* NIC specific static variables go here */
  53
  54 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  55 #define E1000_BUFFER_ALIGN      128
  56
  57 /*
  58  * TODO(sjg@chromium.org): Even with driver model we share these buffers.
  59  * Concurrent receiving on multiple active Ethernet devices will not work.
  60  * Normally U-Boot does not support this anyway. To fix it in this driver,
  61  * move these buffers and the tx/rx pointers to struct e1000_hw.
  62  */
  63 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  64 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  65 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  66
  67 static int tx_tail;
  68 static int rx_tail, rx_last;
  69 #ifdef CONFIG_DM_ETH
  70 static int num_cards;   /* Number of E1000 devices seen so far */
  71 #endif
  72
  73 static struct pci_device_id e1000_supported[] = {
  74         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
  75         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
  76         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
  77         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
  78         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
  79         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
  80         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
  81         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
  82         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
  83         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
  84         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
  85         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
  86         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
  87         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
  88         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
  89         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
  90         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
  91         /* E1000 PCIe card */
  92         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
  93         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
  94         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
  95         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
  96         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
  97         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
  98         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
  99         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
 100         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
 101         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
 102         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
 103         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
 104         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
 105         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
 106         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
 107         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
 108         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
 109         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
 110         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
 111         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
 112         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
 113         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
 114         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
 115         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
 116         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
 117         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
 118         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
 119         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
 120         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
 121         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
 122
 123         {}
 124 };
 125
 126 /* Function forward declarations */
 127 static int e1000_setup_link(struct e1000_hw *hw);
 128 static int e1000_setup_fiber_link(struct e1000_hw *hw);
 129 static int e1000_setup_copper_link(struct e1000_hw *hw);
 130 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 131 static void e1000_config_collision_dist(struct e1000_hw *hw);
 132 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 133 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 134 static int e1000_check_for_link(struct e1000_hw *hw);
 135 static int e1000_wait_autoneg(struct e1000_hw *hw);
 136 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 137                                        uint16_t * duplex);
 138 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 139                               uint16_t * phy_data);
 140 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 141                                uint16_t phy_data);
 142 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 143 static int e1000_phy_reset(struct e1000_hw *hw);
 144 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 145 static void e1000_set_media_type(struct e1000_hw *hw);
 146
 147 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 148 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
 149 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 150
 151 #ifndef CONFIG_E1000_NO_NVM
 152 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 153 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
 154 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 155                 uint16_t words,
 156                 uint16_t *data);
 157 /******************************************************************************
 158  * Raises the EEPROM's clock input.
 159  *
 160  * hw - Struct containing variables accessed by shared code
 161  * eecd - EECD's current value
 162  *****************************************************************************/
 163 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 164 {
 165         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 166          * wait 50 microseconds.
 167          */
 168         *eecd = *eecd | E1000_EECD_SK;
 169         E1000_WRITE_REG(hw, EECD, *eecd);
 170         E1000_WRITE_FLUSH(hw);
 171         udelay(50);
 172 }
 173
 174 /******************************************************************************
 175  * Lowers the EEPROM's clock input.
 176  *
 177  * hw - Struct containing variables accessed by shared code
 178  * eecd - EECD's current value
 179  *****************************************************************************/
 180 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 181 {
 182         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 183          * wait 50 microseconds.
 184          */
 185         *eecd = *eecd & ~E1000_EECD_SK;
 186         E1000_WRITE_REG(hw, EECD, *eecd);
 187         E1000_WRITE_FLUSH(hw);
 188         udelay(50);
 189 }
 190
 191 /******************************************************************************
 192  * Shift data bits out to the EEPROM.
 193  *
 194  * hw - Struct containing variables accessed by shared code
 195  * data - data to send to the EEPROM
 196  * count - number of bits to shift out
 197  *****************************************************************************/
 198 static void
 199 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 200 {
 201         uint32_t eecd;
 202         uint32_t mask;
 203
 204         /* We need to shift "count" bits out to the EEPROM. So, value in the
 205          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 206          * In order to do this, "data" must be broken down into bits.
 207          */
 208         mask = 0x01 << (count - 1);
 209         eecd = E1000_READ_REG(hw, EECD);
 210         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 211         do {
 212                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 213                  * and then raising and then lowering the clock (the SK bit controls
 214                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 215                  * by setting "DI" to "0" and then raising and then lowering the clock.
 216                  */
 217                 eecd &= ~E1000_EECD_DI;
 218
 219                 if (data & mask)
 220                         eecd |= E1000_EECD_DI;
 221
 222                 E1000_WRITE_REG(hw, EECD, eecd);
 223                 E1000_WRITE_FLUSH(hw);
 224
 225                 udelay(50);
 226
 227                 e1000_raise_ee_clk(hw, &eecd);
 228                 e1000_lower_ee_clk(hw, &eecd);
 229
 230                 mask = mask >> 1;
 231
 232         } while (mask);
 233
 234         /* We leave the "DI" bit set to "0" when we leave this routine. */
 235         eecd &= ~E1000_EECD_DI;
 236         E1000_WRITE_REG(hw, EECD, eecd);
 237 }
 238
 239 /******************************************************************************
 240  * Shift data bits in from the EEPROM
 241  *
 242  * hw - Struct containing variables accessed by shared code
 243  *****************************************************************************/
 244 static uint16_t
 245 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 246 {
 247         uint32_t eecd;
 248         uint32_t i;
 249         uint16_t data;
 250
 251         /* In order to read a register from the EEPROM, we need to shift 'count'
 252          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 253          * input to the EEPROM (setting the SK bit), and then reading the
 254          * value of the "DO" bit.  During this "shifting in" process the
 255          * "DI" bit should always be clear.
 256          */
 257
 258         eecd = E1000_READ_REG(hw, EECD);
 259
 260         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 261         data = 0;
 262
 263         for (i = 0; i < count; i++) {
 264                 data = data << 1;
 265                 e1000_raise_ee_clk(hw, &eecd);
 266
 267                 eecd = E1000_READ_REG(hw, EECD);
 268
 269                 eecd &= ~(E1000_EECD_DI);
 270                 if (eecd & E1000_EECD_DO)
 271                         data |= 1;
 272
 273                 e1000_lower_ee_clk(hw, &eecd);
 274         }
 275
 276         return data;
 277 }
 278
 279 /******************************************************************************
 280  * Returns EEPROM to a "standby" state
 281  *
 282  * hw - Struct containing variables accessed by shared code
 283  *****************************************************************************/
 284 void e1000_standby_eeprom(struct e1000_hw *hw)
 285 {
 286         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 287         uint32_t eecd;
 288
 289         eecd = E1000_READ_REG(hw, EECD);
 290
 291         if (eeprom->type == e1000_eeprom_microwire) {
 292                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 293                 E1000_WRITE_REG(hw, EECD, eecd);
 294                 E1000_WRITE_FLUSH(hw);
 295                 udelay(eeprom->delay_usec);
 296
 297                 /* Clock high */
 298                 eecd |= E1000_EECD_SK;
 299                 E1000_WRITE_REG(hw, EECD, eecd);
 300                 E1000_WRITE_FLUSH(hw);
 301                 udelay(eeprom->delay_usec);
 302
 303                 /* Select EEPROM */
 304                 eecd |= E1000_EECD_CS;
 305                 E1000_WRITE_REG(hw, EECD, eecd);
 306                 E1000_WRITE_FLUSH(hw);
 307                 udelay(eeprom->delay_usec);
 308
 309                 /* Clock low */
 310                 eecd &= ~E1000_EECD_SK;
 311                 E1000_WRITE_REG(hw, EECD, eecd);
 312                 E1000_WRITE_FLUSH(hw);
 313                 udelay(eeprom->delay_usec);
 314         } else if (eeprom->type == e1000_eeprom_spi) {
 315                 /* Toggle CS to flush commands */
 316                 eecd |= E1000_EECD_CS;
 317                 E1000_WRITE_REG(hw, EECD, eecd);
 318                 E1000_WRITE_FLUSH(hw);
 319                 udelay(eeprom->delay_usec);
 320                 eecd &= ~E1000_EECD_CS;
 321                 E1000_WRITE_REG(hw, EECD, eecd);
 322                 E1000_WRITE_FLUSH(hw);
 323                 udelay(eeprom->delay_usec);
 324         }
 325 }
 326
 327 /***************************************************************************
 328 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 329 *
 330 * hw - Struct containing variables accessed by shared code
 331 ****************************************************************************/
 332 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 333 {
 334         uint32_t eecd = 0;
 335
 336         DEBUGFUNC();
 337
 338         if (hw->mac_type == e1000_ich8lan)
 339                 return false;
 340
 341         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 342                 eecd = E1000_READ_REG(hw, EECD);
 343
 344                 /* Isolate bits 15 & 16 */
 345                 eecd = ((eecd >> 15) & 0x03);
 346
 347                 /* If both bits are set, device is Flash type */
 348                 if (eecd == 0x03)
 349                         return false;
 350         }
 351         return true;
 352 }
 353
 354 /******************************************************************************
 355  * Prepares EEPROM for access
 356  *
 357  * hw - Struct containing variables accessed by shared code
 358  *
 359  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 360  * function should be called before issuing a command to the EEPROM.
 361  *****************************************************************************/
 362 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 363 {
 364         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 365         uint32_t eecd, i = 0;
 366
 367         DEBUGFUNC();
 368
 369         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 370                 return -E1000_ERR_SWFW_SYNC;
 371         eecd = E1000_READ_REG(hw, EECD);
 372
 373         if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
 374                 /* Request EEPROM Access */
 375                 if (hw->mac_type > e1000_82544) {
 376                         eecd |= E1000_EECD_REQ;
 377                         E1000_WRITE_REG(hw, EECD, eecd);
 378                         eecd = E1000_READ_REG(hw, EECD);
 379                         while ((!(eecd & E1000_EECD_GNT)) &&
 380                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 381                                 i++;
 382                                 udelay(5);
 383                                 eecd = E1000_READ_REG(hw, EECD);
 384                         }
 385                         if (!(eecd & E1000_EECD_GNT)) {
 386                                 eecd &= ~E1000_EECD_REQ;
 387                                 E1000_WRITE_REG(hw, EECD, eecd);
 388                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 389                                 return -E1000_ERR_EEPROM;
 390                         }
 391                 }
 392         }
 393
 394         /* Setup EEPROM for Read/Write */
 395
 396         if (eeprom->type == e1000_eeprom_microwire) {
 397                 /* Clear SK and DI */
 398                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 399                 E1000_WRITE_REG(hw, EECD, eecd);
 400
 401                 /* Set CS */
 402                 eecd |= E1000_EECD_CS;
 403                 E1000_WRITE_REG(hw, EECD, eecd);
 404         } else if (eeprom->type == e1000_eeprom_spi) {
 405                 /* Clear SK and CS */
 406                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 407                 E1000_WRITE_REG(hw, EECD, eecd);
 408                 udelay(1);
 409         }
 410
 411         return E1000_SUCCESS;
 412 }
 413
 414 /******************************************************************************
 415  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 416  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 417  * registers must be mapped, or this will crash.
 418  *
 419  * hw - Struct containing variables accessed by shared code
 420  *****************************************************************************/
 421 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 422 {
 423         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 424         uint32_t eecd;
 425         int32_t ret_val = E1000_SUCCESS;
 426         uint16_t eeprom_size;
 427
 428         if (hw->mac_type == e1000_igb)
 429                 eecd = E1000_READ_REG(hw, I210_EECD);
 430         else
 431                 eecd = E1000_READ_REG(hw, EECD);
 432
 433         DEBUGFUNC();
 434
 435         switch (hw->mac_type) {
 436         case e1000_82542_rev2_0:
 437         case e1000_82542_rev2_1:
 438         case e1000_82543:
 439         case e1000_82544:
 440                 eeprom->type = e1000_eeprom_microwire;
 441                 eeprom->word_size = 64;
 442                 eeprom->opcode_bits = 3;
 443                 eeprom->address_bits = 6;
 444                 eeprom->delay_usec = 50;
 445                 eeprom->use_eerd = false;
 446                 eeprom->use_eewr = false;
 447         break;
 448         case e1000_82540:
 449         case e1000_82545:
 450         case e1000_82545_rev_3:
 451         case e1000_82546:
 452         case e1000_82546_rev_3:
 453                 eeprom->type = e1000_eeprom_microwire;
 454                 eeprom->opcode_bits = 3;
 455                 eeprom->delay_usec = 50;
 456                 if (eecd & E1000_EECD_SIZE) {
 457                         eeprom->word_size = 256;
 458                         eeprom->address_bits = 8;
 459                 } else {
 460                         eeprom->word_size = 64;
 461                         eeprom->address_bits = 6;
 462                 }
 463                 eeprom->use_eerd = false;
 464                 eeprom->use_eewr = false;
 465                 break;
 466         case e1000_82541:
 467         case e1000_82541_rev_2:
 468         case e1000_82547:
 469         case e1000_82547_rev_2:
 470                 if (eecd & E1000_EECD_TYPE) {
 471                         eeprom->type = e1000_eeprom_spi;
 472                         eeprom->opcode_bits = 8;
 473                         eeprom->delay_usec = 1;
 474                         if (eecd & E1000_EECD_ADDR_BITS) {
 475                                 eeprom->page_size = 32;
 476                                 eeprom->address_bits = 16;
 477                         } else {
 478                                 eeprom->page_size = 8;
 479                                 eeprom->address_bits = 8;
 480                         }
 481                 } else {
 482                         eeprom->type = e1000_eeprom_microwire;
 483                         eeprom->opcode_bits = 3;
 484                         eeprom->delay_usec = 50;
 485                         if (eecd & E1000_EECD_ADDR_BITS) {
 486                                 eeprom->word_size = 256;
 487                                 eeprom->address_bits = 8;
 488                         } else {
 489                                 eeprom->word_size = 64;
 490                                 eeprom->address_bits = 6;
 491                         }
 492                 }
 493                 eeprom->use_eerd = false;
 494                 eeprom->use_eewr = false;
 495                 break;
 496         case e1000_82571:
 497         case e1000_82572:
 498                 eeprom->type = e1000_eeprom_spi;
 499                 eeprom->opcode_bits = 8;
 500                 eeprom->delay_usec = 1;
 501                 if (eecd & E1000_EECD_ADDR_BITS) {
 502                         eeprom->page_size = 32;
 503                         eeprom->address_bits = 16;
 504                 } else {
 505                         eeprom->page_size = 8;
 506                         eeprom->address_bits = 8;
 507                 }
 508                 eeprom->use_eerd = false;
 509                 eeprom->use_eewr = false;
 510                 break;
 511         case e1000_82573:
 512         case e1000_82574:
 513                 eeprom->type = e1000_eeprom_spi;
 514                 eeprom->opcode_bits = 8;
 515                 eeprom->delay_usec = 1;
 516                 if (eecd & E1000_EECD_ADDR_BITS) {
 517                         eeprom->page_size = 32;
 518                         eeprom->address_bits = 16;
 519                 } else {
 520                         eeprom->page_size = 8;
 521                         eeprom->address_bits = 8;
 522                 }
 523                 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
 524                         eeprom->use_eerd = true;
 525                         eeprom->use_eewr = true;
 526
 527                         eeprom->type = e1000_eeprom_flash;
 528                         eeprom->word_size = 2048;
 529
 530                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 531                  * Flash update issue on parts which use a FLASH for NVM. */
 532                         eecd &= ~E1000_EECD_AUPDEN;
 533                         E1000_WRITE_REG(hw, EECD, eecd);
 534                 }
 535                 break;
 536         case e1000_80003es2lan:
 537                 eeprom->type = e1000_eeprom_spi;
 538                 eeprom->opcode_bits = 8;
 539                 eeprom->delay_usec = 1;
 540                 if (eecd & E1000_EECD_ADDR_BITS) {
 541                         eeprom->page_size = 32;
 542                         eeprom->address_bits = 16;
 543                 } else {
 544                         eeprom->page_size = 8;
 545                         eeprom->address_bits = 8;
 546                 }
 547                 eeprom->use_eerd = true;
 548                 eeprom->use_eewr = false;
 549                 break;
 550         case e1000_igb:
 551                 /* i210 has 4k of iNVM mapped as EEPROM */
 552                 eeprom->type = e1000_eeprom_invm;
 553                 eeprom->opcode_bits = 8;
 554                 eeprom->delay_usec = 1;
 555                 eeprom->page_size = 32;
 556                 eeprom->address_bits = 16;
 557                 eeprom->use_eerd = true;
 558                 eeprom->use_eewr = false;
 559                 break;
 560         default:
 561                 break;
 562         }
 563
 564         if (eeprom->type == e1000_eeprom_spi ||
 565             eeprom->type == e1000_eeprom_invm) {
 566                 /* eeprom_size will be an enum [0..8] that maps
 567                  * to eeprom sizes 128B to
 568                  * 32KB (incremented by powers of 2).
 569                  */
 570                 if (hw->mac_type <= e1000_82547_rev_2) {
 571                         /* Set to default value for initial eeprom read. */
 572                         eeprom->word_size = 64;
 573                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 574                                         &eeprom_size);
 575                         if (ret_val)
 576                                 return ret_val;
 577                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 578                                 >> EEPROM_SIZE_SHIFT;
 579                         /* 256B eeprom size was not supported in earlier
 580                          * hardware, so we bump eeprom_size up one to
 581                          * ensure that "1" (which maps to 256B) is never
 582                          * the result used in the shifting logic below. */
 583                         if (eeprom_size)
 584                                 eeprom_size++;
 585                 } else {
 586                         eeprom_size = (uint16_t)((eecd &
 587                                 E1000_EECD_SIZE_EX_MASK) >>
 588                                 E1000_EECD_SIZE_EX_SHIFT);
 589                 }
 590
 591                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 592         }
 593         return ret_val;
 594 }
 595
 596 /******************************************************************************
 597  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 598  *
 599  * hw - Struct containing variables accessed by shared code
 600  *****************************************************************************/
 601 static int32_t
 602 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 603 {
 604         uint32_t attempts = 100000;
 605         uint32_t i, reg = 0;
 606         int32_t done = E1000_ERR_EEPROM;
 607
 608         for (i = 0; i < attempts; i++) {
 609                 if (eerd == E1000_EEPROM_POLL_READ) {
 610                         if (hw->mac_type == e1000_igb)
 611                                 reg = E1000_READ_REG(hw, I210_EERD);
 612                         else
 613                                 reg = E1000_READ_REG(hw, EERD);
 614                 } else {
 615                         if (hw->mac_type == e1000_igb)
 616                                 reg = E1000_READ_REG(hw, I210_EEWR);
 617                         else
 618                                 reg = E1000_READ_REG(hw, EEWR);
 619                 }
 620
 621                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 622                         done = E1000_SUCCESS;
 623                         break;
 624                 }
 625                 udelay(5);
 626         }
 627
 628         return done;
 629 }
 630
 631 /******************************************************************************
 632  * Reads a 16 bit word from the EEPROM using the EERD register.
 633  *
 634  * hw - Struct containing variables accessed by shared code
 635  * offset - offset of  word in the EEPROM to read
 636  * data - word read from the EEPROM
 637  * words - number of words to read
 638  *****************************************************************************/
 639 static int32_t
 640 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 641                         uint16_t offset,
 642                         uint16_t words,
 643                         uint16_t *data)
 644 {
 645         uint32_t i, eerd = 0;
 646         int32_t error = 0;
 647
 648         for (i = 0; i < words; i++) {
 649                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 650                         E1000_EEPROM_RW_REG_START;
 651
 652                 if (hw->mac_type == e1000_igb)
 653                         E1000_WRITE_REG(hw, I210_EERD, eerd);
 654                 else
 655                         E1000_WRITE_REG(hw, EERD, eerd);
 656
 657                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 658
 659                 if (error)
 660                         break;
 661
 662                 if (hw->mac_type == e1000_igb) {
 663                         data[i] = (E1000_READ_REG(hw, I210_EERD) >>
 664                                 E1000_EEPROM_RW_REG_DATA);
 665                 } else {
 666                         data[i] = (E1000_READ_REG(hw, EERD) >>
 667                                 E1000_EEPROM_RW_REG_DATA);
 668                 }
 669
 670         }
 671
 672         return error;
 673 }
 674
 675 void e1000_release_eeprom(struct e1000_hw *hw)
 676 {
 677         uint32_t eecd;
 678
 679         DEBUGFUNC();
 680
 681         eecd = E1000_READ_REG(hw, EECD);
 682
 683         if (hw->eeprom.type == e1000_eeprom_spi) {
 684                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 685                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 686
 687                 E1000_WRITE_REG(hw, EECD, eecd);
 688
 689                 udelay(hw->eeprom.delay_usec);
 690         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 691                 /* cleanup eeprom */
 692
 693                 /* CS on Microwire is active-high */
 694                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 695
 696                 E1000_WRITE_REG(hw, EECD, eecd);
 697
 698                 /* Rising edge of clock */
 699                 eecd |= E1000_EECD_SK;
 700                 E1000_WRITE_REG(hw, EECD, eecd);
 701                 E1000_WRITE_FLUSH(hw);
 702                 udelay(hw->eeprom.delay_usec);
 703
 704                 /* Falling edge of clock */
 705                 eecd &= ~E1000_EECD_SK;
 706                 E1000_WRITE_REG(hw, EECD, eecd);
 707                 E1000_WRITE_FLUSH(hw);
 708                 udelay(hw->eeprom.delay_usec);
 709         }
 710
 711         /* Stop requesting EEPROM access */
 712         if (hw->mac_type > e1000_82544) {
 713                 eecd &= ~E1000_EECD_REQ;
 714                 E1000_WRITE_REG(hw, EECD, eecd);
 715         }
 716
 717         e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 718 }
 719
 720 /******************************************************************************
 721  * Reads a 16 bit word from the EEPROM.
 722  *
 723  * hw - Struct containing variables accessed by shared code
 724  *****************************************************************************/
 725 static int32_t
 726 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 727 {
 728         uint16_t retry_count = 0;
 729         uint8_t spi_stat_reg;
 730
 731         DEBUGFUNC();
 732
 733         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 734          * EEPROM will signal that the command has been completed by clearing
 735          * bit 0 of the internal status register.  If it's not cleared within
 736          * 5 milliseconds, then error out.
 737          */
 738         retry_count = 0;
 739         do {
 740                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 741                         hw->eeprom.opcode_bits);
 742                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 743                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 744                         break;
 745
 746                 udelay(5);
 747                 retry_count += 5;
 748
 749                 e1000_standby_eeprom(hw);
 750         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 751
 752         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 753          * only 0-5mSec on 5V devices)
 754          */
 755         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 756                 DEBUGOUT("SPI EEPROM Status error\n");
 757                 return -E1000_ERR_EEPROM;
 758         }
 759
 760         return E1000_SUCCESS;
 761 }
 762
 763 /******************************************************************************
 764  * Reads a 16 bit word from the EEPROM.
 765  *
 766  * hw - Struct containing variables accessed by shared code
 767  * offset - offset of  word in the EEPROM to read
 768  * data - word read from the EEPROM
 769  *****************************************************************************/
 770 static int32_t
 771 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 772                 uint16_t words, uint16_t *data)
 773 {
 774         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 775         uint32_t i = 0;
 776
 777         DEBUGFUNC();
 778
 779         /* If eeprom is not yet detected, do so now */
 780         if (eeprom->word_size == 0)
 781                 e1000_init_eeprom_params(hw);
 782
 783         /* A check for invalid values:  offset too large, too many words,
 784          * and not enough words.
 785          */
 786         if ((offset >= eeprom->word_size) ||
 787                 (words > eeprom->word_size - offset) ||
 788                 (words == 0)) {
 789                 DEBUGOUT("\"words\" parameter out of bounds."
 790                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 791                 return -E1000_ERR_EEPROM;
 792         }
 793
 794         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 795          * directly. In this case, we need to acquire the EEPROM so that
 796          * FW or other port software does not interrupt.
 797          */
 798         if (e1000_is_onboard_nvm_eeprom(hw) == true &&
 799                 hw->eeprom.use_eerd == false) {
 800
 801                 /* Prepare the EEPROM for bit-bang reading */
 802                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 803                         return -E1000_ERR_EEPROM;
 804         }
 805
 806         /* Eerd register EEPROM access requires no eeprom aquire/release */
 807         if (eeprom->use_eerd == true)
 808                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 809
 810         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 811          * acquired the EEPROM at this point, so any returns should relase it */
 812         if (eeprom->type == e1000_eeprom_spi) {
 813                 uint16_t word_in;
 814                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 815
 816                 if (e1000_spi_eeprom_ready(hw)) {
 817                         e1000_release_eeprom(hw);
 818                         return -E1000_ERR_EEPROM;
 819                 }
 820
 821                 e1000_standby_eeprom(hw);
 822
 823                 /* Some SPI eeproms use the 8th address bit embedded in
 824                  * the opcode */
 825                 if ((eeprom->address_bits == 8) && (offset >= 128))
 826                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 827
 828                 /* Send the READ command (opcode + addr)  */
 829                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 830                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 831                                 eeprom->address_bits);
 832
 833                 /* Read the data.  The address of the eeprom internally
 834                  * increments with each byte (spi) being read, saving on the
 835                  * overhead of eeprom setup and tear-down.  The address
 836                  * counter will roll over if reading beyond the size of
 837                  * the eeprom, thus allowing the entire memory to be read
 838                  * starting from any offset. */
 839                 for (i = 0; i < words; i++) {
 840                         word_in = e1000_shift_in_ee_bits(hw, 16);
 841                         data[i] = (word_in >> 8) | (word_in << 8);
 842                 }
 843         } else if (eeprom->type == e1000_eeprom_microwire) {
 844                 for (i = 0; i < words; i++) {
 845                         /* Send the READ command (opcode + addr)  */
 846                         e1000_shift_out_ee_bits(hw,
 847                                 EEPROM_READ_OPCODE_MICROWIRE,
 848                                 eeprom->opcode_bits);
 849                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 850                                 eeprom->address_bits);
 851
 852                         /* Read the data.  For microwire, each word requires
 853                          * the overhead of eeprom setup and tear-down. */
 854                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 855                         e1000_standby_eeprom(hw);
 856                 }
 857         }
 858
 859         /* End this read operation */
 860         e1000_release_eeprom(hw);
 861
 862         return E1000_SUCCESS;
 863 }
 864
 865 #ifndef CONFIG_DM_ETH
 866 /******************************************************************************
 867  *  e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
 868  *  @hw: pointer to the HW structure
 869  *  @offset: offset within the Shadow Ram to be written to
 870  *  @words: number of words to write
 871  *  @data: 16 bit word(s) to be written to the Shadow Ram
 872  *
 873  *  Writes data to Shadow Ram at offset using EEWR register.
 874  *
 875  *  If e1000_update_eeprom_checksum_i210 is not called after this function, the
 876  *  Shadow Ram will most likely contain an invalid checksum.
 877  *****************************************************************************/
 878 static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
 879                                        uint16_t words, uint16_t *data)
 880 {
 881         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 882         uint32_t i, k, eewr = 0;
 883         uint32_t attempts = 100000;
 884         int32_t ret_val = 0;
 885
 886         /* A check for invalid values:  offset too large, too many words,
 887          * too many words for the offset, and not enough words.
 888          */
 889         if ((offset >= eeprom->word_size) ||
 890             (words > (eeprom->word_size - offset)) || (words == 0)) {
 891                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 892                 ret_val = -E1000_ERR_EEPROM;
 893                 goto out;
 894         }
 895
 896         for (i = 0; i < words; i++) {
 897                 eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
 898                                 | (data[i] << E1000_EEPROM_RW_REG_DATA) |
 899                                 E1000_EEPROM_RW_REG_START;
 900
 901                 E1000_WRITE_REG(hw, I210_EEWR, eewr);
 902
 903                 for (k = 0; k < attempts; k++) {
 904                         if (E1000_EEPROM_RW_REG_DONE &
 905                             E1000_READ_REG(hw, I210_EEWR)) {
 906                                 ret_val = 0;
 907                                 break;
 908                         }
 909                         udelay(5);
 910                 }
 911
 912                 if (ret_val) {
 913                         DEBUGOUT("Shadow RAM write EEWR timed out\n");
 914                         break;
 915                 }
 916         }
 917
 918 out:
 919         return ret_val;
 920 }
 921
 922 /******************************************************************************
 923  *  e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
 924  *  @hw: pointer to the HW structure
 925  *
 926  *****************************************************************************/
 927 static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
 928 {
 929         int32_t ret_val = -E1000_ERR_EEPROM;
 930         uint32_t i, reg;
 931
 932         for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
 933                 reg = E1000_READ_REG(hw, EECD);
 934                 if (reg & E1000_EECD_FLUDONE_I210) {
 935                         ret_val = 0;
 936                         break;
 937                 }
 938                 udelay(5);
 939         }
 940
 941         return ret_val;
 942 }
 943
 944 /******************************************************************************
 945  *  e1000_update_flash_i210 - Commit EEPROM to the flash
 946  *  @hw: pointer to the HW structure
 947  *
 948  *****************************************************************************/
 949 static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
 950 {
 951         int32_t ret_val = 0;
 952         uint32_t flup;
 953
 954         ret_val = e1000_pool_flash_update_done_i210(hw);
 955         if (ret_val == -E1000_ERR_EEPROM) {
 956                 DEBUGOUT("Flash update time out\n");
 957                 goto out;
 958         }
 959
 960         flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
 961         E1000_WRITE_REG(hw, EECD, flup);
 962
 963         ret_val = e1000_pool_flash_update_done_i210(hw);
 964         if (ret_val)
 965                 DEBUGOUT("Flash update time out\n");
 966         else
 967                 DEBUGOUT("Flash update complete\n");
 968
 969 out:
 970         return ret_val;
 971 }
 972
 973 /******************************************************************************
 974  *  e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
 975  *  @hw: pointer to the HW structure
 976  *
 977  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 978  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 979  *  value to the EEPROM. Next commit EEPROM data onto the Flash.
 980  *****************************************************************************/
 981 static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
 982 {
 983         int32_t ret_val = 0;
 984         uint16_t checksum = 0;
 985         uint16_t i, nvm_data;
 986
 987         /* Read the first word from the EEPROM. If this times out or fails, do
 988          * not continue or we could be in for a very long wait while every
 989          * EEPROM read fails
 990          */
 991         ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
 992         if (ret_val) {
 993                 DEBUGOUT("EEPROM read failed\n");
 994                 goto out;
 995         }
 996
 997         if (!(e1000_get_hw_eeprom_semaphore(hw))) {
 998                 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
 999                  * because we do not want to take the synchronization
1000                  * semaphores twice here.
1001                  */
1002
1003                 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
1004                         ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
1005                         if (ret_val) {
1006                                 e1000_put_hw_eeprom_semaphore(hw);
1007                                 DEBUGOUT("EEPROM Read Error while updating checksum.\n");
1008                                 goto out;
1009                         }
1010                         checksum += nvm_data;
1011                 }
1012                 checksum = (uint16_t)EEPROM_SUM - checksum;
1013                 ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
1014                                                   &checksum);
1015                 if (ret_val) {
1016                         e1000_put_hw_eeprom_semaphore(hw);
1017                         DEBUGOUT("EEPROM Write Error while updating checksum.\n");
1018                         goto out;
1019                 }
1020
1021                 e1000_put_hw_eeprom_semaphore(hw);
1022
1023                 ret_val = e1000_update_flash_i210(hw);
1024         } else {
1025                 ret_val = -E1000_ERR_SWFW_SYNC;
1026         }
1027
1028 out:
1029         return ret_val;
1030 }
1031 #endif
1032
1033 /******************************************************************************
1034  * Verifies that the EEPROM has a valid checksum
1035  *
1036  * hw - Struct containing variables accessed by shared code
1037  *
1038  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
1039  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
1040  * valid.
1041  *****************************************************************************/
1042 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
1043 {
1044         uint16_t i, checksum, checksum_reg, *buf;
1045
1046         DEBUGFUNC();
1047
1048         /* Allocate a temporary buffer */
1049         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
1050         if (!buf) {
1051                 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
1052                 return -E1000_ERR_EEPROM;
1053         }
1054
1055         /* Read the EEPROM */
1056         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
1057                 E1000_ERR(hw, "Unable to read EEPROM!\n");
1058                 return -E1000_ERR_EEPROM;
1059         }
1060
1061         /* Compute the checksum */
1062         checksum = 0;
1063         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1064                 checksum += buf[i];
1065         checksum = ((uint16_t)EEPROM_SUM) - checksum;
1066         checksum_reg = buf[i];
1067
1068         /* Verify it! */
1069         if (checksum == checksum_reg)
1070                 return 0;
1071
1072         /* Hrm, verification failed, print an error */
1073         E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
1074         E1000_ERR(hw, "  ...register was 0x%04hx, calculated 0x%04hx\n",
1075                   checksum_reg, checksum);
1076
1077         return -E1000_ERR_EEPROM;
1078 }
1079 #endif /* CONFIG_E1000_NO_NVM */
1080
1081 /*****************************************************************************
1082  * Set PHY to class A mode
1083  * Assumes the following operations will follow to enable the new class mode.
1084  *  1. Do a PHY soft reset
1085  *  2. Restart auto-negotiation or force link.
1086  *
1087  * hw - Struct containing variables accessed by shared code
1088  ****************************************************************************/
1089 static int32_t
1090 e1000_set_phy_mode(struct e1000_hw *hw)
1091 {
1092 #ifndef CONFIG_E1000_NO_NVM
1093         int32_t ret_val;
1094         uint16_t eeprom_data;
1095
1096         DEBUGFUNC();
1097
1098         if ((hw->mac_type == e1000_82545_rev_3) &&
1099                 (hw->media_type == e1000_media_type_copper)) {
1100                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1101                                 1, &eeprom_data);
1102                 if (ret_val)
1103                         return ret_val;
1104
1105                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
1106                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
1107                         ret_val = e1000_write_phy_reg(hw,
1108                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
1109                         if (ret_val)
1110                                 return ret_val;
1111                         ret_val = e1000_write_phy_reg(hw,
1112                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
1113                         if (ret_val)
1114                                 return ret_val;
1115
1116                         hw->phy_reset_disable = false;
1117                 }
1118         }
1119 #endif
1120         return E1000_SUCCESS;
1121 }
1122
1123 #ifndef CONFIG_E1000_NO_NVM
1124 /***************************************************************************
1125  *
1126  * Obtaining software semaphore bit (SMBI) before resetting PHY.
1127  *
1128  * hw: Struct containing variables accessed by shared code
1129  *
1130  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
1131  *            E1000_SUCCESS at any other case.
1132  *
1133  ***************************************************************************/
1134 static int32_t
1135 e1000_get_software_semaphore(struct e1000_hw *hw)
1136 {
1137          int32_t timeout = hw->eeprom.word_size + 1;
1138          uint32_t swsm;
1139
1140         DEBUGFUNC();
1141
1142         if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
1143                 return E1000_SUCCESS;
1144
1145         while (timeout) {
1146                 swsm = E1000_READ_REG(hw, SWSM);
1147                 /* If SMBI bit cleared, it is now set and we hold
1148                  * the semaphore */
1149                 if (!(swsm & E1000_SWSM_SMBI))
1150                         break;
1151                 mdelay(1);
1152                 timeout--;
1153         }
1154
1155         if (!timeout) {
1156                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1157                 return -E1000_ERR_RESET;
1158         }
1159
1160         return E1000_SUCCESS;
1161 }
1162 #endif
1163
1164 /***************************************************************************
1165  * This function clears HW semaphore bits.
1166  *
1167  * hw: Struct containing variables accessed by shared code
1168  *
1169  * returns: - None.
1170  *
1171  ***************************************************************************/
1172 static void
1173 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1174 {
1175 #ifndef CONFIG_E1000_NO_NVM
1176          uint32_t swsm;
1177
1178         DEBUGFUNC();
1179
1180         if (!hw->eeprom_semaphore_present)
1181                 return;
1182
1183         swsm = E1000_READ_REG(hw, SWSM);
1184         if (hw->mac_type == e1000_80003es2lan) {
1185                 /* Release both semaphores. */
1186                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1187         } else
1188                 swsm &= ~(E1000_SWSM_SWESMBI);
1189         E1000_WRITE_REG(hw, SWSM, swsm);
1190 #endif
1191 }
1192
1193 /***************************************************************************
1194  *
1195  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1196  * adapter or Eeprom access.
1197  *
1198  * hw: Struct containing variables accessed by shared code
1199  *
1200  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1201  *            E1000_SUCCESS at any other case.
1202  *
1203  ***************************************************************************/
1204 static int32_t
1205 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1206 {
1207 #ifndef CONFIG_E1000_NO_NVM
1208         int32_t timeout;
1209         uint32_t swsm;
1210
1211         DEBUGFUNC();
1212
1213         if (!hw->eeprom_semaphore_present)
1214                 return E1000_SUCCESS;
1215
1216         if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1217                 /* Get the SW semaphore. */
1218                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1219                         return -E1000_ERR_EEPROM;
1220         }
1221
1222         /* Get the FW semaphore. */
1223         timeout = hw->eeprom.word_size + 1;
1224         while (timeout) {
1225                 swsm = E1000_READ_REG(hw, SWSM);
1226                 swsm |= E1000_SWSM_SWESMBI;
1227                 E1000_WRITE_REG(hw, SWSM, swsm);
1228                 /* if we managed to set the bit we got the semaphore. */
1229                 swsm = E1000_READ_REG(hw, SWSM);
1230                 if (swsm & E1000_SWSM_SWESMBI)
1231                         break;
1232
1233                 udelay(50);
1234                 timeout--;
1235         }
1236
1237         if (!timeout) {
1238                 /* Release semaphores */
1239                 e1000_put_hw_eeprom_semaphore(hw);
1240                 DEBUGOUT("Driver can't access the Eeprom - "
1241                                 "SWESMBI bit is set.\n");
1242                 return -E1000_ERR_EEPROM;
1243         }
1244 #endif
1245         return E1000_SUCCESS;
1246 }
1247
1248 /* Take ownership of the PHY */
1249 static int32_t
1250 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1251 {
1252         uint32_t swfw_sync = 0;
1253         uint32_t swmask = mask;
1254         uint32_t fwmask = mask << 16;
1255         int32_t timeout = 200;
1256
1257         DEBUGFUNC();
1258         while (timeout) {
1259                 if (e1000_get_hw_eeprom_semaphore(hw))
1260                         return -E1000_ERR_SWFW_SYNC;
1261
1262                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1263                 if (!(swfw_sync & (fwmask | swmask)))
1264                         break;
1265
1266                 /* firmware currently using resource (fwmask) */
1267                 /* or other software thread currently using resource (swmask) */
1268                 e1000_put_hw_eeprom_semaphore(hw);
1269                 mdelay(5);
1270                 timeout--;
1271         }
1272
1273         if (!timeout) {
1274                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1275                 return -E1000_ERR_SWFW_SYNC;
1276         }
1277
1278         swfw_sync |= swmask;
1279         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1280
1281         e1000_put_hw_eeprom_semaphore(hw);
1282         return E1000_SUCCESS;
1283 }
1284
1285 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1286 {
1287         uint32_t swfw_sync = 0;
1288
1289         DEBUGFUNC();
1290         while (e1000_get_hw_eeprom_semaphore(hw))
1291                 ; /* Empty */
1292
1293         swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1294         swfw_sync &= ~mask;
1295         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1296
1297         e1000_put_hw_eeprom_semaphore(hw);
1298 }
1299
1300 static bool e1000_is_second_port(struct e1000_hw *hw)
1301 {
1302         switch (hw->mac_type) {
1303         case e1000_80003es2lan:
1304         case e1000_82546:
1305         case e1000_82571:
1306                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1307                         return true;
1308                 /* Fallthrough */
1309         default:
1310                 return false;
1311         }
1312 }
1313
1314 #ifndef CONFIG_E1000_NO_NVM
1315 /******************************************************************************
1316  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1317  * second function of dual function devices
1318  *
1319  * nic - Struct containing variables accessed by shared code
1320  *****************************************************************************/
1321 static int
1322 e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1323 {
1324         uint16_t offset;
1325         uint16_t eeprom_data;
1326         uint32_t reg_data = 0;
1327         int i;
1328
1329         DEBUGFUNC();
1330
1331         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1332                 offset = i >> 1;
1333                 if (hw->mac_type == e1000_igb) {
1334                         /* i210 preloads MAC address into RAL/RAH registers */
1335                         if (offset == 0)
1336                                 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1337                         else if (offset == 1)
1338                                 reg_data >>= 16;
1339                         else if (offset == 2)
1340                                 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1341                         eeprom_data = reg_data & 0xffff;
1342                 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1343                         DEBUGOUT("EEPROM Read Error\n");
1344                         return -E1000_ERR_EEPROM;
1345                 }
1346                 enetaddr[i] = eeprom_data & 0xff;
1347                 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1348         }
1349
1350         /* Invert the last bit if this is the second device */
1351         if (e1000_is_second_port(hw))
1352                 enetaddr[5] ^= 1;
1353
1354         return 0;
1355 }
1356 #endif
1357
1358 /******************************************************************************
1359  * Initializes receive address filters.
1360  *
1361  * hw - Struct containing variables accessed by shared code
1362  *
1363  * Places the MAC address in receive address register 0 and clears the rest
1364  * of the receive addresss registers. Clears the multicast table. Assumes
1365  * the receiver is in reset when the routine is called.
1366  *****************************************************************************/
1367 static void
1368 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
1369 {
1370         uint32_t i;
1371         uint32_t addr_low;
1372         uint32_t addr_high;
1373
1374         DEBUGFUNC();
1375
1376         /* Setup the receive address. */
1377         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1378         addr_low = (enetaddr[0] |
1379                     (enetaddr[1] << 8) |
1380                     (enetaddr[2] << 16) | (enetaddr[3] << 24));
1381
1382         addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
1383
1384         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1385         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1386
1387         /* Zero out the other 15 receive addresses. */
1388         DEBUGOUT("Clearing RAR[1-15]\n");
1389         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1390                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1391                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1392         }
1393 }
1394
1395 /******************************************************************************
1396  * Clears the VLAN filer table
1397  *
1398  * hw - Struct containing variables accessed by shared code
1399  *****************************************************************************/
1400 static void
1401 e1000_clear_vfta(struct e1000_hw *hw)
1402 {
1403         uint32_t offset;
1404
1405         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1406                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1407 }
1408
1409 /******************************************************************************
1410  * Set the mac type member in the hw struct.
1411  *
1412  * hw - Struct containing variables accessed by shared code
1413  *****************************************************************************/
1414 int32_t
1415 e1000_set_mac_type(struct e1000_hw *hw)
1416 {
1417         DEBUGFUNC();
1418
1419         switch (hw->device_id) {
1420         case E1000_DEV_ID_82542:
1421                 switch (hw->revision_id) {
1422                 case E1000_82542_2_0_REV_ID:
1423                         hw->mac_type = e1000_82542_rev2_0;
1424                         break;
1425                 case E1000_82542_2_1_REV_ID:
1426                         hw->mac_type = e1000_82542_rev2_1;
1427                         break;
1428                 default:
1429                         /* Invalid 82542 revision ID */
1430                         return -E1000_ERR_MAC_TYPE;
1431                 }
1432                 break;
1433         case E1000_DEV_ID_82543GC_FIBER:
1434         case E1000_DEV_ID_82543GC_COPPER:
1435                 hw->mac_type = e1000_82543;
1436                 break;
1437         case E1000_DEV_ID_82544EI_COPPER:
1438         case E1000_DEV_ID_82544EI_FIBER:
1439         case E1000_DEV_ID_82544GC_COPPER:
1440         case E1000_DEV_ID_82544GC_LOM:
1441                 hw->mac_type = e1000_82544;
1442                 break;
1443         case E1000_DEV_ID_82540EM:
1444         case E1000_DEV_ID_82540EM_LOM:
1445         case E1000_DEV_ID_82540EP:
1446         case E1000_DEV_ID_82540EP_LOM:
1447         case E1000_DEV_ID_82540EP_LP:
1448                 hw->mac_type = e1000_82540;
1449                 break;
1450         case E1000_DEV_ID_82545EM_COPPER:
1451         case E1000_DEV_ID_82545EM_FIBER:
1452                 hw->mac_type = e1000_82545;
1453                 break;
1454         case E1000_DEV_ID_82545GM_COPPER:
1455         case E1000_DEV_ID_82545GM_FIBER:
1456         case E1000_DEV_ID_82545GM_SERDES:
1457                 hw->mac_type = e1000_82545_rev_3;
1458                 break;
1459         case E1000_DEV_ID_82546EB_COPPER:
1460         case E1000_DEV_ID_82546EB_FIBER:
1461         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1462                 hw->mac_type = e1000_82546;
1463                 break;
1464         case E1000_DEV_ID_82546GB_COPPER:
1465         case E1000_DEV_ID_82546GB_FIBER:
1466         case E1000_DEV_ID_82546GB_SERDES:
1467         case E1000_DEV_ID_82546GB_PCIE:
1468         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1469         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1470                 hw->mac_type = e1000_82546_rev_3;
1471                 break;
1472         case E1000_DEV_ID_82541EI:
1473         case E1000_DEV_ID_82541EI_MOBILE:
1474         case E1000_DEV_ID_82541ER_LOM:
1475                 hw->mac_type = e1000_82541;
1476                 break;
1477         case E1000_DEV_ID_82541ER:
1478         case E1000_DEV_ID_82541GI:
1479         case E1000_DEV_ID_82541GI_LF:
1480         case E1000_DEV_ID_82541GI_MOBILE:
1481                 hw->mac_type = e1000_82541_rev_2;
1482                 break;
1483         case E1000_DEV_ID_82547EI:
1484         case E1000_DEV_ID_82547EI_MOBILE:
1485                 hw->mac_type = e1000_82547;
1486                 break;
1487         case E1000_DEV_ID_82547GI:
1488                 hw->mac_type = e1000_82547_rev_2;
1489                 break;
1490         case E1000_DEV_ID_82571EB_COPPER:
1491         case E1000_DEV_ID_82571EB_FIBER:
1492         case E1000_DEV_ID_82571EB_SERDES:
1493         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1494         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1495         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1496         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1497         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1498         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1499                 hw->mac_type = e1000_82571;
1500                 break;
1501         case E1000_DEV_ID_82572EI_COPPER:
1502         case E1000_DEV_ID_82572EI_FIBER:
1503         case E1000_DEV_ID_82572EI_SERDES:
1504         case E1000_DEV_ID_82572EI:
1505                 hw->mac_type = e1000_82572;
1506                 break;
1507         case E1000_DEV_ID_82573E:
1508         case E1000_DEV_ID_82573E_IAMT:
1509         case E1000_DEV_ID_82573L:
1510                 hw->mac_type = e1000_82573;
1511                 break;
1512         case E1000_DEV_ID_82574L:
1513                 hw->mac_type = e1000_82574;
1514                 break;
1515         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1516         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1517         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1518         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1519                 hw->mac_type = e1000_80003es2lan;
1520                 break;
1521         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1522         case E1000_DEV_ID_ICH8_IGP_AMT:
1523         case E1000_DEV_ID_ICH8_IGP_C:
1524         case E1000_DEV_ID_ICH8_IFE:
1525         case E1000_DEV_ID_ICH8_IFE_GT:
1526         case E1000_DEV_ID_ICH8_IFE_G:
1527         case E1000_DEV_ID_ICH8_IGP_M:
1528                 hw->mac_type = e1000_ich8lan;
1529                 break;
1530         case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1531         case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1532         case PCI_DEVICE_ID_INTEL_I210_COPPER:
1533         case PCI_DEVICE_ID_INTEL_I211_COPPER:
1534         case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1535         case PCI_DEVICE_ID_INTEL_I210_SERDES:
1536         case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1537         case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1538                 hw->mac_type = e1000_igb;
1539                 break;
1540         default:
1541                 /* Should never have loaded on this device */
1542                 return -E1000_ERR_MAC_TYPE;
1543         }
1544         return E1000_SUCCESS;
1545 }
1546
1547 /******************************************************************************
1548  * Reset the transmit and receive units; mask and clear all interrupts.
1549  *
1550  * hw - Struct containing variables accessed by shared code
1551  *****************************************************************************/
1552 void
1553 e1000_reset_hw(struct e1000_hw *hw)
1554 {
1555         uint32_t ctrl;
1556         uint32_t ctrl_ext;
1557         uint32_t manc;
1558         uint32_t pba = 0;
1559         uint32_t reg;
1560
1561         DEBUGFUNC();
1562
1563         /* get the correct pba value for both PCI and PCIe*/
1564         if (hw->mac_type <  e1000_82571)
1565                 pba = E1000_DEFAULT_PCI_PBA;
1566         else
1567                 pba = E1000_DEFAULT_PCIE_PBA;
1568
1569         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1570         if (hw->mac_type == e1000_82542_rev2_0) {
1571                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1572 #ifdef CONFIG_DM_ETH
1573                 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1574                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1575 #else
1576                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1577                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1578 #endif
1579         }
1580
1581         /* Clear interrupt mask to stop board from generating interrupts */
1582         DEBUGOUT("Masking off all interrupts\n");
1583         if (hw->mac_type == e1000_igb)
1584                 E1000_WRITE_REG(hw, I210_IAM, 0);
1585         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1586
1587         /* Disable the Transmit and Receive units.  Then delay to allow
1588          * any pending transactions to complete before we hit the MAC with
1589          * the global reset.
1590          */
1591         E1000_WRITE_REG(hw, RCTL, 0);
1592         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1593         E1000_WRITE_FLUSH(hw);
1594
1595         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1596         hw->tbi_compatibility_on = false;
1597
1598         /* Delay to allow any outstanding PCI transactions to complete before
1599          * resetting the device
1600          */
1601         mdelay(10);
1602
1603         /* Issue a global reset to the MAC.  This will reset the chip's
1604          * transmit, receive, DMA, and link units.  It will not effect
1605          * the current PCI configuration.  The global reset bit is self-
1606          * clearing, and should clear within a microsecond.
1607          */
1608         DEBUGOUT("Issuing a global reset to MAC\n");
1609         ctrl = E1000_READ_REG(hw, CTRL);
1610
1611         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1612
1613         /* Force a reload from the EEPROM if necessary */
1614         if (hw->mac_type == e1000_igb) {
1615                 mdelay(20);
1616                 reg = E1000_READ_REG(hw, STATUS);
1617                 if (reg & E1000_STATUS_PF_RST_DONE)
1618                         DEBUGOUT("PF OK\n");
1619                 reg = E1000_READ_REG(hw, I210_EECD);
1620                 if (reg & E1000_EECD_AUTO_RD)
1621                         DEBUGOUT("EEC OK\n");
1622         } else if (hw->mac_type < e1000_82540) {
1623                 /* Wait for reset to complete */
1624                 udelay(10);
1625                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1626                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1627                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1628                 E1000_WRITE_FLUSH(hw);
1629                 /* Wait for EEPROM reload */
1630                 mdelay(2);
1631         } else {
1632                 /* Wait for EEPROM reload (it happens automatically) */
1633                 mdelay(4);
1634                 /* Dissable HW ARPs on ASF enabled adapters */
1635                 manc = E1000_READ_REG(hw, MANC);
1636                 manc &= ~(E1000_MANC_ARP_EN);
1637                 E1000_WRITE_REG(hw, MANC, manc);
1638         }
1639
1640         /* Clear interrupt mask to stop board from generating interrupts */
1641         DEBUGOUT("Masking off all interrupts\n");
1642         if (hw->mac_type == e1000_igb)
1643                 E1000_WRITE_REG(hw, I210_IAM, 0);
1644         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1645
1646         /* Clear any pending interrupt events. */
1647         E1000_READ_REG(hw, ICR);
1648
1649         /* If MWI was previously enabled, reenable it. */
1650         if (hw->mac_type == e1000_82542_rev2_0) {
1651 #ifdef CONFIG_DM_ETH
1652                 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1653 #else
1654                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1655 #endif
1656         }
1657         if (hw->mac_type != e1000_igb)
1658                 E1000_WRITE_REG(hw, PBA, pba);
1659 }
1660
1661 /******************************************************************************
1662  *
1663  * Initialize a number of hardware-dependent bits
1664  *
1665  * hw: Struct containing variables accessed by shared code
1666  *
1667  * This function contains hardware limitation workarounds for PCI-E adapters
1668  *
1669  *****************************************************************************/
1670 static void
1671 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1672 {
1673         if ((hw->mac_type >= e1000_82571) &&
1674                         (!hw->initialize_hw_bits_disable)) {
1675                 /* Settings common to all PCI-express silicon */
1676                 uint32_t reg_ctrl, reg_ctrl_ext;
1677                 uint32_t reg_tarc0, reg_tarc1;
1678                 uint32_t reg_tctl;
1679                 uint32_t reg_txdctl, reg_txdctl1;
1680
1681                 /* link autonegotiation/sync workarounds */
1682                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1683                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1684
1685                 /* Enable not-done TX descriptor counting */
1686                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1687                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1688                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1689
1690                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1691                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1692                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1693
1694
1695                 switch (hw->mac_type) {
1696                 case e1000_igb:                 /* IGB is cool */
1697                         return;
1698                 case e1000_82571:
1699                 case e1000_82572:
1700                         /* Clear PHY TX compatible mode bits */
1701                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1702                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1703
1704                         /* link autonegotiation/sync workarounds */
1705                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1706
1707                         /* TX ring control fixes */
1708                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1709
1710                         /* Multiple read bit is reversed polarity */
1711                         reg_tctl = E1000_READ_REG(hw, TCTL);
1712                         if (reg_tctl & E1000_TCTL_MULR)
1713                                 reg_tarc1 &= ~(1 << 28);
1714                         else
1715                                 reg_tarc1 |= (1 << 28);
1716
1717                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1718                         break;
1719                 case e1000_82573:
1720                 case e1000_82574:
1721                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1722                         reg_ctrl_ext &= ~(1 << 23);
1723                         reg_ctrl_ext |= (1 << 22);
1724
1725                         /* TX byte count fix */
1726                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1727                         reg_ctrl &= ~(1 << 29);
1728
1729                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1730                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1731                         break;
1732                 case e1000_80003es2lan:
1733         /* improve small packet performace for fiber/serdes */
1734                         if ((hw->media_type == e1000_media_type_fiber)
1735                         || (hw->media_type ==
1736                                 e1000_media_type_internal_serdes)) {
1737                                 reg_tarc0 &= ~(1 << 20);
1738                         }
1739
1740                 /* Multiple read bit is reversed polarity */
1741                         reg_tctl = E1000_READ_REG(hw, TCTL);
1742                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1743                         if (reg_tctl & E1000_TCTL_MULR)
1744                                 reg_tarc1 &= ~(1 << 28);
1745                         else
1746                                 reg_tarc1 |= (1 << 28);
1747
1748                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1749                         break;
1750                 case e1000_ich8lan:
1751                         /* Reduce concurrent DMA requests to 3 from 4 */
1752                         if ((hw->revision_id < 3) ||
1753                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1754                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1755                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1756
1757                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1758                         reg_ctrl_ext |= (1 << 22);
1759                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1760
1761                         /* workaround TX hang with TSO=on */
1762                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1763
1764                         /* Multiple read bit is reversed polarity */
1765                         reg_tctl = E1000_READ_REG(hw, TCTL);
1766                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1767                         if (reg_tctl & E1000_TCTL_MULR)
1768                                 reg_tarc1 &= ~(1 << 28);
1769                         else
1770                                 reg_tarc1 |= (1 << 28);
1771
1772                         /* workaround TX hang with TSO=on */
1773                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1774
1775                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1776                         break;
1777                 default:
1778                         break;
1779                 }
1780
1781                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1782         }
1783 }
1784
1785 /******************************************************************************
1786  * Performs basic configuration of the adapter.
1787  *
1788  * hw - Struct containing variables accessed by shared code
1789  *
1790  * Assumes that the controller has previously been reset and is in a
1791  * post-reset uninitialized state. Initializes the receive address registers,
1792  * multicast table, and VLAN filter table. Calls routines to setup link
1793  * configuration and flow control settings. Clears all on-chip counters. Leaves
1794  * the transmit and receive units disabled and uninitialized.
1795  *****************************************************************************/
1796 static int
1797 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
1798 {
1799         uint32_t ctrl;
1800         uint32_t i;
1801         int32_t ret_val;
1802         uint16_t pcix_cmd_word;
1803         uint16_t pcix_stat_hi_word;
1804         uint16_t cmd_mmrbc;
1805         uint16_t stat_mmrbc;
1806         uint32_t mta_size;
1807         uint32_t reg_data;
1808         uint32_t ctrl_ext;
1809         DEBUGFUNC();
1810         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1811         if ((hw->mac_type == e1000_ich8lan) &&
1812                 ((hw->revision_id < 3) ||
1813                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1814                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1815                         reg_data = E1000_READ_REG(hw, STATUS);
1816                         reg_data &= ~0x80000000;
1817                         E1000_WRITE_REG(hw, STATUS, reg_data);
1818         }
1819         /* Do not need initialize Identification LED */
1820
1821         /* Set the media type and TBI compatibility */
1822         e1000_set_media_type(hw);
1823
1824         /* Must be called after e1000_set_media_type
1825          * because media_type is used */
1826         e1000_initialize_hardware_bits(hw);
1827
1828         /* Disabling VLAN filtering. */
1829         DEBUGOUT("Initializing the IEEE VLAN\n");
1830         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1831         if (hw->mac_type != e1000_ich8lan) {
1832                 if (hw->mac_type < e1000_82545_rev_3)
1833                         E1000_WRITE_REG(hw, VET, 0);
1834                 e1000_clear_vfta(hw);
1835         }
1836
1837         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1838         if (hw->mac_type == e1000_82542_rev2_0) {
1839                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1840 #ifdef CONFIG_DM_ETH
1841                 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1842                                       hw->
1843                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1844 #else
1845                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1846                                       hw->
1847                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1848 #endif
1849                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1850                 E1000_WRITE_FLUSH(hw);
1851                 mdelay(5);
1852         }
1853
1854         /* Setup the receive address. This involves initializing all of the Receive
1855          * Address Registers (RARs 0 - 15).
1856          */
1857         e1000_init_rx_addrs(hw, enetaddr);
1858
1859         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1860         if (hw->mac_type == e1000_82542_rev2_0) {
1861                 E1000_WRITE_REG(hw, RCTL, 0);
1862                 E1000_WRITE_FLUSH(hw);
1863                 mdelay(1);
1864 #ifdef CONFIG_DM_ETH
1865                 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1866 #else
1867                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1868 #endif
1869         }
1870
1871         /* Zero out the Multicast HASH table */
1872         DEBUGOUT("Zeroing the MTA\n");
1873         mta_size = E1000_MC_TBL_SIZE;
1874         if (hw->mac_type == e1000_ich8lan)
1875                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1876         for (i = 0; i < mta_size; i++) {
1877                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1878                 /* use write flush to prevent Memory Write Block (MWB) from
1879                  * occuring when accessing our register space */
1880                 E1000_WRITE_FLUSH(hw);
1881         }
1882
1883         switch (hw->mac_type) {
1884         case e1000_82545_rev_3:
1885         case e1000_82546_rev_3:
1886         case e1000_igb:
1887                 break;
1888         default:
1889         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1890         if (hw->bus_type == e1000_bus_type_pcix) {
1891 #ifdef CONFIG_DM_ETH
1892                 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1893                                      &pcix_cmd_word);
1894                 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
1895                                      &pcix_stat_hi_word);
1896 #else
1897                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1898                                      &pcix_cmd_word);
1899                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1900                                      &pcix_stat_hi_word);
1901 #endif
1902                 cmd_mmrbc =
1903                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1904                     PCIX_COMMAND_MMRBC_SHIFT;
1905                 stat_mmrbc =
1906                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1907                     PCIX_STATUS_HI_MMRBC_SHIFT;
1908                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1909                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1910                 if (cmd_mmrbc > stat_mmrbc) {
1911                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1912                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1913 #ifdef CONFIG_DM_ETH
1914                         dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1915                                               pcix_cmd_word);
1916 #else
1917                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1918                                               pcix_cmd_word);
1919 #endif
1920                 }
1921         }
1922                 break;
1923         }
1924
1925         /* More time needed for PHY to initialize */
1926         if (hw->mac_type == e1000_ich8lan)
1927                 mdelay(15);
1928         if (hw->mac_type == e1000_igb)
1929                 mdelay(15);
1930
1931         /* Call a subroutine to configure the link and setup flow control. */
1932         ret_val = e1000_setup_link(hw);
1933
1934         /* Set the transmit descriptor write-back policy */
1935         if (hw->mac_type > e1000_82544) {
1936                 ctrl = E1000_READ_REG(hw, TXDCTL);
1937                 ctrl =
1938                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1939                     E1000_TXDCTL_FULL_TX_DESC_WB;
1940                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1941         }
1942
1943         /* Set the receive descriptor write back policy */
1944         if (hw->mac_type >= e1000_82571) {
1945                 ctrl = E1000_READ_REG(hw, RXDCTL);
1946                 ctrl =
1947                     (ctrl & ~E1000_RXDCTL_WTHRESH) |
1948                     E1000_RXDCTL_FULL_RX_DESC_WB;
1949                 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1950         }
1951
1952         switch (hw->mac_type) {
1953         default:
1954                 break;
1955         case e1000_80003es2lan:
1956                 /* Enable retransmit on late collisions */
1957                 reg_data = E1000_READ_REG(hw, TCTL);
1958                 reg_data |= E1000_TCTL_RTLC;
1959                 E1000_WRITE_REG(hw, TCTL, reg_data);
1960
1961                 /* Configure Gigabit Carry Extend Padding */
1962                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1963                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1964                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1965                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1966
1967                 /* Configure Transmit Inter-Packet Gap */
1968                 reg_data = E1000_READ_REG(hw, TIPG);
1969                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1970                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1971                 E1000_WRITE_REG(hw, TIPG, reg_data);
1972
1973                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1974                 reg_data &= ~0x00100000;
1975                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1976                 /* Fall through */
1977         case e1000_82571:
1978         case e1000_82572:
1979         case e1000_ich8lan:
1980                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1981                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1982                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1983                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1984                 break;
1985         case e1000_82573:
1986         case e1000_82574:
1987                 reg_data = E1000_READ_REG(hw, GCR);
1988                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1989                 E1000_WRITE_REG(hw, GCR, reg_data);
1990         case e1000_igb:
1991                 break;
1992         }
1993
1994         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1995                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1996                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1997                 /* Relaxed ordering must be disabled to avoid a parity
1998                  * error crash in a PCI slot. */
1999                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2000                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2001         }
2002
2003         return ret_val;
2004 }
2005
2006 /******************************************************************************
2007  * Configures flow control and link settings.
2008  *
2009  * hw - Struct containing variables accessed by shared code
2010  *
2011  * Determines which flow control settings to use. Calls the apropriate media-
2012  * specific link configuration function. Configures the flow control settings.
2013  * Assuming the adapter has a valid link partner, a valid link should be
2014  * established. Assumes the hardware has previously been reset and the
2015  * transmitter and receiver are not enabled.
2016  *****************************************************************************/
2017 static int
2018 e1000_setup_link(struct e1000_hw *hw)
2019 {
2020         int32_t ret_val;
2021 #ifndef CONFIG_E1000_NO_NVM
2022         uint32_t ctrl_ext;
2023         uint16_t eeprom_data;
2024 #endif
2025
2026         DEBUGFUNC();
2027
2028         /* In the case of the phy reset being blocked, we already have a link.
2029          * We do not have to set it up again. */
2030         if (e1000_check_phy_reset_block(hw))
2031                 return E1000_SUCCESS;
2032
2033 #ifndef CONFIG_E1000_NO_NVM
2034         /* Read and store word 0x0F of the EEPROM. This word contains bits
2035          * that determine the hardware's default PAUSE (flow control) mode,
2036          * a bit that determines whether the HW defaults to enabling or
2037          * disabling auto-negotiation, and the direction of the
2038          * SW defined pins. If there is no SW over-ride of the flow
2039          * control setting, then the variable hw->fc will
2040          * be initialized based on a value in the EEPROM.
2041          */
2042         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
2043                                 &eeprom_data) < 0) {
2044                 DEBUGOUT("EEPROM Read Error\n");
2045                 return -E1000_ERR_EEPROM;
2046         }
2047 #endif
2048         if (hw->fc == e1000_fc_default) {
2049                 switch (hw->mac_type) {
2050                 case e1000_ich8lan:
2051                 case e1000_82573:
2052                 case e1000_82574:
2053                 case e1000_igb:
2054                         hw->fc = e1000_fc_full;
2055                         break;
2056                 default:
2057 #ifndef CONFIG_E1000_NO_NVM
2058                         ret_val = e1000_read_eeprom(hw,
2059                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
2060                         if (ret_val) {
2061                                 DEBUGOUT("EEPROM Read Error\n");
2062                                 return -E1000_ERR_EEPROM;
2063                         }
2064                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
2065                                 hw->fc = e1000_fc_none;
2066                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
2067                                     EEPROM_WORD0F_ASM_DIR)
2068                                 hw->fc = e1000_fc_tx_pause;
2069                         else
2070 #endif
2071                                 hw->fc = e1000_fc_full;
2072                         break;
2073                 }
2074         }
2075
2076         /* We want to save off the original Flow Control configuration just
2077          * in case we get disconnected and then reconnected into a different
2078          * hub or switch with different Flow Control capabilities.
2079          */
2080         if (hw->mac_type == e1000_82542_rev2_0)
2081                 hw->fc &= (~e1000_fc_tx_pause);
2082
2083         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
2084                 hw->fc &= (~e1000_fc_rx_pause);
2085
2086         hw->original_fc = hw->fc;
2087
2088         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
2089
2090 #ifndef CONFIG_E1000_NO_NVM
2091         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
2092          * polarity value for the SW controlled pins, and setup the
2093          * Extended Device Control reg with that info.
2094          * This is needed because one of the SW controlled pins is used for
2095          * signal detection.  So this should be done before e1000_setup_pcs_link()
2096          * or e1000_phy_setup() is called.
2097          */
2098         if (hw->mac_type == e1000_82543) {
2099                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
2100                             SWDPIO__EXT_SHIFT);
2101                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2102         }
2103 #endif
2104
2105         /* Call the necessary subroutine to configure the link. */
2106         ret_val = (hw->media_type == e1000_media_type_fiber) ?
2107             e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
2108         if (ret_val < 0) {
2109                 return ret_val;
2110         }
2111
2112         /* Initialize the flow control address, type, and PAUSE timer
2113          * registers to their default values.  This is done even if flow
2114          * control is disabled, because it does not hurt anything to
2115          * initialize these registers.
2116          */
2117         DEBUGOUT("Initializing the Flow Control address, type"
2118                         "and timer regs\n");
2119
2120         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
2121         if (hw->mac_type != e1000_ich8lan) {
2122                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
2123                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
2124                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
2125         }
2126
2127         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
2128
2129         /* Set the flow control receive threshold registers.  Normally,
2130          * these registers will be set to a default threshold that may be
2131          * adjusted later by the driver's runtime code.  However, if the
2132          * ability to transmit pause frames in not enabled, then these
2133          * registers will be set to 0.
2134          */
2135         if (!(hw->fc & e1000_fc_tx_pause)) {
2136                 E1000_WRITE_REG(hw, FCRTL, 0);
2137                 E1000_WRITE_REG(hw, FCRTH, 0);
2138         } else {
2139                 /* We need to set up the Receive Threshold high and low water marks
2140                  * as well as (optionally) enabling the transmission of XON frames.
2141                  */
2142                 if (hw->fc_send_xon) {
2143                         E1000_WRITE_REG(hw, FCRTL,
2144                                         (hw->fc_low_water | E1000_FCRTL_XONE));
2145                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2146                 } else {
2147                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2148                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2149                 }
2150         }
2151         return ret_val;
2152 }
2153
2154 /******************************************************************************
2155  * Sets up link for a fiber based adapter
2156  *
2157  * hw - Struct containing variables accessed by shared code
2158  *
2159  * Manipulates Physical Coding Sublayer functions in order to configure
2160  * link. Assumes the hardware has been previously reset and the transmitter
2161  * and receiver are not enabled.
2162  *****************************************************************************/
2163 static int
2164 e1000_setup_fiber_link(struct e1000_hw *hw)
2165 {
2166         uint32_t ctrl;
2167         uint32_t status;
2168         uint32_t txcw = 0;
2169         uint32_t i;
2170         uint32_t signal;
2171         int32_t ret_val;
2172
2173         DEBUGFUNC();
2174         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2175          * set when the optics detect a signal. On older adapters, it will be
2176          * cleared when there is a signal
2177          */
2178         ctrl = E1000_READ_REG(hw, CTRL);
2179         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2180                 signal = E1000_CTRL_SWDPIN1;
2181         else
2182                 signal = 0;
2183
2184         printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
2185                ctrl);
2186         /* Take the link out of reset */
2187         ctrl &= ~(E1000_CTRL_LRST);
2188
2189         e1000_config_collision_dist(hw);
2190
2191         /* Check for a software override of the flow control settings, and setup
2192          * the device accordingly.  If auto-negotiation is enabled, then software
2193          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2194          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
2195          * auto-negotiation is disabled, then software will have to manually
2196          * configure the two flow control enable bits in the CTRL register.
2197          *
2198          * The possible values of the "fc" parameter are:
2199          *      0:  Flow control is completely disabled
2200          *      1:  Rx flow control is enabled (we can receive pause frames, but
2201          *          not send pause frames).
2202          *      2:  Tx flow control is enabled (we can send pause frames but we do
2203          *          not support receiving pause frames).
2204          *      3:  Both Rx and TX flow control (symmetric) are enabled.
2205          */
2206         switch (hw->fc) {
2207         case e1000_fc_none:
2208                 /* Flow control is completely disabled by a software over-ride. */
2209                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2210                 break;
2211         case e1000_fc_rx_pause:
2212                 /* RX Flow control is enabled and TX Flow control is disabled by a
2213                  * software over-ride. Since there really isn't a way to advertise
2214                  * that we are capable of RX Pause ONLY, we will advertise that we
2215                  * support both symmetric and asymmetric RX PAUSE. Later, we will
2216                  *  disable the adapter's ability to send PAUSE frames.
2217                  */
2218                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2219                 break;
2220         case e1000_fc_tx_pause:
2221                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2222                  * software over-ride.
2223                  */
2224                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2225                 break;
2226         case e1000_fc_full:
2227                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2228                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2229                 break;
2230         default:
2231                 DEBUGOUT("Flow control param set incorrectly\n");
2232                 return -E1000_ERR_CONFIG;
2233                 break;
2234         }
2235
2236         /* Since auto-negotiation is enabled, take the link out of reset (the link
2237          * will be in reset, because we previously reset the chip). This will
2238          * restart auto-negotiation.  If auto-neogtiation is successful then the
2239          * link-up status bit will be set and the flow control enable bits (RFCE
2240          * and TFCE) will be set according to their negotiated value.
2241          */
2242         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2243
2244         E1000_WRITE_REG(hw, TXCW, txcw);
2245         E1000_WRITE_REG(hw, CTRL, ctrl);
2246         E1000_WRITE_FLUSH(hw);
2247
2248         hw->txcw = txcw;
2249         mdelay(1);
2250
2251         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2252          * indication in the Device Status Register.  Time-out if a link isn't
2253          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2254          * less than 500 milliseconds even if the other end is doing it in SW).
2255          */
2256         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2257                 DEBUGOUT("Looking for Link\n");
2258                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2259                         mdelay(10);
2260                         status = E1000_READ_REG(hw, STATUS);
2261                         if (status & E1000_STATUS_LU)
2262                                 break;
2263                 }
2264                 if (i == (LINK_UP_TIMEOUT / 10)) {
2265                         /* AutoNeg failed to achieve a link, so we'll call
2266                          * e1000_check_for_link. This routine will force the link up if we
2267                          * detect a signal. This will allow us to communicate with
2268                          * non-autonegotiating link partners.
2269                          */
2270                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2271                         hw->autoneg_failed = 1;
2272                         ret_val = e1000_check_for_link(hw);
2273                         if (ret_val < 0) {
2274                                 DEBUGOUT("Error while checking for link\n");
2275                                 return ret_val;
2276                         }
2277                         hw->autoneg_failed = 0;
2278                 } else {
2279                         hw->autoneg_failed = 0;
2280                         DEBUGOUT("Valid Link Found\n");
2281                 }
2282         } else {
2283                 DEBUGOUT("No Signal Detected\n");
2284                 return -E1000_ERR_NOLINK;
2285         }
2286         return 0;
2287 }
2288
2289 /******************************************************************************
2290 * Make sure we have a valid PHY and change PHY mode before link setup.
2291 *
2292 * hw - Struct containing variables accessed by shared code
2293 ******************************************************************************/
2294 static int32_t
2295 e1000_copper_link_preconfig(struct e1000_hw *hw)
2296 {
2297         uint32_t ctrl;
2298         int32_t ret_val;
2299         uint16_t phy_data;
2300
2301         DEBUGFUNC();
2302
2303         ctrl = E1000_READ_REG(hw, CTRL);
2304         /* With 82543, we need to force speed and duplex on the MAC equal to what
2305          * the PHY speed and duplex configuration is. In addition, we need to
2306          * perform a hardware reset on the PHY to take it out of reset.
2307          */
2308         if (hw->mac_type > e1000_82543) {
2309                 ctrl |= E1000_CTRL_SLU;
2310                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2311                 E1000_WRITE_REG(hw, CTRL, ctrl);
2312         } else {
2313                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2314                                 | E1000_CTRL_SLU);
2315                 E1000_WRITE_REG(hw, CTRL, ctrl);
2316                 ret_val = e1000_phy_hw_reset(hw);
2317                 if (ret_val)
2318                         return ret_val;
2319         }
2320
2321         /* Make sure we have a valid PHY */
2322         ret_val = e1000_detect_gig_phy(hw);
2323         if (ret_val) {
2324                 DEBUGOUT("Error, did not detect valid phy.\n");
2325                 return ret_val;
2326         }
2327         DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2328
2329         /* Set PHY to class A mode (if necessary) */
2330         ret_val = e1000_set_phy_mode(hw);
2331         if (ret_val)
2332                 return ret_val;
2333         if ((hw->mac_type == e1000_82545_rev_3) ||
2334                 (hw->mac_type == e1000_82546_rev_3)) {
2335                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2336                                 &phy_data);
2337                 phy_data |= 0x00000008;
2338                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2339                                 phy_data);
2340         }
2341
2342         if (hw->mac_type <= e1000_82543 ||
2343                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2344                 hw->mac_type == e1000_82541_rev_2
2345                 || hw->mac_type == e1000_82547_rev_2)
2346                         hw->phy_reset_disable = false;
2347
2348         return E1000_SUCCESS;
2349 }
2350
2351 /*****************************************************************************
2352  *
2353  * This function sets the lplu state according to the active flag.  When
2354  * activating lplu this function also disables smart speed and vise versa.
2355  * lplu will not be activated unless the device autonegotiation advertisment
2356  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2357  * hw: Struct containing variables accessed by shared code
2358  * active - true to enable lplu false to disable lplu.
2359  *
2360  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2361  *            E1000_SUCCESS at any other case.
2362  *
2363  ****************************************************************************/
2364
2365 static int32_t
2366 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2367 {
2368         uint32_t phy_ctrl = 0;
2369         int32_t ret_val;
2370         uint16_t phy_data;
2371         DEBUGFUNC();
2372
2373         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2374             && hw->phy_type != e1000_phy_igp_3)
2375                 return E1000_SUCCESS;
2376
2377         /* During driver activity LPLU should not be used or it will attain link
2378          * from the lowest speeds starting from 10Mbps. The capability is used
2379          * for Dx transitions and states */
2380         if (hw->mac_type == e1000_82541_rev_2
2381                         || hw->mac_type == e1000_82547_rev_2) {
2382                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2383                                 &phy_data);
2384                 if (ret_val)
2385                         return ret_val;
2386         } else if (hw->mac_type == e1000_ich8lan) {
2387                 /* MAC writes into PHY register based on the state transition
2388                  * and start auto-negotiation. SW driver can overwrite the
2389                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2390                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2391         } else {
2392                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2393                                 &phy_data);
2394                 if (ret_val)
2395                         return ret_val;
2396         }
2397
2398         if (!active) {
2399                 if (hw->mac_type == e1000_82541_rev_2 ||
2400                         hw->mac_type == e1000_82547_rev_2) {
2401                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2402                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2403                                         phy_data);
2404                         if (ret_val)
2405                                 return ret_val;
2406                 } else {
2407                         if (hw->mac_type == e1000_ich8lan) {
2408                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2409                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2410                         } else {
2411                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2412                                 ret_val = e1000_write_phy_reg(hw,
2413                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2414                                 if (ret_val)
2415                                         return ret_val;
2416                         }
2417                 }
2418
2419         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2420          * Dx states where the power conservation is most important.  During
2421          * driver activity we should enable SmartSpeed, so performance is
2422          * maintained. */
2423                 if (hw->smart_speed == e1000_smart_speed_on) {
2424                         ret_val = e1000_read_phy_reg(hw,
2425                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2426                         if (ret_val)
2427                                 return ret_val;
2428
2429                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2430                         ret_val = e1000_write_phy_reg(hw,
2431                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2432                         if (ret_val)
2433                                 return ret_val;
2434                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2435                         ret_val = e1000_read_phy_reg(hw,
2436                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2437                         if (ret_val)
2438                                 return ret_val;
2439
2440                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2441                         ret_val = e1000_write_phy_reg(hw,
2442                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2443                         if (ret_val)
2444                                 return ret_val;
2445                 }
2446
2447         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2448                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2449                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2450
2451                 if (hw->mac_type == e1000_82541_rev_2 ||
2452                     hw->mac_type == e1000_82547_rev_2) {
2453                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2454                         ret_val = e1000_write_phy_reg(hw,
2455                                         IGP01E1000_GMII_FIFO, phy_data);
2456                         if (ret_val)
2457                                 return ret_val;
2458                 } else {
2459                         if (hw->mac_type == e1000_ich8lan) {
2460                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2461                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2462                         } else {
2463                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2464                                 ret_val = e1000_write_phy_reg(hw,
2465                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2466                                 if (ret_val)
2467                                         return ret_val;
2468                         }
2469                 }
2470
2471                 /* When LPLU is enabled we should disable SmartSpeed */
2472                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2473                                 &phy_data);
2474                 if (ret_val)
2475                         return ret_val;
2476
2477                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2478                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2479                                 phy_data);
2480                 if (ret_val)
2481                         return ret_val;
2482         }
2483         return E1000_SUCCESS;
2484 }
2485
2486 /*****************************************************************************
2487  *
2488  * This function sets the lplu d0 state according to the active flag.  When
2489  * activating lplu this function also disables smart speed and vise versa.
2490  * lplu will not be activated unless the device autonegotiation advertisment
2491  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2492  * hw: Struct containing variables accessed by shared code
2493  * active - true to enable lplu false to disable lplu.
2494  *
2495  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2496  *            E1000_SUCCESS at any other case.
2497  *
2498  ****************************************************************************/
2499
2500 static int32_t
2501 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2502 {
2503         uint32_t phy_ctrl = 0;
2504         int32_t ret_val;
2505         uint16_t phy_data;
2506         DEBUGFUNC();
2507
2508         if (hw->mac_type <= e1000_82547_rev_2)
2509                 return E1000_SUCCESS;
2510
2511         if (hw->mac_type == e1000_ich8lan) {
2512                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2513         } else if (hw->mac_type == e1000_igb) {
2514                 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2515         } else {
2516                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2517                                 &phy_data);
2518                 if (ret_val)
2519                         return ret_val;
2520         }
2521
2522         if (!active) {
2523                 if (hw->mac_type == e1000_ich8lan) {
2524                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2525                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2526                 } else if (hw->mac_type == e1000_igb) {
2527                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2528                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2529                 } else {
2530                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2531                         ret_val = e1000_write_phy_reg(hw,
2532                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2533                         if (ret_val)
2534                                 return ret_val;
2535                 }
2536
2537                 if (hw->mac_type == e1000_igb)
2538                         return E1000_SUCCESS;
2539
2540         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2541          * Dx states where the power conservation is most important.  During
2542          * driver activity we should enable SmartSpeed, so performance is
2543          * maintained. */
2544                 if (hw->smart_speed == e1000_smart_speed_on) {
2545                         ret_val = e1000_read_phy_reg(hw,
2546                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2547                         if (ret_val)
2548                                 return ret_val;
2549
2550                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2551                         ret_val = e1000_write_phy_reg(hw,
2552                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2553                         if (ret_val)
2554                                 return ret_val;
2555                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2556                         ret_val = e1000_read_phy_reg(hw,
2557                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2558                         if (ret_val)
2559                                 return ret_val;
2560
2561                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2562                         ret_val = e1000_write_phy_reg(hw,
2563                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2564                         if (ret_val)
2565                                 return ret_val;
2566                 }
2567
2568
2569         } else {
2570
2571                 if (hw->mac_type == e1000_ich8lan) {
2572                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2573                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2574                 } else if (hw->mac_type == e1000_igb) {
2575                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2576                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2577                 } else {
2578                         phy_data |= IGP02E1000_PM_D0_LPLU;
2579                         ret_val = e1000_write_phy_reg(hw,
2580                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2581                         if (ret_val)
2582                                 return ret_val;
2583                 }
2584
2585                 if (hw->mac_type == e1000_igb)
2586                         return E1000_SUCCESS;
2587
2588                 /* When LPLU is enabled we should disable SmartSpeed */
2589                 ret_val = e1000_read_phy_reg(hw,
2590                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2591                 if (ret_val)
2592                         return ret_val;
2593
2594                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2595                 ret_val = e1000_write_phy_reg(hw,
2596                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2597                 if (ret_val)
2598                         return ret_val;
2599
2600         }
2601         return E1000_SUCCESS;
2602 }
2603
2604 /********************************************************************
2605 * Copper link setup for e1000_phy_igp series.
2606 *
2607 * hw - Struct containing variables accessed by shared code
2608 *********************************************************************/
2609 static int32_t
2610 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2611 {
2612         uint32_t led_ctrl;
2613         int32_t ret_val;
2614         uint16_t phy_data;
2615
2616         DEBUGFUNC();
2617
2618         if (hw->phy_reset_disable)
2619                 return E1000_SUCCESS;
2620
2621         ret_val = e1000_phy_reset(hw);
2622         if (ret_val) {
2623                 DEBUGOUT("Error Resetting the PHY\n");
2624                 return ret_val;
2625         }
2626
2627         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2628         mdelay(15);
2629         if (hw->mac_type != e1000_ich8lan) {
2630                 /* Configure activity LED after PHY reset */
2631                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2632                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2633                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2634                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2635         }
2636
2637         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2638         if (hw->phy_type == e1000_phy_igp) {
2639                 /* disable lplu d3 during driver init */
2640                 ret_val = e1000_set_d3_lplu_state(hw, false);
2641                 if (ret_val) {
2642                         DEBUGOUT("Error Disabling LPLU D3\n");
2643                         return ret_val;
2644                 }
2645         }
2646
2647         /* disable lplu d0 during driver init */
2648         ret_val = e1000_set_d0_lplu_state(hw, false);
2649         if (ret_val) {
2650                 DEBUGOUT("Error Disabling LPLU D0\n");
2651                 return ret_val;
2652         }
2653         /* Configure mdi-mdix settings */
2654         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2655         if (ret_val)
2656                 return ret_val;
2657
2658         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2659                 hw->dsp_config_state = e1000_dsp_config_disabled;
2660                 /* Force MDI for earlier revs of the IGP PHY */
2661                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2662                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2663                 hw->mdix = 1;
2664
2665         } else {
2666                 hw->dsp_config_state = e1000_dsp_config_enabled;
2667                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2668
2669                 switch (hw->mdix) {
2670                 case 1:
2671                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2672                         break;
2673                 case 2:
2674                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2675                         break;
2676                 case 0:
2677                 default:
2678                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2679                         break;
2680                 }
2681         }
2682         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2683         if (ret_val)
2684                 return ret_val;
2685
2686         /* set auto-master slave resolution settings */
2687         if (hw->autoneg) {
2688                 e1000_ms_type phy_ms_setting = hw->master_slave;
2689
2690                 if (hw->ffe_config_state == e1000_ffe_config_active)
2691                         hw->ffe_config_state = e1000_ffe_config_enabled;
2692
2693                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2694                         hw->dsp_config_state = e1000_dsp_config_enabled;
2695
2696                 /* when autonegotiation advertisment is only 1000Mbps then we
2697                   * should disable SmartSpeed and enable Auto MasterSlave
2698                   * resolution as hardware default. */
2699                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2700                         /* Disable SmartSpeed */
2701                         ret_val = e1000_read_phy_reg(hw,
2702                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2703                         if (ret_val)
2704                                 return ret_val;
2705                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2706                         ret_val = e1000_write_phy_reg(hw,
2707                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2708                         if (ret_val)
2709                                 return ret_val;
2710                         /* Set auto Master/Slave resolution process */
2711                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2712                                         &phy_data);
2713                         if (ret_val)
2714                                 return ret_val;
2715                         phy_data &= ~CR_1000T_MS_ENABLE;
2716                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2717                                         phy_data);
2718                         if (ret_val)
2719                                 return ret_val;
2720                 }
2721
2722                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2723                 if (ret_val)
2724                         return ret_val;
2725
2726                 /* load defaults for future use */
2727                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2728                                 ((phy_data & CR_1000T_MS_VALUE) ?
2729                                 e1000_ms_force_master :
2730                                 e1000_ms_force_slave) :
2731                                 e1000_ms_auto;
2732
2733                 switch (phy_ms_setting) {
2734                 case e1000_ms_force_master:
2735                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2736                         break;
2737                 case e1000_ms_force_slave:
2738                         phy_data |= CR_1000T_MS_ENABLE;
2739                         phy_data &= ~(CR_1000T_MS_VALUE);
2740                         break;
2741                 case e1000_ms_auto:
2742                         phy_data &= ~CR_1000T_MS_ENABLE;
2743                 default:
2744                         break;
2745                 }
2746                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2747                 if (ret_val)
2748                         return ret_val;
2749         }
2750
2751         return E1000_SUCCESS;
2752 }
2753
2754 /*****************************************************************************
2755  * This function checks the mode of the firmware.
2756  *
2757  * returns  - true when the mode is IAMT or false.
2758  ****************************************************************************/
2759 bool
2760 e1000_check_mng_mode(struct e1000_hw *hw)
2761 {
2762         uint32_t fwsm;
2763         DEBUGFUNC();
2764
2765         fwsm = E1000_READ_REG(hw, FWSM);
2766
2767         if (hw->mac_type == e1000_ich8lan) {
2768                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2769                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2770                         return true;
2771         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2772                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2773                         return true;
2774
2775         return false;
2776 }
2777
2778 static int32_t
2779 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2780 {
2781         uint16_t swfw = E1000_SWFW_PHY0_SM;
2782         uint32_t reg_val;
2783         DEBUGFUNC();
2784
2785         if (e1000_is_second_port(hw))
2786                 swfw = E1000_SWFW_PHY1_SM;
2787
2788         if (e1000_swfw_sync_acquire(hw, swfw))
2789                 return -E1000_ERR_SWFW_SYNC;
2790
2791         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2792                         & E1000_KUMCTRLSTA_OFFSET) | data;
2793         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2794         udelay(2);
2795
2796         return E1000_SUCCESS;
2797 }
2798
2799 static int32_t
2800 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2801 {
2802         uint16_t swfw = E1000_SWFW_PHY0_SM;
2803         uint32_t reg_val;
2804         DEBUGFUNC();
2805
2806         if (e1000_is_second_port(hw))
2807                 swfw = E1000_SWFW_PHY1_SM;
2808
2809         if (e1000_swfw_sync_acquire(hw, swfw)) {
2810                 debug("%s[%i]\n", __func__, __LINE__);
2811                 return -E1000_ERR_SWFW_SYNC;
2812         }
2813
2814         /* Write register address */
2815         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2816                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2817         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2818         udelay(2);
2819
2820         /* Read the data returned */
2821         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2822         *data = (uint16_t)reg_val;
2823
2824         return E1000_SUCCESS;
2825 }
2826
2827 /********************************************************************
2828 * Copper link setup for e1000_phy_gg82563 series.
2829 *
2830 * hw - Struct containing variables accessed by shared code
2831 *********************************************************************/
2832 static int32_t
2833 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2834 {
2835         int32_t ret_val;
2836         uint16_t phy_data;
2837         uint32_t reg_data;
2838
2839         DEBUGFUNC();
2840
2841         if (!hw->phy_reset_disable) {
2842                 /* Enable CRS on TX for half-duplex operation. */
2843                 ret_val = e1000_read_phy_reg(hw,
2844                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2845                 if (ret_val)
2846                         return ret_val;
2847
2848                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2849                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2850                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2851
2852                 ret_val = e1000_write_phy_reg(hw,
2853                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2854                 if (ret_val)
2855                         return ret_val;
2856
2857                 /* Options:
2858                  *   MDI/MDI-X = 0 (default)
2859                  *   0 - Auto for all speeds
2860                  *   1 - MDI mode
2861                  *   2 - MDI-X mode
2862                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2863                  */
2864                 ret_val = e1000_read_phy_reg(hw,
2865                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2866                 if (ret_val)
2867                         return ret_val;
2868
2869                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2870
2871                 switch (hw->mdix) {
2872                 case 1:
2873                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2874                         break;
2875                 case 2:
2876                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2877                         break;
2878                 case 0:
2879                 default:
2880                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2881                         break;
2882                 }
2883
2884                 /* Options:
2885                  *   disable_polarity_correction = 0 (default)
2886                  *       Automatic Correction for Reversed Cable Polarity
2887                  *   0 - Disabled
2888                  *   1 - Enabled
2889                  */
2890                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2891                 ret_val = e1000_write_phy_reg(hw,
2892                                 GG82563_PHY_SPEC_CTRL, phy_data);
2893
2894                 if (ret_val)
2895                         return ret_val;
2896
2897                 /* SW Reset the PHY so all changes take effect */
2898                 ret_val = e1000_phy_reset(hw);
2899                 if (ret_val) {
2900                         DEBUGOUT("Error Resetting the PHY\n");
2901                         return ret_val;
2902                 }
2903         } /* phy_reset_disable */
2904
2905         if (hw->mac_type == e1000_80003es2lan) {
2906                 /* Bypass RX and TX FIFO's */
2907                 ret_val = e1000_write_kmrn_reg(hw,
2908                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2909                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2910                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2911                 if (ret_val)
2912                         return ret_val;
2913
2914                 ret_val = e1000_read_phy_reg(hw,
2915                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2916                 if (ret_val)
2917                         return ret_val;
2918
2919                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2920                 ret_val = e1000_write_phy_reg(hw,
2921                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2922
2923                 if (ret_val)
2924                         return ret_val;
2925
2926                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2927                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2928                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2929
2930                 ret_val = e1000_read_phy_reg(hw,
2931                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2932                 if (ret_val)
2933                         return ret_val;
2934
2935         /* Do not init these registers when the HW is in IAMT mode, since the
2936          * firmware will have already initialized them.  We only initialize
2937          * them if the HW is not in IAMT mode.
2938          */
2939                 if (e1000_check_mng_mode(hw) == false) {
2940                         /* Enable Electrical Idle on the PHY */
2941                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2942                         ret_val = e1000_write_phy_reg(hw,
2943                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2944                         if (ret_val)
2945                                 return ret_val;
2946
2947                         ret_val = e1000_read_phy_reg(hw,
2948                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2949                         if (ret_val)
2950                                 return ret_val;
2951
2952                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2953                         ret_val = e1000_write_phy_reg(hw,
2954                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2955
2956                         if (ret_val)
2957                                 return ret_val;
2958                 }
2959
2960                 /* Workaround: Disable padding in Kumeran interface in the MAC
2961                  * and in the PHY to avoid CRC errors.
2962                  */
2963                 ret_val = e1000_read_phy_reg(hw,
2964                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2965                 if (ret_val)
2966                         return ret_val;
2967                 phy_data |= GG82563_ICR_DIS_PADDING;
2968                 ret_val = e1000_write_phy_reg(hw,
2969                                 GG82563_PHY_INBAND_CTRL, phy_data);
2970                 if (ret_val)
2971                         return ret_val;
2972         }
2973         return E1000_SUCCESS;
2974 }
2975
2976 /********************************************************************
2977 * Copper link setup for e1000_phy_m88 series.
2978 *
2979 * hw - Struct containing variables accessed by shared code
2980 *********************************************************************/
2981 static int32_t
2982 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2983 {
2984         int32_t ret_val;
2985         uint16_t phy_data;
2986
2987         DEBUGFUNC();
2988
2989         if (hw->phy_reset_disable)
2990                 return E1000_SUCCESS;
2991
2992         /* Enable CRS on TX. This must be set for half-duplex operation. */
2993         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2994         if (ret_val)
2995                 return ret_val;
2996
2997         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2998
2999         /* Options:
3000          *   MDI/MDI-X = 0 (default)
3001          *   0 - Auto for all speeds
3002          *   1 - MDI mode
3003          *   2 - MDI-X mode
3004          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
3005          */
3006         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
3007
3008         switch (hw->mdix) {
3009         case 1:
3010                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
3011                 break;
3012         case 2:
3013                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
3014                 break;
3015         case 3:
3016                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
3017                 break;
3018         case 0:
3019         default:
3020                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
3021                 break;
3022         }
3023
3024         /* Options:
3025          *   disable_polarity_correction = 0 (default)
3026          *       Automatic Correction for Reversed Cable Polarity
3027          *   0 - Disabled
3028          *   1 - Enabled
3029          */
3030         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
3031         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
3032         if (ret_val)
3033                 return ret_val;
3034
3035         if (hw->phy_revision < M88E1011_I_REV_4) {
3036                 /* Force TX_CLK in the Extended PHY Specific Control Register
3037                  * to 25MHz clock.
3038                  */
3039                 ret_val = e1000_read_phy_reg(hw,
3040                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
3041                 if (ret_val)
3042                         return ret_val;
3043
3044                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
3045
3046                 if ((hw->phy_revision == E1000_REVISION_2) &&
3047                         (hw->phy_id == M88E1111_I_PHY_ID)) {
3048                         /* Vidalia Phy, set the downshift counter to 5x */
3049                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
3050                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
3051                         ret_val = e1000_write_phy_reg(hw,
3052                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3053                         if (ret_val)
3054                                 return ret_val;
3055                 } else {
3056                         /* Configure Master and Slave downshift values */
3057                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
3058                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
3059                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
3060                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
3061                         ret_val = e1000_write_phy_reg(hw,
3062                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3063                         if (ret_val)
3064                                 return ret_val;
3065                 }
3066         }
3067
3068         /* SW Reset the PHY so all changes take effect */
3069         ret_val = e1000_phy_reset(hw);
3070         if (ret_val) {
3071                 DEBUGOUT("Error Resetting the PHY\n");
3072                 return ret_val;
3073         }
3074
3075         return E1000_SUCCESS;
3076 }
3077
3078 /********************************************************************
3079 * Setup auto-negotiation and flow control advertisements,
3080 * and then perform auto-negotiation.
3081 *
3082 * hw - Struct containing variables accessed by shared code
3083 *********************************************************************/
3084 static int32_t
3085 e1000_copper_link_autoneg(struct e1000_hw *hw)
3086 {
3087         int32_t ret_val;
3088         uint16_t phy_data;
3089
3090         DEBUGFUNC();
3091
3092         /* Perform some bounds checking on the hw->autoneg_advertised
3093          * parameter.  If this variable is zero, then set it to the default.
3094          */
3095         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
3096
3097         /* If autoneg_advertised is zero, we assume it was not defaulted
3098          * by the calling code so we set to advertise full capability.
3099          */
3100         if (hw->autoneg_advertised == 0)
3101                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
3102
3103         /* IFE phy only supports 10/100 */
3104         if (hw->phy_type == e1000_phy_ife)
3105                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
3106
3107         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3108         ret_val = e1000_phy_setup_autoneg(hw);
3109         if (ret_val) {
3110                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
3111                 return ret_val;
3112         }
3113         DEBUGOUT("Restarting Auto-Neg\n");
3114
3115         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
3116          * the Auto Neg Restart bit in the PHY control register.
3117          */
3118         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3119         if (ret_val)
3120                 return ret_val;
3121
3122         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
3123         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3124         if (ret_val)
3125                 return ret_val;
3126
3127         /* Does the user want to wait for Auto-Neg to complete here, or
3128          * check at a later time (for example, callback routine).
3129          */
3130         /* If we do not wait for autonegtation to complete I
3131          * do not see a valid link status.
3132          * wait_autoneg_complete = 1 .
3133          */
3134         if (hw->wait_autoneg_complete) {
3135                 ret_val = e1000_wait_autoneg(hw);
3136                 if (ret_val) {
3137                         DEBUGOUT("Error while waiting for autoneg"
3138                                         "to complete\n");
3139                         return ret_val;
3140                 }
3141         }
3142
3143         hw->get_link_status = true;
3144
3145         return E1000_SUCCESS;
3146 }
3147
3148 /******************************************************************************
3149 * Config the MAC and the PHY after link is up.
3150 *   1) Set up the MAC to the current PHY speed/duplex
3151 *      if we are on 82543.  If we
3152 *      are on newer silicon, we only need to configure
3153 *      collision distance in the Transmit Control Register.
3154 *   2) Set up flow control on the MAC to that established with
3155 *      the link partner.
3156 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
3157 *
3158 * hw - Struct containing variables accessed by shared code
3159 ******************************************************************************/
3160 static int32_t
3161 e1000_copper_link_postconfig(struct e1000_hw *hw)
3162 {
3163         int32_t ret_val;
3164         DEBUGFUNC();
3165
3166         if (hw->mac_type >= e1000_82544) {
3167                 e1000_config_collision_dist(hw);
3168         } else {
3169                 ret_val = e1000_config_mac_to_phy(hw);
3170                 if (ret_val) {
3171                         DEBUGOUT("Error configuring MAC to PHY settings\n");
3172                         return ret_val;
3173                 }
3174         }
3175         ret_val = e1000_config_fc_after_link_up(hw);
3176         if (ret_val) {
3177                 DEBUGOUT("Error Configuring Flow Control\n");
3178                 return ret_val;
3179         }
3180         return E1000_SUCCESS;
3181 }
3182
3183 /******************************************************************************
3184 * Detects which PHY is present and setup the speed and duplex
3185 *
3186 * hw - Struct containing variables accessed by shared code
3187 ******************************************************************************/
3188 static int
3189 e1000_setup_copper_link(struct e1000_hw *hw)
3190 {
3191         int32_t ret_val;
3192         uint16_t i;
3193         uint16_t phy_data;
3194         uint16_t reg_data;
3195
3196         DEBUGFUNC();
3197
3198         switch (hw->mac_type) {
3199         case e1000_80003es2lan:
3200         case e1000_ich8lan:
3201                 /* Set the mac to wait the maximum time between each
3202                  * iteration and increase the max iterations when
3203                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3204                 ret_val = e1000_write_kmrn_reg(hw,
3205                                 GG82563_REG(0x34, 4), 0xFFFF);
3206                 if (ret_val)
3207                         return ret_val;
3208                 ret_val = e1000_read_kmrn_reg(hw,
3209                                 GG82563_REG(0x34, 9), &reg_data);
3210                 if (ret_val)
3211                         return ret_val;
3212                 reg_data |= 0x3F;
3213                 ret_val = e1000_write_kmrn_reg(hw,
3214                                 GG82563_REG(0x34, 9), reg_data);
3215                 if (ret_val)
3216                         return ret_val;
3217         default:
3218                 break;
3219         }
3220
3221         /* Check if it is a valid PHY and set PHY mode if necessary. */
3222         ret_val = e1000_copper_link_preconfig(hw);
3223         if (ret_val)
3224                 return ret_val;
3225         switch (hw->mac_type) {
3226         case e1000_80003es2lan:
3227                 /* Kumeran registers are written-only */
3228                 reg_data =
3229                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3230                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3231                 ret_val = e1000_write_kmrn_reg(hw,
3232                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3233                 if (ret_val)
3234                         return ret_val;
3235                 break;
3236         default:
3237                 break;
3238         }
3239
3240         if (hw->phy_type == e1000_phy_igp ||
3241                 hw->phy_type == e1000_phy_igp_3 ||
3242                 hw->phy_type == e1000_phy_igp_2) {
3243                 ret_val = e1000_copper_link_igp_setup(hw);
3244                 if (ret_val)
3245                         return ret_val;
3246         } else if (hw->phy_type == e1000_phy_m88 ||
3247                 hw->phy_type == e1000_phy_igb) {
3248                 ret_val = e1000_copper_link_mgp_setup(hw);
3249                 if (ret_val)
3250                         return ret_val;
3251         } else if (hw->phy_type == e1000_phy_gg82563) {
3252                 ret_val = e1000_copper_link_ggp_setup(hw);
3253                 if (ret_val)
3254                         return ret_val;
3255         }
3256
3257         /* always auto */
3258         /* Setup autoneg and flow control advertisement
3259           * and perform autonegotiation */
3260         ret_val = e1000_copper_link_autoneg(hw);
3261         if (ret_val)
3262                 return ret_val;
3263
3264         /* Check link status. Wait up to 100 microseconds for link to become
3265          * valid.
3266          */
3267         for (i = 0; i < 10; i++) {
3268                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3269                 if (ret_val)
3270                         return ret_val;
3271                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3272                 if (ret_val)
3273                         return ret_val;
3274
3275                 if (phy_data & MII_SR_LINK_STATUS) {
3276                         /* Config the MAC and PHY after link is up */
3277                         ret_val = e1000_copper_link_postconfig(hw);
3278                         if (ret_val)
3279                                 return ret_val;
3280
3281                         DEBUGOUT("Valid link established!!!\n");
3282                         return E1000_SUCCESS;
3283                 }
3284                 udelay(10);
3285         }
3286
3287         DEBUGOUT("Unable to establish link!!!\n");
3288         return E1000_SUCCESS;
3289 }
3290
3291 /******************************************************************************
3292 * Configures PHY autoneg and flow control advertisement settings
3293 *
3294 * hw - Struct containing variables accessed by shared code
3295 ******************************************************************************/
3296 int32_t
3297 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3298 {
3299         int32_t ret_val;
3300         uint16_t mii_autoneg_adv_reg;
3301         uint16_t mii_1000t_ctrl_reg;
3302
3303         DEBUGFUNC();
3304
3305         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3306         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3307         if (ret_val)
3308                 return ret_val;
3309
3310         if (hw->phy_type != e1000_phy_ife) {
3311                 /* Read the MII 1000Base-T Control Register (Address 9). */
3312                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3313                                 &mii_1000t_ctrl_reg);
3314                 if (ret_val)
3315                         return ret_val;
3316         } else
3317                 mii_1000t_ctrl_reg = 0;
3318
3319         /* Need to parse both autoneg_advertised and fc and set up
3320          * the appropriate PHY registers.  First we will parse for
3321          * autoneg_advertised software override.  Since we can advertise
3322          * a plethora of combinations, we need to check each bit
3323          * individually.
3324          */
3325
3326         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3327          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3328          * the  1000Base-T Control Register (Address 9).
3329          */
3330         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3331         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3332
3333         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3334
3335         /* Do we want to advertise 10 Mb Half Duplex? */
3336         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3337                 DEBUGOUT("Advertise 10mb Half duplex\n");
3338                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3339         }
3340
3341         /* Do we want to advertise 10 Mb Full Duplex? */
3342         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3343                 DEBUGOUT("Advertise 10mb Full duplex\n");
3344                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3345         }
3346
3347         /* Do we want to advertise 100 Mb Half Duplex? */
3348         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3349                 DEBUGOUT("Advertise 100mb Half duplex\n");
3350                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3351         }
3352
3353         /* Do we want to advertise 100 Mb Full Duplex? */
3354         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3355                 DEBUGOUT("Advertise 100mb Full duplex\n");
3356                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3357         }
3358
3359         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3360         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3361                 DEBUGOUT
3362                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3363         }
3364
3365         /* Do we want to advertise 1000 Mb Full Duplex? */
3366         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3367                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3368                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3369         }
3370
3371         /* Check for a software override of the flow control settings, and
3372          * setup the PHY advertisement registers accordingly.  If
3373          * auto-negotiation is enabled, then software will have to set the
3374          * "PAUSE" bits to the correct value in the Auto-Negotiation
3375          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3376          *
3377          * The possible values of the "fc" parameter are:
3378          *      0:  Flow control is completely disabled
3379          *      1:  Rx flow control is enabled (we can receive pause frames
3380          *          but not send pause frames).
3381          *      2:  Tx flow control is enabled (we can send pause frames
3382          *          but we do not support receiving pause frames).
3383          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3384          *  other:  No software override.  The flow control configuration
3385          *          in the EEPROM is used.
3386          */
3387         switch (hw->fc) {
3388         case e1000_fc_none:     /* 0 */
3389                 /* Flow control (RX & TX) is completely disabled by a
3390                  * software over-ride.
3391                  */
3392                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3393                 break;
3394         case e1000_fc_rx_pause: /* 1 */
3395                 /* RX Flow control is enabled, and TX Flow control is
3396                  * disabled, by a software over-ride.
3397                  */
3398                 /* Since there really isn't a way to advertise that we are
3399                  * capable of RX Pause ONLY, we will advertise that we
3400                  * support both symmetric and asymmetric RX PAUSE.  Later
3401                  * (in e1000_config_fc_after_link_up) we will disable the
3402                  *hw's ability to send PAUSE frames.
3403                  */
3404                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3405                 break;
3406         case e1000_fc_tx_pause: /* 2 */
3407                 /* TX Flow control is enabled, and RX Flow control is
3408                  * disabled, by a software over-ride.
3409                  */
3410                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3411                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3412                 break;
3413         case e1000_fc_full:     /* 3 */
3414                 /* Flow control (both RX and TX) is enabled by a software
3415                  * over-ride.
3416                  */
3417                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3418                 break;
3419         default:
3420                 DEBUGOUT("Flow control param set incorrectly\n");
3421                 return -E1000_ERR_CONFIG;
3422         }
3423
3424         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3425         if (ret_val)
3426                 return ret_val;
3427
3428         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3429
3430         if (hw->phy_type != e1000_phy_ife) {
3431                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3432                                 mii_1000t_ctrl_reg);
3433                 if (ret_val)
3434                         return ret_val;
3435         }
3436
3437         return E1000_SUCCESS;
3438 }
3439
3440 /******************************************************************************
3441 * Sets the collision distance in the Transmit Control register
3442 *
3443 * hw - Struct containing variables accessed by shared code
3444 *
3445 * Link should have been established previously. Reads the speed and duplex
3446 * information from the Device Status register.
3447 ******************************************************************************/
3448 static void
3449 e1000_config_collision_dist(struct e1000_hw *hw)
3450 {
3451         uint32_t tctl, coll_dist;
3452
3453         DEBUGFUNC();
3454
3455         if (hw->mac_type < e1000_82543)
3456                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3457         else
3458                 coll_dist = E1000_COLLISION_DISTANCE;
3459
3460         tctl = E1000_READ_REG(hw, TCTL);
3461
3462         tctl &= ~E1000_TCTL_COLD;
3463         tctl |= coll_dist << E1000_COLD_SHIFT;
3464
3465         E1000_WRITE_REG(hw, TCTL, tctl);
3466         E1000_WRITE_FLUSH(hw);
3467 }
3468
3469 /******************************************************************************
3470 * Sets MAC speed and duplex settings to reflect the those in the PHY
3471 *
3472 * hw - Struct containing variables accessed by shared code
3473 * mii_reg - data to write to the MII control register
3474 *
3475 * The contents of the PHY register containing the needed information need to
3476 * be passed in.
3477 ******************************************************************************/
3478 static int
3479 e1000_config_mac_to_phy(struct e1000_hw *hw)
3480 {
3481         uint32_t ctrl;
3482         uint16_t phy_data;
3483
3484         DEBUGFUNC();
3485
3486         /* Read the Device Control Register and set the bits to Force Speed
3487          * and Duplex.
3488          */
3489         ctrl = E1000_READ_REG(hw, CTRL);
3490         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3491         ctrl &= ~(E1000_CTRL_ILOS);
3492         ctrl |= (E1000_CTRL_SPD_SEL);
3493
3494         /* Set up duplex in the Device Control and Transmit Control
3495          * registers depending on negotiated values.
3496          */
3497         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3498                 DEBUGOUT("PHY Read Error\n");
3499                 return -E1000_ERR_PHY;
3500         }
3501         if (phy_data & M88E1000_PSSR_DPLX)
3502                 ctrl |= E1000_CTRL_FD;
3503         else
3504                 ctrl &= ~E1000_CTRL_FD;
3505
3506         e1000_config_collision_dist(hw);
3507
3508         /* Set up speed in the Device Control register depending on
3509          * negotiated values.
3510          */
3511         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3512                 ctrl |= E1000_CTRL_SPD_1000;
3513         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3514                 ctrl |= E1000_CTRL_SPD_100;
3515         /* Write the configured values back to the Device Control Reg. */
3516         E1000_WRITE_REG(hw, CTRL, ctrl);
3517         return 0;
3518 }
3519
3520 /******************************************************************************
3521  * Forces the MAC's flow control settings.
3522  *
3523  * hw - Struct containing variables accessed by shared code
3524  *
3525  * Sets the TFCE and RFCE bits in the device control register to reflect
3526  * the adapter settings. TFCE and RFCE need to be explicitly set by
3527  * software when a Copper PHY is used because autonegotiation is managed
3528  * by the PHY rather than the MAC. Software must also configure these
3529  * bits when link is forced on a fiber connection.
3530  *****************************************************************************/
3531 static int
3532 e1000_force_mac_fc(struct e1000_hw *hw)
3533 {
3534         uint32_t ctrl;
3535
3536         DEBUGFUNC();
3537
3538         /* Get the current configuration of the Device Control Register */
3539         ctrl = E1000_READ_REG(hw, CTRL);
3540
3541         /* Because we didn't get link via the internal auto-negotiation
3542          * mechanism (we either forced link or we got link via PHY
3543          * auto-neg), we have to manually enable/disable transmit an
3544          * receive flow control.
3545          *
3546          * The "Case" statement below enables/disable flow control
3547          * according to the "hw->fc" parameter.
3548          *
3549          * The possible values of the "fc" parameter are:
3550          *      0:  Flow control is completely disabled
3551          *      1:  Rx flow control is enabled (we can receive pause
3552          *          frames but not send pause frames).
3553          *      2:  Tx flow control is enabled (we can send pause frames
3554          *          frames but we do not receive pause frames).
3555          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3556          *  other:  No other values should be possible at this point.
3557          */
3558
3559         switch (hw->fc) {
3560         case e1000_fc_none:
3561                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3562                 break;
3563         case e1000_fc_rx_pause:
3564                 ctrl &= (~E1000_CTRL_TFCE);
3565                 ctrl |= E1000_CTRL_RFCE;
3566                 break;
3567         case e1000_fc_tx_pause:
3568                 ctrl &= (~E1000_CTRL_RFCE);
3569                 ctrl |= E1000_CTRL_TFCE;
3570                 break;
3571         case e1000_fc_full:
3572                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3573                 break;
3574         default:
3575                 DEBUGOUT("Flow control param set incorrectly\n");
3576                 return -E1000_ERR_CONFIG;
3577         }
3578
3579         /* Disable TX Flow Control for 82542 (rev 2.0) */
3580         if (hw->mac_type == e1000_82542_rev2_0)
3581                 ctrl &= (~E1000_CTRL_TFCE);
3582
3583         E1000_WRITE_REG(hw, CTRL, ctrl);
3584         return 0;
3585 }
3586
3587 /******************************************************************************
3588  * Configures flow control settings after link is established
3589  *
3590  * hw - Struct containing variables accessed by shared code
3591  *
3592  * Should be called immediately after a valid link has been established.
3593  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3594  * and autonegotiation is enabled, the MAC flow control settings will be set
3595  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3596  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3597  *****************************************************************************/
3598 static int32_t
3599 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3600 {
3601         int32_t ret_val;
3602         uint16_t mii_status_reg;
3603         uint16_t mii_nway_adv_reg;
3604         uint16_t mii_nway_lp_ability_reg;
3605         uint16_t speed;
3606         uint16_t duplex;
3607
3608         DEBUGFUNC();
3609
3610         /* Check for the case where we have fiber media and auto-neg failed
3611          * so we had to force link.  In this case, we need to force the
3612          * configuration of the MAC to match the "fc" parameter.
3613          */
3614         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3615                 || ((hw->media_type == e1000_media_type_internal_serdes)
3616                 && (hw->autoneg_failed))
3617                 || ((hw->media_type == e1000_media_type_copper)
3618                 && (!hw->autoneg))) {
3619                 ret_val = e1000_force_mac_fc(hw);
3620                 if (ret_val < 0) {
3621                         DEBUGOUT("Error forcing flow control settings\n");
3622                         return ret_val;
3623                 }
3624         }
3625
3626         /* Check for the case where we have copper media and auto-neg is
3627          * enabled.  In this case, we need to check and see if Auto-Neg
3628          * has completed, and if so, how the PHY and link partner has
3629          * flow control configured.
3630          */
3631         if (hw->media_type == e1000_media_type_copper) {
3632                 /* Read the MII Status Register and check to see if AutoNeg
3633                  * has completed.  We read this twice because this reg has
3634                  * some "sticky" (latched) bits.
3635                  */
3636                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3637                         DEBUGOUT("PHY Read Error\n");
3638                         return -E1000_ERR_PHY;
3639                 }
3640                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3641                         DEBUGOUT("PHY Read Error\n");
3642                         return -E1000_ERR_PHY;
3643                 }
3644
3645                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3646                         /* The AutoNeg process has completed, so we now need to
3647                          * read both the Auto Negotiation Advertisement Register
3648                          * (Address 4) and the Auto_Negotiation Base Page Ability
3649                          * Register (Address 5) to determine how flow control was
3650                          * negotiated.
3651                          */
3652                         if (e1000_read_phy_reg
3653                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3654                                 DEBUGOUT("PHY Read Error\n");
3655                                 return -E1000_ERR_PHY;
3656                         }
3657                         if (e1000_read_phy_reg
3658                             (hw, PHY_LP_ABILITY,
3659                              &mii_nway_lp_ability_reg) < 0) {
3660                                 DEBUGOUT("PHY Read Error\n");
3661                                 return -E1000_ERR_PHY;
3662                         }
3663
3664                         /* Two bits in the Auto Negotiation Advertisement Register
3665                          * (Address 4) and two bits in the Auto Negotiation Base
3666                          * Page Ability Register (Address 5) determine flow control
3667                          * for both the PHY and the link partner.  The following
3668                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3669                          * 1999, describes these PAUSE resolution bits and how flow
3670                          * control is determined based upon these settings.
3671                          * NOTE:  DC = Don't Care
3672                          *
3673                          *   LOCAL DEVICE  |   LINK PARTNER
3674                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3675                          *-------|---------|-------|---------|--------------------
3676                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3677                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3678                          *   0   |    1    |   1   |    0    | e1000_fc_none
3679                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3680                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3681                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3682                          *   1   |    1    |   0   |    0    | e1000_fc_none
3683                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3684                          *
3685                          */
3686                         /* Are both PAUSE bits set to 1?  If so, this implies
3687                          * Symmetric Flow Control is enabled at both ends.  The
3688                          * ASM_DIR bits are irrelevant per the spec.
3689                          *
3690                          * For Symmetric Flow Control:
3691                          *
3692                          *   LOCAL DEVICE  |   LINK PARTNER
3693                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3694                          *-------|---------|-------|---------|--------------------
3695                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3696                          *
3697                          */
3698                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3699                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3700                                 /* Now we need to check if the user selected RX ONLY
3701                                  * of pause frames.  In this case, we had to advertise
3702                                  * FULL flow control because we could not advertise RX
3703                                  * ONLY. Hence, we must now check to see if we need to
3704                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3705                                  */
3706                                 if (hw->original_fc == e1000_fc_full) {
3707                                         hw->fc = e1000_fc_full;
3708                                         DEBUGOUT("Flow Control = FULL.\r\n");
3709                                 } else {
3710                                         hw->fc = e1000_fc_rx_pause;
3711                                         DEBUGOUT
3712                                             ("Flow Control = RX PAUSE frames only.\r\n");
3713                                 }
3714                         }
3715                         /* For receiving PAUSE frames ONLY.
3716                          *
3717                          *   LOCAL DEVICE  |   LINK PARTNER
3718                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3719                          *-------|---------|-------|---------|--------------------
3720                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3721                          *
3722                          */
3723                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3724                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3725                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3726                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3727                         {
3728                                 hw->fc = e1000_fc_tx_pause;
3729                                 DEBUGOUT
3730                                     ("Flow Control = TX PAUSE frames only.\r\n");
3731                         }
3732                         /* For transmitting PAUSE frames ONLY.
3733                          *
3734                          *   LOCAL DEVICE  |   LINK PARTNER
3735                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3736                          *-------|---------|-------|---------|--------------------
3737                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3738                          *
3739                          */
3740                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3741                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3742                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3743                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3744                         {
3745                                 hw->fc = e1000_fc_rx_pause;
3746                                 DEBUGOUT
3747                                     ("Flow Control = RX PAUSE frames only.\r\n");
3748                         }
3749                         /* Per the IEEE spec, at this point flow control should be
3750                          * disabled.  However, we want to consider that we could
3751                          * be connected to a legacy switch that doesn't advertise
3752                          * desired flow control, but can be forced on the link
3753                          * partner.  So if we advertised no flow control, that is
3754                          * what we will resolve to.  If we advertised some kind of
3755                          * receive capability (Rx Pause Only or Full Flow Control)
3756                          * and the link partner advertised none, we will configure
3757                          * ourselves to enable Rx Flow Control only.  We can do
3758                          * this safely for two reasons:  If the link partner really
3759                          * didn't want flow control enabled, and we enable Rx, no
3760                          * harm done since we won't be receiving any PAUSE frames
3761                          * anyway.  If the intent on the link partner was to have
3762                          * flow control enabled, then by us enabling RX only, we
3763                          * can at least receive pause frames and process them.
3764                          * This is a good idea because in most cases, since we are
3765                          * predominantly a server NIC, more times than not we will
3766                          * be asked to delay transmission of packets than asking
3767                          * our link partner to pause transmission of frames.
3768                          */
3769                         else if (hw->original_fc == e1000_fc_none ||
3770                                  hw->original_fc == e1000_fc_tx_pause) {
3771                                 hw->fc = e1000_fc_none;
3772                                 DEBUGOUT("Flow Control = NONE.\r\n");
3773                         } else {
3774                                 hw->fc = e1000_fc_rx_pause;
3775                                 DEBUGOUT
3776                                     ("Flow Control = RX PAUSE frames only.\r\n");
3777                         }
3778
3779                         /* Now we need to do one last check...  If we auto-
3780                          * negotiated to HALF DUPLEX, flow control should not be
3781                          * enabled per IEEE 802.3 spec.
3782                          */
3783                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3784
3785                         if (duplex == HALF_DUPLEX)
3786                                 hw->fc = e1000_fc_none;
3787
3788                         /* Now we call a subroutine to actually force the MAC
3789                          * controller to use the correct flow control settings.
3790                          */
3791                         ret_val = e1000_force_mac_fc(hw);
3792                         if (ret_val < 0) {
3793                                 DEBUGOUT
3794                                     ("Error forcing flow control settings\n");
3795                                 return ret_val;
3796                         }
3797                 } else {
3798                         DEBUGOUT
3799                             ("Copper PHY and Auto Neg has not completed.\r\n");
3800                 }
3801         }
3802         return E1000_SUCCESS;
3803 }
3804
3805 /******************************************************************************
3806  * Checks to see if the link status of the hardware has changed.
3807  *
3808  * hw - Struct containing variables accessed by shared code
3809  *
3810  * Called by any function that needs to check the link status of the adapter.
3811  *****************************************************************************/
3812 static int
3813 e1000_check_for_link(struct e1000_hw *hw)
3814 {
3815         uint32_t rxcw;
3816         uint32_t ctrl;
3817         uint32_t status;
3818         uint32_t rctl;
3819         uint32_t signal;
3820         int32_t ret_val;
3821         uint16_t phy_data;
3822         uint16_t lp_capability;
3823
3824         DEBUGFUNC();
3825
3826         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3827          * set when the optics detect a signal. On older adapters, it will be
3828          * cleared when there is a signal
3829          */
3830         ctrl = E1000_READ_REG(hw, CTRL);
3831         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3832                 signal = E1000_CTRL_SWDPIN1;
3833         else
3834                 signal = 0;
3835
3836         status = E1000_READ_REG(hw, STATUS);
3837         rxcw = E1000_READ_REG(hw, RXCW);
3838         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3839
3840         /* If we have a copper PHY then we only want to go out to the PHY
3841          * registers to see if Auto-Neg has completed and/or if our link
3842          * status has changed.  The get_link_status flag will be set if we
3843          * receive a Link Status Change interrupt or we have Rx Sequence
3844          * Errors.
3845          */
3846         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3847                 /* First we want to see if the MII Status Register reports
3848                  * link.  If so, then we want to get the current speed/duplex
3849                  * of the PHY.
3850                  * Read the register twice since the link bit is sticky.
3851                  */
3852                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3853                         DEBUGOUT("PHY Read Error\n");
3854                         return -E1000_ERR_PHY;
3855                 }
3856                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3857                         DEBUGOUT("PHY Read Error\n");
3858                         return -E1000_ERR_PHY;
3859                 }
3860
3861                 if (phy_data & MII_SR_LINK_STATUS) {
3862                         hw->get_link_status = false;
3863                 } else {
3864                         /* No link detected */
3865                         return -E1000_ERR_NOLINK;
3866                 }
3867
3868                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3869                  * have Si on board that is 82544 or newer, Auto
3870                  * Speed Detection takes care of MAC speed/duplex
3871                  * configuration.  So we only need to configure Collision
3872                  * Distance in the MAC.  Otherwise, we need to force
3873                  * speed/duplex on the MAC to the current PHY speed/duplex
3874                  * settings.
3875                  */
3876                 if (hw->mac_type >= e1000_82544)
3877                         e1000_config_collision_dist(hw);
3878                 else {
3879                         ret_val = e1000_config_mac_to_phy(hw);
3880                         if (ret_val < 0) {
3881                                 DEBUGOUT
3882                                     ("Error configuring MAC to PHY settings\n");
3883                                 return ret_val;
3884                         }
3885                 }
3886
3887                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3888                  * need to restore the desired flow control settings because we may
3889                  * have had to re-autoneg with a different link partner.
3890                  */
3891                 ret_val = e1000_config_fc_after_link_up(hw);
3892                 if (ret_val < 0) {
3893                         DEBUGOUT("Error configuring flow control\n");
3894                         return ret_val;
3895                 }
3896
3897                 /* At this point we know that we are on copper and we have
3898                  * auto-negotiated link.  These are conditions for checking the link
3899                  * parter capability register.  We use the link partner capability to
3900                  * determine if TBI Compatibility needs to be turned on or off.  If
3901                  * the link partner advertises any speed in addition to Gigabit, then
3902                  * we assume that they are GMII-based, and TBI compatibility is not
3903                  * needed. If no other speeds are advertised, we assume the link
3904                  * partner is TBI-based, and we turn on TBI Compatibility.
3905                  */
3906                 if (hw->tbi_compatibility_en) {
3907                         if (e1000_read_phy_reg
3908                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3909                                 DEBUGOUT("PHY Read Error\n");
3910                                 return -E1000_ERR_PHY;
3911                         }
3912                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3913                                              NWAY_LPAR_10T_FD_CAPS |
3914                                              NWAY_LPAR_100TX_HD_CAPS |
3915                                              NWAY_LPAR_100TX_FD_CAPS |
3916                                              NWAY_LPAR_100T4_CAPS)) {
3917                                 /* If our link partner advertises anything in addition to
3918                                  * gigabit, we do not need to enable TBI compatibility.
3919                                  */
3920                                 if (hw->tbi_compatibility_on) {
3921                                         /* If we previously were in the mode, turn it off. */
3922                                         rctl = E1000_READ_REG(hw, RCTL);
3923                                         rctl &= ~E1000_RCTL_SBP;
3924                                         E1000_WRITE_REG(hw, RCTL, rctl);
3925                                         hw->tbi_compatibility_on = false;
3926                                 }
3927                         } else {
3928                                 /* If TBI compatibility is was previously off, turn it on. For
3929                                  * compatibility with a TBI link partner, we will store bad
3930                                  * packets. Some frames have an additional byte on the end and
3931                                  * will look like CRC errors to to the hardware.
3932                                  */
3933                                 if (!hw->tbi_compatibility_on) {
3934                                         hw->tbi_compatibility_on = true;
3935                                         rctl = E1000_READ_REG(hw, RCTL);
3936                                         rctl |= E1000_RCTL_SBP;
3937                                         E1000_WRITE_REG(hw, RCTL, rctl);
3938                                 }
3939                         }
3940                 }
3941         }
3942         /* If we don't have link (auto-negotiation failed or link partner cannot
3943          * auto-negotiate), the cable is plugged in (we have signal), and our
3944          * link partner is not trying to auto-negotiate with us (we are receiving
3945          * idles or data), we need to force link up. We also need to give
3946          * auto-negotiation time to complete, in case the cable was just plugged
3947          * in. The autoneg_failed flag does this.
3948          */
3949         else if ((hw->media_type == e1000_media_type_fiber) &&
3950                  (!(status & E1000_STATUS_LU)) &&
3951                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3952                  (!(rxcw & E1000_RXCW_C))) {
3953                 if (hw->autoneg_failed == 0) {
3954                         hw->autoneg_failed = 1;
3955                         return 0;
3956                 }
3957                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3958
3959                 /* Disable auto-negotiation in the TXCW register */
3960                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3961
3962                 /* Force link-up and also force full-duplex. */
3963                 ctrl = E1000_READ_REG(hw, CTRL);
3964                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3965                 E1000_WRITE_REG(hw, CTRL, ctrl);
3966
3967                 /* Configure Flow Control after forcing link up. */
3968                 ret_val = e1000_config_fc_after_link_up(hw);
3969                 if (ret_val < 0) {
3970                         DEBUGOUT("Error configuring flow control\n");
3971                         return ret_val;
3972                 }
3973         }
3974         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3975          * auto-negotiation in the TXCW register and disable forced link in the
3976          * Device Control register in an attempt to auto-negotiate with our link
3977          * partner.
3978          */
3979         else if ((hw->media_type == e1000_media_type_fiber) &&
3980                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3981                 DEBUGOUT
3982                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3983                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3984                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3985         }
3986         return 0;
3987 }
3988
3989 /******************************************************************************
3990 * Configure the MAC-to-PHY interface for 10/100Mbps
3991 *
3992 * hw - Struct containing variables accessed by shared code
3993 ******************************************************************************/
3994 static int32_t
3995 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3996 {
3997         int32_t ret_val = E1000_SUCCESS;
3998         uint32_t tipg;
3999         uint16_t reg_data;
4000
4001         DEBUGFUNC();
4002
4003         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
4004         ret_val = e1000_write_kmrn_reg(hw,
4005                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4006         if (ret_val)
4007                 return ret_val;
4008
4009         /* Configure Transmit Inter-Packet Gap */
4010         tipg = E1000_READ_REG(hw, TIPG);
4011         tipg &= ~E1000_TIPG_IPGT_MASK;
4012         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
4013         E1000_WRITE_REG(hw, TIPG, tipg);
4014
4015         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4016
4017         if (ret_val)
4018                 return ret_val;
4019
4020         if (duplex == HALF_DUPLEX)
4021                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
4022         else
4023                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4024
4025         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4026
4027         return ret_val;
4028 }
4029
4030 static int32_t
4031 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
4032 {
4033         int32_t ret_val = E1000_SUCCESS;
4034         uint16_t reg_data;
4035         uint32_t tipg;
4036
4037         DEBUGFUNC();
4038
4039         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
4040         ret_val = e1000_write_kmrn_reg(hw,
4041                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4042         if (ret_val)
4043                 return ret_val;
4044
4045         /* Configure Transmit Inter-Packet Gap */
4046         tipg = E1000_READ_REG(hw, TIPG);
4047         tipg &= ~E1000_TIPG_IPGT_MASK;
4048         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
4049         E1000_WRITE_REG(hw, TIPG, tipg);
4050
4051         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4052
4053         if (ret_val)
4054                 return ret_val;
4055
4056         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4057         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4058
4059         return ret_val;
4060 }
4061
4062 /******************************************************************************
4063  * Detects the current speed and duplex settings of the hardware.
4064  *
4065  * hw - Struct containing variables accessed by shared code
4066  * speed - Speed of the connection
4067  * duplex - Duplex setting of the connection
4068  *****************************************************************************/
4069 static int
4070 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
4071                 uint16_t *duplex)
4072 {
4073         uint32_t status;
4074         int32_t ret_val;
4075         uint16_t phy_data;
4076
4077         DEBUGFUNC();
4078
4079         if (hw->mac_type >= e1000_82543) {
4080                 status = E1000_READ_REG(hw, STATUS);
4081                 if (status & E1000_STATUS_SPEED_1000) {
4082                         *speed = SPEED_1000;
4083                         DEBUGOUT("1000 Mbs, ");
4084                 } else if (status & E1000_STATUS_SPEED_100) {
4085                         *speed = SPEED_100;
4086                         DEBUGOUT("100 Mbs, ");
4087                 } else {
4088                         *speed = SPEED_10;
4089                         DEBUGOUT("10 Mbs, ");
4090                 }
4091
4092                 if (status & E1000_STATUS_FD) {
4093                         *duplex = FULL_DUPLEX;
4094                         DEBUGOUT("Full Duplex\r\n");
4095                 } else {
4096                         *duplex = HALF_DUPLEX;
4097                         DEBUGOUT(" Half Duplex\r\n");
4098                 }
4099         } else {
4100                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
4101                 *speed = SPEED_1000;
4102                 *duplex = FULL_DUPLEX;
4103         }
4104
4105         /* IGP01 PHY may advertise full duplex operation after speed downgrade
4106          * even if it is operating at half duplex.  Here we set the duplex
4107          * settings to match the duplex in the link partner's capabilities.
4108          */
4109         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
4110                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4111                 if (ret_val)
4112                         return ret_val;
4113
4114                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4115                         *duplex = HALF_DUPLEX;
4116                 else {
4117                         ret_val = e1000_read_phy_reg(hw,
4118                                         PHY_LP_ABILITY, &phy_data);
4119                         if (ret_val)
4120                                 return ret_val;
4121                         if ((*speed == SPEED_100 &&
4122                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
4123                                 || (*speed == SPEED_10
4124                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4125                                 *duplex = HALF_DUPLEX;
4126                 }
4127         }
4128
4129         if ((hw->mac_type == e1000_80003es2lan) &&
4130                 (hw->media_type == e1000_media_type_copper)) {
4131                 if (*speed == SPEED_1000)
4132                         ret_val = e1000_configure_kmrn_for_1000(hw);
4133                 else
4134                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4135                 if (ret_val)
4136                         return ret_val;
4137         }
4138         return E1000_SUCCESS;
4139 }
4140
4141 /******************************************************************************
4142 * Blocks until autoneg completes or times out (~4.5 seconds)
4143 *
4144 * hw - Struct containing variables accessed by shared code
4145 ******************************************************************************/
4146 static int
4147 e1000_wait_autoneg(struct e1000_hw *hw)
4148 {
4149         uint16_t i;
4150         uint16_t phy_data;
4151
4152         DEBUGFUNC();
4153         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4154
4155         /* We will wait for autoneg to complete or timeout to expire. */
4156         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4157                 /* Read the MII Status Register and wait for Auto-Neg
4158                  * Complete bit to be set.
4159                  */
4160                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4161                         DEBUGOUT("PHY Read Error\n");
4162                         return -E1000_ERR_PHY;
4163                 }
4164                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4165                         DEBUGOUT("PHY Read Error\n");
4166                         return -E1000_ERR_PHY;
4167                 }
4168                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4169                         DEBUGOUT("Auto-Neg complete.\n");
4170                         return 0;
4171                 }
4172                 mdelay(100);
4173         }
4174         DEBUGOUT("Auto-Neg timedout.\n");
4175         return -E1000_ERR_TIMEOUT;
4176 }
4177
4178 /******************************************************************************
4179 * Raises the Management Data Clock
4180 *
4181 * hw - Struct containing variables accessed by shared code
4182 * ctrl - Device control register's current value
4183 ******************************************************************************/
4184 static void
4185 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4186 {
4187         /* Raise the clock input to the Management Data Clock (by setting the MDC
4188          * bit), and then delay 2 microseconds.
4189          */
4190         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4191         E1000_WRITE_FLUSH(hw);
4192         udelay(2);
4193 }
4194
4195 /******************************************************************************
4196 * Lowers the Management Data Clock
4197 *
4198 * hw - Struct containing variables accessed by shared code
4199 * ctrl - Device control register's current value
4200 ******************************************************************************/
4201 static void
4202 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4203 {
4204         /* Lower the clock input to the Management Data Clock (by clearing the MDC
4205          * bit), and then delay 2 microseconds.
4206          */
4207         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4208         E1000_WRITE_FLUSH(hw);
4209         udelay(2);
4210 }
4211
4212 /******************************************************************************
4213 * Shifts data bits out to the PHY
4214 *
4215 * hw - Struct containing variables accessed by shared code
4216 * data - Data to send out to the PHY
4217 * count - Number of bits to shift out
4218 *
4219 * Bits are shifted out in MSB to LSB order.
4220 ******************************************************************************/
4221 static void
4222 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4223 {
4224         uint32_t ctrl;
4225         uint32_t mask;
4226
4227         /* We need to shift "count" number of bits out to the PHY. So, the value
4228          * in the "data" parameter will be shifted out to the PHY one bit at a
4229          * time. In order to do this, "data" must be broken down into bits.
4230          */
4231         mask = 0x01;
4232         mask <<= (count - 1);
4233
4234         ctrl = E1000_READ_REG(hw, CTRL);
4235
4236         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4237         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4238
4239         while (mask) {
4240                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4241                  * then raising and lowering the Management Data Clock. A "0" is
4242                  * shifted out to the PHY by setting the MDIO bit to "0" and then
4243                  * raising and lowering the clock.
4244                  */
4245                 if (data & mask)
4246                         ctrl |= E1000_CTRL_MDIO;
4247                 else
4248                         ctrl &= ~E1000_CTRL_MDIO;
4249
4250                 E1000_WRITE_REG(hw, CTRL, ctrl);
4251                 E1000_WRITE_FLUSH(hw);
4252
4253                 udelay(2);
4254
4255                 e1000_raise_mdi_clk(hw, &ctrl);
4256                 e1000_lower_mdi_clk(hw, &ctrl);
4257
4258                 mask = mask >> 1;
4259         }
4260 }
4261
4262 /******************************************************************************
4263 * Shifts data bits in from the PHY
4264 *
4265 * hw - Struct containing variables accessed by shared code
4266 *
4267 * Bits are shifted in in MSB to LSB order.
4268 ******************************************************************************/
4269 static uint16_t
4270 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4271 {
4272         uint32_t ctrl;
4273         uint16_t data = 0;
4274         uint8_t i;
4275
4276         /* In order to read a register from the PHY, we need to shift in a total
4277          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4278          * to avoid contention on the MDIO pin when a read operation is performed.
4279          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4280          * by raising the input to the Management Data Clock (setting the MDC bit),
4281          * and then reading the value of the MDIO bit.
4282          */
4283         ctrl = E1000_READ_REG(hw, CTRL);
4284
4285         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4286         ctrl &= ~E1000_CTRL_MDIO_DIR;
4287         ctrl &= ~E1000_CTRL_MDIO;
4288
4289         E1000_WRITE_REG(hw, CTRL, ctrl);
4290         E1000_WRITE_FLUSH(hw);
4291
4292         /* Raise and Lower the clock before reading in the data. This accounts for
4293          * the turnaround bits. The first clock occurred when we clocked out the
4294          * last bit of the Register Address.
4295          */
4296         e1000_raise_mdi_clk(hw, &ctrl);
4297         e1000_lower_mdi_clk(hw, &ctrl);
4298
4299         for (data = 0, i = 0; i < 16; i++) {
4300                 data = data << 1;
4301                 e1000_raise_mdi_clk(hw, &ctrl);
4302                 ctrl = E1000_READ_REG(hw, CTRL);
4303                 /* Check to see if we shifted in a "1". */
4304                 if (ctrl & E1000_CTRL_MDIO)
4305                         data |= 1;
4306                 e1000_lower_mdi_clk(hw, &ctrl);
4307         }
4308
4309         e1000_raise_mdi_clk(hw, &ctrl);
4310         e1000_lower_mdi_clk(hw, &ctrl);
4311
4312         return data;
4313 }
4314
4315 /*****************************************************************************
4316 * Reads the value from a PHY register
4317 *
4318 * hw - Struct containing variables accessed by shared code
4319 * reg_addr - address of the PHY register to read
4320 ******************************************************************************/
4321 static int
4322 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4323 {
4324         uint32_t i;
4325         uint32_t mdic = 0;
4326         const uint32_t phy_addr = 1;
4327
4328         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4329                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4330                 return -E1000_ERR_PARAM;
4331         }
4332
4333         if (hw->mac_type > e1000_82543) {
4334                 /* Set up Op-code, Phy Address, and register address in the MDI
4335                  * Control register.  The MAC will take care of interfacing with the
4336                  * PHY to retrieve the desired data.
4337                  */
4338                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4339                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4340                         (E1000_MDIC_OP_READ));
4341
4342                 E1000_WRITE_REG(hw, MDIC, mdic);
4343
4344                 /* Poll the ready bit to see if the MDI read completed */
4345                 for (i = 0; i < 64; i++) {
4346                         udelay(10);
4347                         mdic = E1000_READ_REG(hw, MDIC);
4348                         if (mdic & E1000_MDIC_READY)
4349                                 break;
4350                 }
4351                 if (!(mdic & E1000_MDIC_READY)) {
4352                         DEBUGOUT("MDI Read did not complete\n");
4353                         return -E1000_ERR_PHY;
4354                 }
4355                 if (mdic & E1000_MDIC_ERROR) {
4356                         DEBUGOUT("MDI Error\n");
4357                         return -E1000_ERR_PHY;
4358                 }
4359                 *phy_data = (uint16_t) mdic;
4360         } else {
4361                 /* We must first send a preamble through the MDIO pin to signal the
4362                  * beginning of an MII instruction.  This is done by sending 32
4363                  * consecutive "1" bits.
4364                  */
4365                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4366
4367                 /* Now combine the next few fields that are required for a read
4368                  * operation.  We use this method instead of calling the
4369                  * e1000_shift_out_mdi_bits routine five different times. The format of
4370                  * a MII read instruction consists of a shift out of 14 bits and is
4371                  * defined as follows:
4372                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4373                  * followed by a shift in of 18 bits.  This first two bits shifted in
4374                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4375                  * READ operation is performed.  These two bits are thrown away
4376                  * followed by a shift in of 16 bits which contains the desired data.
4377                  */
4378                 mdic = ((reg_addr) | (phy_addr << 5) |
4379                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4380
4381                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4382
4383                 /* Now that we've shifted out the read command to the MII, we need to
4384                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4385                  * register address.
4386                  */
4387                 *phy_data = e1000_shift_in_mdi_bits(hw);
4388         }
4389         return 0;
4390 }
4391
4392 /******************************************************************************
4393 * Writes a value to a PHY register
4394 *
4395 * hw - Struct containing variables accessed by shared code
4396 * reg_addr - address of the PHY register to write
4397 * data - data to write to the PHY
4398 ******************************************************************************/
4399 static int
4400 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4401 {
4402         uint32_t i;
4403         uint32_t mdic = 0;
4404         const uint32_t phy_addr = 1;
4405
4406         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4407                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4408                 return -E1000_ERR_PARAM;
4409         }
4410
4411         if (hw->mac_type > e1000_82543) {
4412                 /* Set up Op-code, Phy Address, register address, and data intended
4413                  * for the PHY register in the MDI Control register.  The MAC will take
4414                  * care of interfacing with the PHY to send the desired data.
4415                  */
4416                 mdic = (((uint32_t) phy_data) |
4417                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4418                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4419                         (E1000_MDIC_OP_WRITE));
4420
4421                 E1000_WRITE_REG(hw, MDIC, mdic);
4422
4423                 /* Poll the ready bit to see if the MDI read completed */
4424                 for (i = 0; i < 64; i++) {
4425                         udelay(10);
4426                         mdic = E1000_READ_REG(hw, MDIC);
4427                         if (mdic & E1000_MDIC_READY)
4428                                 break;
4429                 }
4430                 if (!(mdic & E1000_MDIC_READY)) {
4431                         DEBUGOUT("MDI Write did not complete\n");
4432                         return -E1000_ERR_PHY;
4433                 }
4434         } else {
4435                 /* We'll need to use the SW defined pins to shift the write command
4436                  * out to the PHY. We first send a preamble to the PHY to signal the
4437                  * beginning of the MII instruction.  This is done by sending 32
4438                  * consecutive "1" bits.
4439                  */
4440                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4441
4442                 /* Now combine the remaining required fields that will indicate a
4443                  * write operation. We use this method instead of calling the
4444                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4445                  * format of a MII write instruction is as follows:
4446                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4447                  */
4448                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4449                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4450                 mdic <<= 16;
4451                 mdic |= (uint32_t) phy_data;
4452
4453                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4454         }
4455         return 0;
4456 }
4457
4458 /******************************************************************************
4459  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4460  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4461  * the caller to figure out how to deal with it.
4462  *
4463  * hw - Struct containing variables accessed by shared code
4464  *
4465  * returns: - E1000_BLK_PHY_RESET
4466  *            E1000_SUCCESS
4467  *
4468  *****************************************************************************/
4469 int32_t
4470 e1000_check_phy_reset_block(struct e1000_hw *hw)
4471 {
4472         uint32_t manc = 0;
4473         uint32_t fwsm = 0;
4474
4475         if (hw->mac_type == e1000_ich8lan) {
4476                 fwsm = E1000_READ_REG(hw, FWSM);
4477                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4478                                                 : E1000_BLK_PHY_RESET;
4479         }
4480
4481         if (hw->mac_type > e1000_82547_rev_2)
4482                 manc = E1000_READ_REG(hw, MANC);
4483         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4484                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4485 }
4486
4487 /***************************************************************************
4488  * Checks if the PHY configuration is done
4489  *
4490  * hw: Struct containing variables accessed by shared code
4491  *
4492  * returns: - E1000_ERR_RESET if fail to reset MAC
4493  *            E1000_SUCCESS at any other case.
4494  *
4495  ***************************************************************************/
4496 static int32_t
4497 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4498 {
4499         int32_t timeout = PHY_CFG_TIMEOUT;
4500         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4501
4502         DEBUGFUNC();
4503
4504         switch (hw->mac_type) {
4505         default:
4506                 mdelay(10);
4507                 break;
4508
4509         case e1000_80003es2lan:
4510                 /* Separate *_CFG_DONE_* bit for each port */
4511                 if (e1000_is_second_port(hw))
4512                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4513                 /* Fall Through */
4514
4515         case e1000_82571:
4516         case e1000_82572:
4517         case e1000_igb:
4518                 while (timeout) {
4519                         if (hw->mac_type == e1000_igb) {
4520                                 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4521                                         break;
4522                         } else {
4523                                 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4524                                         break;
4525                         }
4526                         mdelay(1);
4527                         timeout--;
4528                 }
4529                 if (!timeout) {
4530                         DEBUGOUT("MNG configuration cycle has not "
4531                                         "completed.\n");
4532                         return -E1000_ERR_RESET;
4533                 }
4534                 break;
4535         }
4536
4537         return E1000_SUCCESS;
4538 }
4539
4540 /******************************************************************************
4541 * Returns the PHY to the power-on reset state
4542 *
4543 * hw - Struct containing variables accessed by shared code
4544 ******************************************************************************/
4545 int32_t
4546 e1000_phy_hw_reset(struct e1000_hw *hw)
4547 {
4548         uint16_t swfw = E1000_SWFW_PHY0_SM;
4549         uint32_t ctrl, ctrl_ext;
4550         uint32_t led_ctrl;
4551         int32_t ret_val;
4552
4553         DEBUGFUNC();
4554
4555         /* In the case of the phy reset being blocked, it's not an error, we
4556          * simply return success without performing the reset. */
4557         ret_val = e1000_check_phy_reset_block(hw);
4558         if (ret_val)
4559                 return E1000_SUCCESS;
4560
4561         DEBUGOUT("Resetting Phy...\n");
4562
4563         if (hw->mac_type > e1000_82543) {
4564                 if (e1000_is_second_port(hw))
4565                         swfw = E1000_SWFW_PHY1_SM;
4566
4567                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4568                         DEBUGOUT("Unable to acquire swfw sync\n");
4569                         return -E1000_ERR_SWFW_SYNC;
4570                 }
4571
4572                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4573                  * bit. Then, take it out of reset.
4574                  */
4575                 ctrl = E1000_READ_REG(hw, CTRL);
4576                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4577                 E1000_WRITE_FLUSH(hw);
4578
4579                 if (hw->mac_type < e1000_82571)
4580                         udelay(10);
4581                 else
4582                         udelay(100);
4583
4584                 E1000_WRITE_REG(hw, CTRL, ctrl);
4585                 E1000_WRITE_FLUSH(hw);
4586
4587                 if (hw->mac_type >= e1000_82571)
4588                         mdelay(10);
4589
4590         } else {
4591                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4592                  * bit to put the PHY into reset. Then, take it out of reset.
4593                  */
4594                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4595                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4596                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4597                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4598                 E1000_WRITE_FLUSH(hw);
4599                 mdelay(10);
4600                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4601                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4602                 E1000_WRITE_FLUSH(hw);
4603         }
4604         udelay(150);
4605
4606         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4607                 /* Configure activity LED after PHY reset */
4608                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4609                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4610                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4611                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4612         }
4613
4614         e1000_swfw_sync_release(hw, swfw);
4615
4616         /* Wait for FW to finish PHY configuration. */
4617         ret_val = e1000_get_phy_cfg_done(hw);
4618         if (ret_val != E1000_SUCCESS)
4619                 return ret_val;
4620
4621         return ret_val;
4622 }
4623
4624 /******************************************************************************
4625  * IGP phy init script - initializes the GbE PHY
4626  *
4627  * hw - Struct containing variables accessed by shared code
4628  *****************************************************************************/
4629 static void
4630 e1000_phy_init_script(struct e1000_hw *hw)
4631 {
4632         uint32_t ret_val;
4633         uint16_t phy_saved_data;
4634         DEBUGFUNC();
4635
4636         if (hw->phy_init_script) {
4637                 mdelay(20);
4638
4639                 /* Save off the current value of register 0x2F5B to be
4640                  * restored at the end of this routine. */
4641                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4642
4643                 /* Disabled the PHY transmitter */
4644                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4645
4646                 mdelay(20);
4647
4648                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4649
4650                 mdelay(5);
4651
4652                 switch (hw->mac_type) {
4653                 case e1000_82541:
4654                 case e1000_82547:
4655                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4656
4657                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4658
4659                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4660
4661                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4662
4663                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4664
4665                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4666
4667                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4668
4669                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4670
4671                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4672                         break;
4673
4674                 case e1000_82541_rev_2:
4675                 case e1000_82547_rev_2:
4676                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4677                         break;
4678                 default:
4679                         break;
4680                 }
4681
4682                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4683
4684                 mdelay(20);
4685
4686                 /* Now enable the transmitter */
4687                 if (!ret_val)
4688                         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4689
4690                 if (hw->mac_type == e1000_82547) {
4691                         uint16_t fused, fine, coarse;
4692
4693                         /* Move to analog registers page */
4694                         e1000_read_phy_reg(hw,
4695                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4696
4697                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4698                                 e1000_read_phy_reg(hw,
4699                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4700
4701                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4702                                 coarse = fused
4703                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4704
4705                                 if (coarse >
4706                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4707                                         coarse -=
4708                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4709                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4710                                 } else if (coarse
4711                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4712                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4713
4714                                 fused = (fused
4715                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4716                                         (fine
4717                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4718                                         (coarse
4719                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4720
4721                                 e1000_write_phy_reg(hw,
4722                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4723                                 e1000_write_phy_reg(hw,
4724                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4725                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4726                         }
4727                 }
4728         }
4729 }
4730
4731 /******************************************************************************
4732 * Resets the PHY
4733 *
4734 * hw - Struct containing variables accessed by shared code
4735 *
4736 * Sets bit 15 of the MII Control register
4737 ******************************************************************************/
4738 int32_t
4739 e1000_phy_reset(struct e1000_hw *hw)
4740 {
4741         int32_t ret_val;
4742         uint16_t phy_data;
4743
4744         DEBUGFUNC();
4745
4746         /* In the case of the phy reset being blocked, it's not an error, we
4747          * simply return success without performing the reset. */
4748         ret_val = e1000_check_phy_reset_block(hw);
4749         if (ret_val)
4750                 return E1000_SUCCESS;
4751
4752         switch (hw->phy_type) {
4753         case e1000_phy_igp:
4754         case e1000_phy_igp_2:
4755         case e1000_phy_igp_3:
4756         case e1000_phy_ife:
4757         case e1000_phy_igb:
4758                 ret_val = e1000_phy_hw_reset(hw);
4759                 if (ret_val)
4760                         return ret_val;
4761                 break;
4762         default:
4763                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4764                 if (ret_val)
4765                         return ret_val;
4766
4767                 phy_data |= MII_CR_RESET;
4768                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4769                 if (ret_val)
4770                         return ret_val;
4771
4772                 udelay(1);
4773                 break;
4774         }
4775
4776         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4777                 e1000_phy_init_script(hw);
4778
4779         return E1000_SUCCESS;
4780 }
4781
4782 static int e1000_set_phy_type (struct e1000_hw *hw)
4783 {
4784         DEBUGFUNC ();
4785
4786         if (hw->mac_type == e1000_undefined)
4787                 return -E1000_ERR_PHY_TYPE;
4788
4789         switch (hw->phy_id) {
4790         case M88E1000_E_PHY_ID:
4791         case M88E1000_I_PHY_ID:
4792         case M88E1011_I_PHY_ID:
4793         case M88E1111_I_PHY_ID:
4794                 hw->phy_type = e1000_phy_m88;
4795                 break;
4796         case IGP01E1000_I_PHY_ID:
4797                 if (hw->mac_type == e1000_82541 ||
4798                         hw->mac_type == e1000_82541_rev_2 ||
4799                         hw->mac_type == e1000_82547 ||
4800                         hw->mac_type == e1000_82547_rev_2) {
4801                         hw->phy_type = e1000_phy_igp;
4802                         break;
4803                 }
4804         case IGP03E1000_E_PHY_ID:
4805                 hw->phy_type = e1000_phy_igp_3;
4806                 break;
4807         case IFE_E_PHY_ID:
4808         case IFE_PLUS_E_PHY_ID:
4809         case IFE_C_E_PHY_ID:
4810                 hw->phy_type = e1000_phy_ife;
4811                 break;
4812         case GG82563_E_PHY_ID:
4813                 if (hw->mac_type == e1000_80003es2lan) {
4814                         hw->phy_type = e1000_phy_gg82563;
4815                         break;
4816                 }
4817         case BME1000_E_PHY_ID:
4818                 hw->phy_type = e1000_phy_bm;
4819                 break;
4820         case I210_I_PHY_ID:
4821                 hw->phy_type = e1000_phy_igb;
4822                 break;
4823                 /* Fall Through */
4824         default:
4825                 /* Should never have loaded on this device */
4826                 hw->phy_type = e1000_phy_undefined;
4827                 return -E1000_ERR_PHY_TYPE;
4828         }
4829
4830         return E1000_SUCCESS;
4831 }
4832
4833 /******************************************************************************
4834 * Probes the expected PHY address for known PHY IDs
4835 *
4836 * hw - Struct containing variables accessed by shared code
4837 ******************************************************************************/
4838 static int32_t
4839 e1000_detect_gig_phy(struct e1000_hw *hw)
4840 {
4841         int32_t phy_init_status, ret_val;
4842         uint16_t phy_id_high, phy_id_low;
4843         bool match = false;
4844
4845         DEBUGFUNC();
4846
4847         /* The 82571 firmware may still be configuring the PHY.  In this
4848          * case, we cannot access the PHY until the configuration is done.  So
4849          * we explicitly set the PHY values. */
4850         if (hw->mac_type == e1000_82571 ||
4851                 hw->mac_type == e1000_82572) {
4852                 hw->phy_id = IGP01E1000_I_PHY_ID;
4853                 hw->phy_type = e1000_phy_igp_2;
4854                 return E1000_SUCCESS;
4855         }
4856
4857         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4858          * work- around that forces PHY page 0 to be set or the reads fail.
4859          * The rest of the code in this routine uses e1000_read_phy_reg to
4860          * read the PHY ID.  So for ESB-2 we need to have this set so our
4861          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4862          * the routines below will figure this out as well. */
4863         if (hw->mac_type == e1000_80003es2lan)
4864                 hw->phy_type = e1000_phy_gg82563;
4865
4866         /* Read the PHY ID Registers to identify which PHY is onboard. */
4867         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4868         if (ret_val)
4869                 return ret_val;
4870
4871         hw->phy_id = (uint32_t) (phy_id_high << 16);
4872         udelay(20);
4873         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4874         if (ret_val)
4875                 return ret_val;
4876
4877         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4878         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4879
4880         switch (hw->mac_type) {
4881         case e1000_82543:
4882                 if (hw->phy_id == M88E1000_E_PHY_ID)
4883                         match = true;
4884                 break;
4885         case e1000_82544:
4886                 if (hw->phy_id == M88E1000_I_PHY_ID)
4887                         match = true;
4888                 break;
4889         case e1000_82540:
4890         case e1000_82545:
4891         case e1000_82545_rev_3:
4892         case e1000_82546:
4893         case e1000_82546_rev_3:
4894                 if (hw->phy_id == M88E1011_I_PHY_ID)
4895                         match = true;
4896                 break;
4897         case e1000_82541:
4898         case e1000_82541_rev_2:
4899         case e1000_82547:
4900         case e1000_82547_rev_2:
4901                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4902                         match = true;
4903
4904                 break;
4905         case e1000_82573:
4906                 if (hw->phy_id == M88E1111_I_PHY_ID)
4907                         match = true;
4908                 break;
4909         case e1000_82574:
4910                 if (hw->phy_id == BME1000_E_PHY_ID)
4911                         match = true;
4912                 break;
4913         case e1000_80003es2lan:
4914                 if (hw->phy_id == GG82563_E_PHY_ID)
4915                         match = true;
4916                 break;
4917         case e1000_ich8lan:
4918                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4919                         match = true;
4920                 if (hw->phy_id == IFE_E_PHY_ID)
4921                         match = true;
4922                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4923                         match = true;
4924                 if (hw->phy_id == IFE_C_E_PHY_ID)
4925                         match = true;
4926                 break;
4927         case e1000_igb:
4928                 if (hw->phy_id == I210_I_PHY_ID)
4929                         match = true;
4930                 break;
4931         default:
4932                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4933                 return -E1000_ERR_CONFIG;
4934         }
4935
4936         phy_init_status = e1000_set_phy_type(hw);
4937
4938         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4939                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4940                 return 0;
4941         }
4942         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4943         return -E1000_ERR_PHY;
4944 }
4945
4946 /*****************************************************************************
4947  * Set media type and TBI compatibility.
4948  *
4949  * hw - Struct containing variables accessed by shared code
4950  * **************************************************************************/
4951 void
4952 e1000_set_media_type(struct e1000_hw *hw)
4953 {
4954         uint32_t status;
4955
4956         DEBUGFUNC();
4957
4958         if (hw->mac_type != e1000_82543) {
4959                 /* tbi_compatibility is only valid on 82543 */
4960                 hw->tbi_compatibility_en = false;
4961         }
4962
4963         switch (hw->device_id) {
4964         case E1000_DEV_ID_82545GM_SERDES:
4965         case E1000_DEV_ID_82546GB_SERDES:
4966         case E1000_DEV_ID_82571EB_SERDES:
4967         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4968         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4969         case E1000_DEV_ID_82572EI_SERDES:
4970         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4971                 hw->media_type = e1000_media_type_internal_serdes;
4972                 break;
4973         default:
4974                 switch (hw->mac_type) {
4975                 case e1000_82542_rev2_0:
4976                 case e1000_82542_rev2_1:
4977                         hw->media_type = e1000_media_type_fiber;
4978                         break;
4979                 case e1000_ich8lan:
4980                 case e1000_82573:
4981                 case e1000_82574:
4982                 case e1000_igb:
4983                         /* The STATUS_TBIMODE bit is reserved or reused
4984                          * for the this device.
4985                          */
4986                         hw->media_type = e1000_media_type_copper;
4987                         break;
4988                 default:
4989                         status = E1000_READ_REG(hw, STATUS);
4990                         if (status & E1000_STATUS_TBIMODE) {
4991                                 hw->media_type = e1000_media_type_fiber;
4992                                 /* tbi_compatibility not valid on fiber */
4993                                 hw->tbi_compatibility_en = false;
4994                         } else {
4995                                 hw->media_type = e1000_media_type_copper;
4996                         }
4997                         break;
4998                 }
4999         }
5000 }
5001
5002 /**
5003  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
5004  *
5005  * e1000_sw_init initializes the Adapter private data structure.
5006  * Fields are initialized based on PCI device information and
5007  * OS network device settings (MTU size).
5008  **/
5009
5010 static int
5011 e1000_sw_init(struct e1000_hw *hw)
5012 {
5013         int result;
5014
5015         /* PCI config space info */
5016 #ifdef CONFIG_DM_ETH
5017         dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5018         dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5019         dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5020                              &hw->subsystem_vendor_id);
5021         dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5022
5023         dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5024         dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5025 #else
5026         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5027         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5028         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5029                              &hw->subsystem_vendor_id);
5030         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5031
5032         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5033         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5034 #endif
5035
5036         /* identify the MAC */
5037         result = e1000_set_mac_type(hw);
5038         if (result) {
5039                 E1000_ERR(hw, "Unknown MAC Type\n");
5040                 return result;
5041         }
5042
5043         switch (hw->mac_type) {
5044         default:
5045                 break;
5046         case e1000_82541:
5047         case e1000_82547:
5048         case e1000_82541_rev_2:
5049         case e1000_82547_rev_2:
5050                 hw->phy_init_script = 1;
5051                 break;
5052         }
5053
5054         /* flow control settings */
5055         hw->fc_high_water = E1000_FC_HIGH_THRESH;
5056         hw->fc_low_water = E1000_FC_LOW_THRESH;
5057         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
5058         hw->fc_send_xon = 1;
5059
5060         /* Media type - copper or fiber */
5061         hw->tbi_compatibility_en = true;
5062         e1000_set_media_type(hw);
5063
5064         if (hw->mac_type >= e1000_82543) {
5065                 uint32_t status = E1000_READ_REG(hw, STATUS);
5066
5067                 if (status & E1000_STATUS_TBIMODE) {
5068                         DEBUGOUT("fiber interface\n");
5069                         hw->media_type = e1000_media_type_fiber;
5070                 } else {
5071                         DEBUGOUT("copper interface\n");
5072                         hw->media_type = e1000_media_type_copper;
5073                 }
5074         } else {
5075                 hw->media_type = e1000_media_type_fiber;
5076         }
5077
5078         hw->wait_autoneg_complete = true;
5079         if (hw->mac_type < e1000_82543)
5080                 hw->report_tx_early = 0;
5081         else
5082                 hw->report_tx_early = 1;
5083
5084         return E1000_SUCCESS;
5085 }
5086
5087 void
5088 fill_rx(struct e1000_hw *hw)
5089 {
5090         struct e1000_rx_desc *rd;
5091         unsigned long flush_start, flush_end;
5092
5093         rx_last = rx_tail;
5094         rd = rx_base + rx_tail;
5095         rx_tail = (rx_tail + 1) % 8;
5096         memset(rd, 0, 16);
5097         rd->buffer_addr = cpu_to_le64((unsigned long)packet);
5098
5099         /*
5100          * Make sure there are no stale data in WB over this area, which
5101          * might get written into the memory while the e1000 also writes
5102          * into the same memory area.
5103          */
5104         invalidate_dcache_range((unsigned long)packet,
5105                                 (unsigned long)packet + 4096);
5106         /* Dump the DMA descriptor into RAM. */
5107         flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5108         flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5109         flush_dcache_range(flush_start, flush_end);
5110
5111         E1000_WRITE_REG(hw, RDT, rx_tail);
5112 }
5113
5114 /**
5115  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
5116  * @adapter: board private structure
5117  *
5118  * Configure the Tx unit of the MAC after a reset.
5119  **/
5120
5121 static void
5122 e1000_configure_tx(struct e1000_hw *hw)
5123 {
5124         unsigned long tctl;
5125         unsigned long tipg, tarc;
5126         uint32_t ipgr1, ipgr2;
5127
5128         E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
5129         E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
5130
5131         E1000_WRITE_REG(hw, TDLEN, 128);
5132
5133         /* Setup the HW Tx Head and Tail descriptor pointers */
5134         E1000_WRITE_REG(hw, TDH, 0);
5135         E1000_WRITE_REG(hw, TDT, 0);
5136         tx_tail = 0;
5137
5138         /* Set the default values for the Tx Inter Packet Gap timer */
5139         if (hw->mac_type <= e1000_82547_rev_2 &&
5140             (hw->media_type == e1000_media_type_fiber ||
5141              hw->media_type == e1000_media_type_internal_serdes))
5142                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5143         else
5144                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5145
5146         /* Set the default values for the Tx Inter Packet Gap timer */
5147         switch (hw->mac_type) {
5148         case e1000_82542_rev2_0:
5149         case e1000_82542_rev2_1:
5150                 tipg = DEFAULT_82542_TIPG_IPGT;
5151                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5152                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5153                 break;
5154         case e1000_80003es2lan:
5155                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5156                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5157                 break;
5158         default:
5159                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5160                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5161                 break;
5162         }
5163         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5164         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5165         E1000_WRITE_REG(hw, TIPG, tipg);
5166         /* Program the Transmit Control Register */
5167         tctl = E1000_READ_REG(hw, TCTL);
5168         tctl &= ~E1000_TCTL_CT;
5169         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5170             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5171
5172         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5173                 tarc = E1000_READ_REG(hw, TARC0);
5174                 /* set the speed mode bit, we'll clear it if we're not at
5175                  * gigabit link later */
5176                 /* git bit can be set to 1*/
5177         } else if (hw->mac_type == e1000_80003es2lan) {
5178                 tarc = E1000_READ_REG(hw, TARC0);
5179                 tarc |= 1;
5180                 E1000_WRITE_REG(hw, TARC0, tarc);
5181                 tarc = E1000_READ_REG(hw, TARC1);
5182                 tarc |= 1;
5183                 E1000_WRITE_REG(hw, TARC1, tarc);
5184         }
5185
5186
5187         e1000_config_collision_dist(hw);
5188         /* Setup Transmit Descriptor Settings for eop descriptor */
5189         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5190
5191         /* Need to set up RS bit */
5192         if (hw->mac_type < e1000_82543)
5193                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5194         else
5195                 hw->txd_cmd |= E1000_TXD_CMD_RS;
5196
5197
5198         if (hw->mac_type == e1000_igb) {
5199                 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5200
5201                 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5202                 reg_txdctl |= 1 << 25;
5203                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5204                 mdelay(20);
5205         }
5206
5207
5208
5209         E1000_WRITE_REG(hw, TCTL, tctl);
5210
5211
5212 }
5213
5214 /**
5215  * e1000_setup_rctl - configure the receive control register
5216  * @adapter: Board private structure
5217  **/
5218 static void
5219 e1000_setup_rctl(struct e1000_hw *hw)
5220 {
5221         uint32_t rctl;
5222
5223         rctl = E1000_READ_REG(hw, RCTL);
5224
5225         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5226
5227         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5228                 | E1000_RCTL_RDMTS_HALF;        /* |
5229                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5230
5231         if (hw->tbi_compatibility_on == 1)
5232                 rctl |= E1000_RCTL_SBP;
5233         else
5234                 rctl &= ~E1000_RCTL_SBP;
5235
5236         rctl &= ~(E1000_RCTL_SZ_4096);
5237                 rctl |= E1000_RCTL_SZ_2048;
5238                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5239         E1000_WRITE_REG(hw, RCTL, rctl);
5240 }
5241
5242 /**
5243  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5244  * @adapter: board private structure
5245  *
5246  * Configure the Rx unit of the MAC after a reset.
5247  **/
5248 static void
5249 e1000_configure_rx(struct e1000_hw *hw)
5250 {
5251         unsigned long rctl, ctrl_ext;
5252         rx_tail = 0;
5253
5254         /* make sure receives are disabled while setting up the descriptors */
5255         rctl = E1000_READ_REG(hw, RCTL);
5256         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5257         if (hw->mac_type >= e1000_82540) {
5258                 /* Set the interrupt throttling rate.  Value is calculated
5259                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5260 #define MAX_INTS_PER_SEC        8000
5261 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
5262                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5263         }
5264
5265         if (hw->mac_type >= e1000_82571) {
5266                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5267                 /* Reset delay timers after every interrupt */
5268                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5269                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5270                 E1000_WRITE_FLUSH(hw);
5271         }
5272         /* Setup the Base and Length of the Rx Descriptor Ring */
5273         E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
5274         E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
5275
5276         E1000_WRITE_REG(hw, RDLEN, 128);
5277
5278         /* Setup the HW Rx Head and Tail Descriptor Pointers */
5279         E1000_WRITE_REG(hw, RDH, 0);
5280         E1000_WRITE_REG(hw, RDT, 0);
5281         /* Enable Receives */
5282
5283         if (hw->mac_type == e1000_igb) {
5284
5285                 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5286                 reg_rxdctl |= 1 << 25;
5287                 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5288                 mdelay(20);
5289         }
5290
5291         E1000_WRITE_REG(hw, RCTL, rctl);
5292
5293         fill_rx(hw);
5294 }
5295
5296 /**************************************************************************
5297 POLL - Wait for a frame
5298 ***************************************************************************/
5299 static int
5300 _e1000_poll(struct e1000_hw *hw)
5301 {
5302         struct e1000_rx_desc *rd;
5303         unsigned long inval_start, inval_end;
5304         uint32_t len;
5305
5306         /* return true if there's an ethernet packet ready to read */
5307         rd = rx_base + rx_last;
5308
5309         /* Re-load the descriptor from RAM. */
5310         inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5311         inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5312         invalidate_dcache_range(inval_start, inval_end);
5313
5314         if (!(rd->status & E1000_RXD_STAT_DD))
5315                 return 0;
5316         /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5317         /* Packet received, make sure the data are re-loaded from RAM. */
5318         len = le16_to_cpu(rd->length);
5319         invalidate_dcache_range((unsigned long)packet,
5320                                 (unsigned long)packet +
5321                                 roundup(len, ARCH_DMA_MINALIGN));
5322         return len;
5323 }
5324
5325 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
5326 {
5327         void *nv_packet = (void *)txpacket;
5328         struct e1000_tx_desc *txp;
5329         int i = 0;
5330         unsigned long flush_start, flush_end;
5331
5332         txp = tx_base + tx_tail;
5333         tx_tail = (tx_tail + 1) % 8;
5334
5335         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5336         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5337         txp->upper.data = 0;
5338
5339         /* Dump the packet into RAM so e1000 can pick them. */
5340         flush_dcache_range((unsigned long)nv_packet,
5341                            (unsigned long)nv_packet +
5342                            roundup(length, ARCH_DMA_MINALIGN));
5343         /* Dump the descriptor into RAM as well. */
5344         flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5345         flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5346         flush_dcache_range(flush_start, flush_end);
5347
5348         E1000_WRITE_REG(hw, TDT, tx_tail);
5349
5350         E1000_WRITE_FLUSH(hw);
5351         while (1) {
5352                 invalidate_dcache_range(flush_start, flush_end);
5353                 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5354                         break;
5355                 if (i++ > TOUT_LOOP) {
5356                         DEBUGOUT("e1000: tx timeout\n");
5357                         return 0;
5358                 }
5359                 udelay(10);     /* give the nic a chance to write to the register */
5360         }
5361         return 1;
5362 }
5363
5364 static void
5365 _e1000_disable(struct e1000_hw *hw)
5366 {
5367         /* Turn off the ethernet interface */
5368         E1000_WRITE_REG(hw, RCTL, 0);
5369         E1000_WRITE_REG(hw, TCTL, 0);
5370
5371         /* Clear the transmit ring */
5372         E1000_WRITE_REG(hw, TDH, 0);
5373         E1000_WRITE_REG(hw, TDT, 0);
5374
5375         /* Clear the receive ring */
5376         E1000_WRITE_REG(hw, RDH, 0);
5377         E1000_WRITE_REG(hw, RDT, 0);
5378
5379         mdelay(10);
5380 }
5381
5382 /*reset function*/
5383 static inline int
5384 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5385 {
5386         e1000_reset_hw(hw);
5387         if (hw->mac_type >= e1000_82544)
5388                 E1000_WRITE_REG(hw, WUC, 0);
5389
5390         return e1000_init_hw(hw, enetaddr);
5391 }
5392
5393 static int
5394 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
5395 {
5396         int ret_val = 0;
5397
5398         ret_val = e1000_reset(hw, enetaddr);
5399         if (ret_val < 0) {
5400                 if ((ret_val == -E1000_ERR_NOLINK) ||
5401                     (ret_val == -E1000_ERR_TIMEOUT)) {
5402                         E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5403                 } else {
5404                         E1000_ERR(hw, "Hardware Initialization Failed\n");
5405                 }
5406                 return ret_val;
5407         }
5408         e1000_configure_tx(hw);
5409         e1000_setup_rctl(hw);
5410         e1000_configure_rx(hw);
5411         return 0;
5412 }
5413
5414 /******************************************************************************
5415  * Gets the current PCI bus type of hardware
5416  *
5417  * hw - Struct containing variables accessed by shared code
5418  *****************************************************************************/
5419 void e1000_get_bus_type(struct e1000_hw *hw)
5420 {
5421         uint32_t status;
5422
5423         switch (hw->mac_type) {
5424         case e1000_82542_rev2_0:
5425         case e1000_82542_rev2_1:
5426                 hw->bus_type = e1000_bus_type_pci;
5427                 break;
5428         case e1000_82571:
5429         case e1000_82572:
5430         case e1000_82573:
5431         case e1000_82574:
5432         case e1000_80003es2lan:
5433         case e1000_ich8lan:
5434         case e1000_igb:
5435                 hw->bus_type = e1000_bus_type_pci_express;
5436                 break;
5437         default:
5438                 status = E1000_READ_REG(hw, STATUS);
5439                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5440                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5441                 break;
5442         }
5443 }
5444
5445 #ifndef CONFIG_DM_ETH
5446 /* A list of all registered e1000 devices */
5447 static LIST_HEAD(e1000_hw_list);
5448 #endif
5449
5450 #ifdef CONFIG_DM_ETH
5451 static int e1000_init_one(struct e1000_hw *hw, int cardnum,
5452                           struct udevice *devno, unsigned char enetaddr[6])
5453 #else
5454 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5455                           unsigned char enetaddr[6])
5456 #endif
5457 {
5458         u32 val;
5459
5460         /* Assign the passed-in values */
5461 #ifdef CONFIG_DM_ETH
5462         hw->pdev = devno;
5463 #else
5464         hw->pdev = devno;
5465 #endif
5466         hw->cardnum = cardnum;
5467
5468         /* Print a debug message with the IO base address */
5469 #ifdef CONFIG_DM_ETH
5470         dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
5471 #else
5472         pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5473 #endif
5474         E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5475
5476         /* Try to enable I/O accesses and bus-mastering */
5477         val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5478 #ifdef CONFIG_DM_ETH
5479         dm_pci_write_config32(devno, PCI_COMMAND, val);
5480 #else
5481         pci_write_config_dword(devno, PCI_COMMAND, val);
5482 #endif
5483
5484         /* Make sure it worked */
5485 #ifdef CONFIG_DM_ETH
5486         dm_pci_read_config32(devno, PCI_COMMAND, &val);
5487 #else
5488         pci_read_config_dword(devno, PCI_COMMAND, &val);
5489 #endif
5490         if (!(val & PCI_COMMAND_MEMORY)) {
5491                 E1000_ERR(hw, "Can't enable I/O memory\n");
5492                 return -ENOSPC;
5493         }
5494         if (!(val & PCI_COMMAND_MASTER)) {
5495                 E1000_ERR(hw, "Can't enable bus-mastering\n");
5496                 return -EPERM;
5497         }
5498
5499         /* Are these variables needed? */
5500         hw->fc = e1000_fc_default;
5501         hw->original_fc = e1000_fc_default;
5502         hw->autoneg_failed = 0;
5503         hw->autoneg = 1;
5504         hw->get_link_status = true;
5505 #ifndef CONFIG_E1000_NO_NVM
5506         hw->eeprom_semaphore_present = true;
5507 #endif
5508 #ifdef CONFIG_DM_ETH
5509         hw->hw_addr = dm_pci_map_bar(devno,     PCI_BASE_ADDRESS_0,
5510                                                 PCI_REGION_MEM);
5511 #else
5512         hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5513                                                 PCI_REGION_MEM);
5514 #endif
5515         hw->mac_type = e1000_undefined;
5516
5517         /* MAC and Phy settings */
5518         if (e1000_sw_init(hw) < 0) {
5519                 E1000_ERR(hw, "Software init failed\n");
5520                 return -EIO;
5521         }
5522         if (e1000_check_phy_reset_block(hw))
5523                 E1000_ERR(hw, "PHY Reset is blocked!\n");
5524
5525         /* Basic init was OK, reset the hardware and allow SPI access */
5526         e1000_reset_hw(hw);
5527
5528 #ifndef CONFIG_E1000_NO_NVM
5529         /* Validate the EEPROM and get chipset information */
5530         if (e1000_init_eeprom_params(hw)) {
5531                 E1000_ERR(hw, "EEPROM is invalid!\n");
5532                 return -EINVAL;
5533         }
5534         if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5535             e1000_validate_eeprom_checksum(hw))
5536                 return -ENXIO;
5537         e1000_read_mac_addr(hw, enetaddr);
5538 #endif
5539         e1000_get_bus_type(hw);
5540
5541 #ifndef CONFIG_E1000_NO_NVM
5542         printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5543                enetaddr[0], enetaddr[1], enetaddr[2],
5544                enetaddr[3], enetaddr[4], enetaddr[5]);
5545 #else
5546         memset(enetaddr, 0, 6);
5547         printf("e1000: no NVM\n");
5548 #endif
5549
5550         return 0;
5551 }
5552
5553 /* Put the name of a device in a string */
5554 static void e1000_name(char *str, int cardnum)
5555 {
5556         sprintf(str, "e1000#%u", cardnum);
5557 }
5558
5559 #ifndef CONFIG_DM_ETH
5560 /**************************************************************************
5561 TRANSMIT - Transmit a frame
5562 ***************************************************************************/
5563 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5564 {
5565         struct e1000_hw *hw = nic->priv;
5566
5567         return _e1000_transmit(hw, txpacket, length);
5568 }
5569
5570 /**************************************************************************
5571 DISABLE - Turn off ethernet interface
5572 ***************************************************************************/
5573 static void
5574 e1000_disable(struct eth_device *nic)
5575 {
5576         struct e1000_hw *hw = nic->priv;
5577
5578         _e1000_disable(hw);
5579 }
5580
5581 /**************************************************************************
5582 INIT - set up ethernet interface(s)
5583 ***************************************************************************/
5584 static int
5585 e1000_init(struct eth_device *nic, bd_t *bis)
5586 {
5587         struct e1000_hw *hw = nic->priv;
5588
5589         return _e1000_init(hw, nic->enetaddr);
5590 }
5591
5592 static int
5593 e1000_poll(struct eth_device *nic)
5594 {
5595         struct e1000_hw *hw = nic->priv;
5596         int len;
5597
5598         len = _e1000_poll(hw);
5599         if (len) {
5600                 net_process_received_packet((uchar *)packet, len);
5601                 fill_rx(hw);
5602         }
5603
5604         return len ? 1 : 0;
5605 }
5606
5607 /**************************************************************************
5608 PROBE - Look for an adapter, this routine's visible to the outside
5609 You should omit the last argument struct pci_device * for a non-PCI NIC
5610 ***************************************************************************/
5611 int
5612 e1000_initialize(bd_t * bis)
5613 {
5614         unsigned int i;
5615         pci_dev_t devno;
5616         int ret;
5617
5618         DEBUGFUNC();
5619
5620         /* Find and probe all the matching PCI devices */
5621         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5622                 /*
5623                  * These will never get freed due to errors, this allows us to
5624                  * perform SPI EEPROM programming from U-Boot, for example.
5625                  */
5626                 struct eth_device *nic = malloc(sizeof(*nic));
5627                 struct e1000_hw *hw = malloc(sizeof(*hw));
5628                 if (!nic || !hw) {
5629                         printf("e1000#%u: Out of Memory!\n", i);
5630                         free(nic);
5631                         free(hw);
5632                         continue;
5633                 }
5634
5635                 /* Make sure all of the fields are initially zeroed */
5636                 memset(nic, 0, sizeof(*nic));
5637                 memset(hw, 0, sizeof(*hw));
5638                 nic->priv = hw;
5639
5640                 /* Generate a card name */
5641                 e1000_name(nic->name, i);
5642                 hw->name = nic->name;
5643
5644                 ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5645                 if (ret)
5646                         continue;
5647                 list_add_tail(&hw->list_node, &e1000_hw_list);
5648
5649                 hw->nic = nic;
5650
5651                 /* Set up the function pointers and register the device */
5652                 nic->init = e1000_init;
5653                 nic->recv = e1000_poll;
5654                 nic->send = e1000_transmit;
5655                 nic->halt = e1000_disable;
5656                 eth_register(nic);
5657         }
5658
5659         return i;
5660 }
5661
5662 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5663 {
5664         struct e1000_hw *hw;
5665
5666         list_for_each_entry(hw, &e1000_hw_list, list_node)
5667                 if (hw->cardnum == cardnum)
5668                         return hw;
5669
5670         return NULL;
5671 }
5672 #endif /* !CONFIG_DM_ETH */
5673
5674 #ifdef CONFIG_CMD_E1000
5675 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5676                 int argc, char * const argv[])
5677 {
5678         unsigned char *mac = NULL;
5679 #ifdef CONFIG_DM_ETH
5680         struct eth_pdata *plat;
5681         struct udevice *dev;
5682         char name[30];
5683         int ret;
5684 #endif
5685 #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
5686         struct e1000_hw *hw;
5687 #endif
5688         int cardnum;
5689
5690         if (argc < 3) {
5691                 cmd_usage(cmdtp);
5692                 return 1;
5693         }
5694
5695         /* Make sure we can find the requested e1000 card */
5696         cardnum = simple_strtoul(argv[1], NULL, 10);
5697 #ifdef CONFIG_DM_ETH
5698         e1000_name(name, cardnum);
5699         ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5700         if (!ret) {
5701                 plat = dev_get_platdata(dev);
5702                 mac = plat->enetaddr;
5703         }
5704 #else
5705         hw = e1000_find_card(cardnum);
5706         if (hw)
5707                 mac = hw->nic->enetaddr;
5708 #endif
5709         if (!mac) {
5710                 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5711                 return 1;
5712         }
5713
5714         if (!strcmp(argv[2], "print-mac-address")) {
5715                 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5716                         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5717                 return 0;
5718         }
5719
5720 #ifdef CONFIG_E1000_SPI
5721 #ifdef CONFIG_DM_ETH
5722         hw = dev_get_priv(dev);
5723 #endif
5724         /* Handle the "SPI" subcommand */
5725         if (!strcmp(argv[2], "spi"))
5726                 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5727 #endif
5728
5729         cmd_usage(cmdtp);
5730         return 1;
5731 }
5732
5733 U_BOOT_CMD(
5734         e1000, 7, 0, do_e1000,
5735         "Intel e1000 controller management",
5736         /*  */"<card#> print-mac-address\n"
5737 #ifdef CONFIG_E1000_SPI
5738         "e1000 <card#> spi show [<offset> [<length>]]\n"
5739         "e1000 <card#> spi dump <addr> <offset> <length>\n"
5740         "e1000 <card#> spi program <addr> <offset> <length>\n"
5741         "e1000 <card#> spi checksum [update]\n"
5742 #endif
5743         "       - Manage the Intel E1000 PCI device"
5744 );
5745 #endif /* not CONFIG_CMD_E1000 */
5746
5747 #ifdef CONFIG_DM_ETH
5748 static int e1000_eth_start(struct udevice *dev)
5749 {
5750         struct eth_pdata *plat = dev_get_platdata(dev);
5751         struct e1000_hw *hw = dev_get_priv(dev);
5752
5753         return _e1000_init(hw, plat->enetaddr);
5754 }
5755
5756 static void e1000_eth_stop(struct udevice *dev)
5757 {
5758         struct e1000_hw *hw = dev_get_priv(dev);
5759
5760         _e1000_disable(hw);
5761 }
5762
5763 static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5764 {
5765         struct e1000_hw *hw = dev_get_priv(dev);
5766         int ret;
5767
5768         ret = _e1000_transmit(hw, packet, length);
5769
5770         return ret ? 0 : -ETIMEDOUT;
5771 }
5772
5773 static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5774 {
5775         struct e1000_hw *hw = dev_get_priv(dev);
5776         int len;
5777
5778         len = _e1000_poll(hw);
5779         if (len)
5780                 *packetp = packet;
5781
5782         return len ? len : -EAGAIN;
5783 }
5784
5785 static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5786 {
5787         struct e1000_hw *hw = dev_get_priv(dev);
5788
5789         fill_rx(hw);
5790
5791         return 0;
5792 }
5793
5794 static int e1000_eth_probe(struct udevice *dev)
5795 {
5796         struct eth_pdata *plat = dev_get_platdata(dev);
5797         struct e1000_hw *hw = dev_get_priv(dev);
5798         int ret;
5799
5800         hw->name = dev->name;
5801         ret = e1000_init_one(hw, trailing_strtol(dev->name),
5802                              dev, plat->enetaddr);
5803         if (ret < 0) {
5804                 printf(pr_fmt("failed to initialize card: %d\n"), ret);
5805                 return ret;
5806         }
5807
5808         return 0;
5809 }
5810
5811 static int e1000_eth_bind(struct udevice *dev)
5812 {
5813         char name[20];
5814
5815         /*
5816          * A simple way to number the devices. When device tree is used this
5817          * is unnecessary, but when the device is just discovered on the PCI
5818          * bus we need a name. We could instead have the uclass figure out
5819          * which devices are different and number them.
5820          */
5821         e1000_name(name, num_cards++);
5822
5823         return device_set_name(dev, name);
5824 }
5825
5826 static const struct eth_ops e1000_eth_ops = {
5827         .start  = e1000_eth_start,
5828         .send   = e1000_eth_send,
5829         .recv   = e1000_eth_recv,
5830         .stop   = e1000_eth_stop,
5831         .free_pkt = e1000_free_pkt,
5832 };
5833
5834 static const struct udevice_id e1000_eth_ids[] = {
5835         { .compatible = "intel,e1000" },
5836         { }
5837 };
5838
5839 U_BOOT_DRIVER(eth_e1000) = {
5840         .name   = "eth_e1000",
5841         .id     = UCLASS_ETH,
5842         .of_match = e1000_eth_ids,
5843         .bind   = e1000_eth_bind,
5844         .probe  = e1000_eth_probe,
5845         .ops    = &e1000_eth_ops,
5846         .priv_auto_alloc_size = sizeof(struct e1000_hw),
5847         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5848 };
5849
5850 U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
5851 #endif