1 /**************************************************************************
2 Intel Pro 1000 for ppcboot/das-u-boot
3 Drivers are port from Intel's Linux driver e1000-4.3.15
4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
5 tested on both gig copper and gig fiber boards
6 ***************************************************************************/
7 /*******************************************************************************
10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
12 * SPDX-License-Identifier: GPL-2.0+
15 Linux NICS <linux.nics@intel.com>
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
18 *******************************************************************************/
20 * Copyright (C) Archway Digital Solutions.
22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
25 * Copyright (C) Linux Networx.
26 * Massive upgrade to work with the new intel gigabit NICs.
27 * <ebiederman at lnxi dot com>
29 * Copyright 2011 Freescale Semiconductor, Inc.
39 #define TOUT_LOOP 100000
41 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
42 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
44 #define E1000_DEFAULT_PCI_PBA 0x00000030
45 #define E1000_DEFAULT_PCIE_PBA 0x000a0026
47 /* NIC specific static variables go here */
49 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
50 #define E1000_BUFFER_ALIGN 128
53 * TODO(sjg@chromium.org): Even with driver model we share these buffers.
54 * Concurrent receiving on multiple active Ethernet devices will not work.
55 * Normally U-Boot does not support this anyway. To fix it in this driver,
56 * move these buffers and the tx/rx pointers to struct e1000_hw.
58 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
59 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
60 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
63 static int rx_tail, rx_last;
65 static int num_cards; /* Number of E1000 devices seen so far */
68 static struct pci_device_id e1000_supported[] = {
69 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
70 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
71 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
72 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
73 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
74 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
75 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
76 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
77 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
78 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
79 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
80 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
85 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
88 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
98 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
106 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
107 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
108 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
109 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
110 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
111 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
112 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
113 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
114 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
115 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
116 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
121 /* Function forward declarations */
122 static int e1000_setup_link(struct e1000_hw *hw);
123 static int e1000_setup_fiber_link(struct e1000_hw *hw);
124 static int e1000_setup_copper_link(struct e1000_hw *hw);
125 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
126 static void e1000_config_collision_dist(struct e1000_hw *hw);
127 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
128 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
129 static int e1000_check_for_link(struct e1000_hw *hw);
130 static int e1000_wait_autoneg(struct e1000_hw *hw);
131 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
133 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
134 uint16_t * phy_data);
135 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
137 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
138 static int e1000_phy_reset(struct e1000_hw *hw);
139 static int e1000_detect_gig_phy(struct e1000_hw *hw);
140 static void e1000_set_media_type(struct e1000_hw *hw);
142 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
143 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
144 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
146 #ifndef CONFIG_E1000_NO_NVM
147 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
148 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
151 /******************************************************************************
152 * Raises the EEPROM's clock input.
154 * hw - Struct containing variables accessed by shared code
155 * eecd - EECD's current value
156 *****************************************************************************/
157 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
159 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
160 * wait 50 microseconds.
162 *eecd = *eecd | E1000_EECD_SK;
163 E1000_WRITE_REG(hw, EECD, *eecd);
164 E1000_WRITE_FLUSH(hw);
168 /******************************************************************************
169 * Lowers the EEPROM's clock input.
171 * hw - Struct containing variables accessed by shared code
172 * eecd - EECD's current value
173 *****************************************************************************/
174 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
176 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
177 * wait 50 microseconds.
179 *eecd = *eecd & ~E1000_EECD_SK;
180 E1000_WRITE_REG(hw, EECD, *eecd);
181 E1000_WRITE_FLUSH(hw);
185 /******************************************************************************
186 * Shift data bits out to the EEPROM.
188 * hw - Struct containing variables accessed by shared code
189 * data - data to send to the EEPROM
190 * count - number of bits to shift out
191 *****************************************************************************/
193 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
198 /* We need to shift "count" bits out to the EEPROM. So, value in the
199 * "data" parameter will be shifted out to the EEPROM one bit at a time.
200 * In order to do this, "data" must be broken down into bits.
202 mask = 0x01 << (count - 1);
203 eecd = E1000_READ_REG(hw, EECD);
204 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
206 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
207 * and then raising and then lowering the clock (the SK bit controls
208 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
209 * by setting "DI" to "0" and then raising and then lowering the clock.
211 eecd &= ~E1000_EECD_DI;
214 eecd |= E1000_EECD_DI;
216 E1000_WRITE_REG(hw, EECD, eecd);
217 E1000_WRITE_FLUSH(hw);
221 e1000_raise_ee_clk(hw, &eecd);
222 e1000_lower_ee_clk(hw, &eecd);
228 /* We leave the "DI" bit set to "0" when we leave this routine. */
229 eecd &= ~E1000_EECD_DI;
230 E1000_WRITE_REG(hw, EECD, eecd);
233 /******************************************************************************
234 * Shift data bits in from the EEPROM
236 * hw - Struct containing variables accessed by shared code
237 *****************************************************************************/
239 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
245 /* In order to read a register from the EEPROM, we need to shift 'count'
246 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
247 * input to the EEPROM (setting the SK bit), and then reading the
248 * value of the "DO" bit. During this "shifting in" process the
249 * "DI" bit should always be clear.
252 eecd = E1000_READ_REG(hw, EECD);
254 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
257 for (i = 0; i < count; i++) {
259 e1000_raise_ee_clk(hw, &eecd);
261 eecd = E1000_READ_REG(hw, EECD);
263 eecd &= ~(E1000_EECD_DI);
264 if (eecd & E1000_EECD_DO)
267 e1000_lower_ee_clk(hw, &eecd);
273 /******************************************************************************
274 * Returns EEPROM to a "standby" state
276 * hw - Struct containing variables accessed by shared code
277 *****************************************************************************/
278 void e1000_standby_eeprom(struct e1000_hw *hw)
280 struct e1000_eeprom_info *eeprom = &hw->eeprom;
283 eecd = E1000_READ_REG(hw, EECD);
285 if (eeprom->type == e1000_eeprom_microwire) {
286 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
287 E1000_WRITE_REG(hw, EECD, eecd);
288 E1000_WRITE_FLUSH(hw);
289 udelay(eeprom->delay_usec);
292 eecd |= E1000_EECD_SK;
293 E1000_WRITE_REG(hw, EECD, eecd);
294 E1000_WRITE_FLUSH(hw);
295 udelay(eeprom->delay_usec);
298 eecd |= E1000_EECD_CS;
299 E1000_WRITE_REG(hw, EECD, eecd);
300 E1000_WRITE_FLUSH(hw);
301 udelay(eeprom->delay_usec);
304 eecd &= ~E1000_EECD_SK;
305 E1000_WRITE_REG(hw, EECD, eecd);
306 E1000_WRITE_FLUSH(hw);
307 udelay(eeprom->delay_usec);
308 } else if (eeprom->type == e1000_eeprom_spi) {
309 /* Toggle CS to flush commands */
310 eecd |= E1000_EECD_CS;
311 E1000_WRITE_REG(hw, EECD, eecd);
312 E1000_WRITE_FLUSH(hw);
313 udelay(eeprom->delay_usec);
314 eecd &= ~E1000_EECD_CS;
315 E1000_WRITE_REG(hw, EECD, eecd);
316 E1000_WRITE_FLUSH(hw);
317 udelay(eeprom->delay_usec);
321 /***************************************************************************
322 * Description: Determines if the onboard NVM is FLASH or EEPROM.
324 * hw - Struct containing variables accessed by shared code
325 ****************************************************************************/
326 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
332 if (hw->mac_type == e1000_ich8lan)
335 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
336 eecd = E1000_READ_REG(hw, EECD);
338 /* Isolate bits 15 & 16 */
339 eecd = ((eecd >> 15) & 0x03);
341 /* If both bits are set, device is Flash type */
348 /******************************************************************************
349 * Prepares EEPROM for access
351 * hw - Struct containing variables accessed by shared code
353 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
354 * function should be called before issuing a command to the EEPROM.
355 *****************************************************************************/
356 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
358 struct e1000_eeprom_info *eeprom = &hw->eeprom;
359 uint32_t eecd, i = 0;
363 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
364 return -E1000_ERR_SWFW_SYNC;
365 eecd = E1000_READ_REG(hw, EECD);
367 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
368 /* Request EEPROM Access */
369 if (hw->mac_type > e1000_82544) {
370 eecd |= E1000_EECD_REQ;
371 E1000_WRITE_REG(hw, EECD, eecd);
372 eecd = E1000_READ_REG(hw, EECD);
373 while ((!(eecd & E1000_EECD_GNT)) &&
374 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
377 eecd = E1000_READ_REG(hw, EECD);
379 if (!(eecd & E1000_EECD_GNT)) {
380 eecd &= ~E1000_EECD_REQ;
381 E1000_WRITE_REG(hw, EECD, eecd);
382 DEBUGOUT("Could not acquire EEPROM grant\n");
383 return -E1000_ERR_EEPROM;
388 /* Setup EEPROM for Read/Write */
390 if (eeprom->type == e1000_eeprom_microwire) {
391 /* Clear SK and DI */
392 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
393 E1000_WRITE_REG(hw, EECD, eecd);
396 eecd |= E1000_EECD_CS;
397 E1000_WRITE_REG(hw, EECD, eecd);
398 } else if (eeprom->type == e1000_eeprom_spi) {
399 /* Clear SK and CS */
400 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
401 E1000_WRITE_REG(hw, EECD, eecd);
405 return E1000_SUCCESS;
408 /******************************************************************************
409 * Sets up eeprom variables in the hw struct. Must be called after mac_type
410 * is configured. Additionally, if this is ICH8, the flash controller GbE
411 * registers must be mapped, or this will crash.
413 * hw - Struct containing variables accessed by shared code
414 *****************************************************************************/
415 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
417 struct e1000_eeprom_info *eeprom = &hw->eeprom;
419 int32_t ret_val = E1000_SUCCESS;
420 uint16_t eeprom_size;
422 if (hw->mac_type == e1000_igb)
423 eecd = E1000_READ_REG(hw, I210_EECD);
425 eecd = E1000_READ_REG(hw, EECD);
429 switch (hw->mac_type) {
430 case e1000_82542_rev2_0:
431 case e1000_82542_rev2_1:
434 eeprom->type = e1000_eeprom_microwire;
435 eeprom->word_size = 64;
436 eeprom->opcode_bits = 3;
437 eeprom->address_bits = 6;
438 eeprom->delay_usec = 50;
439 eeprom->use_eerd = false;
440 eeprom->use_eewr = false;
444 case e1000_82545_rev_3:
446 case e1000_82546_rev_3:
447 eeprom->type = e1000_eeprom_microwire;
448 eeprom->opcode_bits = 3;
449 eeprom->delay_usec = 50;
450 if (eecd & E1000_EECD_SIZE) {
451 eeprom->word_size = 256;
452 eeprom->address_bits = 8;
454 eeprom->word_size = 64;
455 eeprom->address_bits = 6;
457 eeprom->use_eerd = false;
458 eeprom->use_eewr = false;
461 case e1000_82541_rev_2:
463 case e1000_82547_rev_2:
464 if (eecd & E1000_EECD_TYPE) {
465 eeprom->type = e1000_eeprom_spi;
466 eeprom->opcode_bits = 8;
467 eeprom->delay_usec = 1;
468 if (eecd & E1000_EECD_ADDR_BITS) {
469 eeprom->page_size = 32;
470 eeprom->address_bits = 16;
472 eeprom->page_size = 8;
473 eeprom->address_bits = 8;
476 eeprom->type = e1000_eeprom_microwire;
477 eeprom->opcode_bits = 3;
478 eeprom->delay_usec = 50;
479 if (eecd & E1000_EECD_ADDR_BITS) {
480 eeprom->word_size = 256;
481 eeprom->address_bits = 8;
483 eeprom->word_size = 64;
484 eeprom->address_bits = 6;
487 eeprom->use_eerd = false;
488 eeprom->use_eewr = false;
492 eeprom->type = e1000_eeprom_spi;
493 eeprom->opcode_bits = 8;
494 eeprom->delay_usec = 1;
495 if (eecd & E1000_EECD_ADDR_BITS) {
496 eeprom->page_size = 32;
497 eeprom->address_bits = 16;
499 eeprom->page_size = 8;
500 eeprom->address_bits = 8;
502 eeprom->use_eerd = false;
503 eeprom->use_eewr = false;
507 eeprom->type = e1000_eeprom_spi;
508 eeprom->opcode_bits = 8;
509 eeprom->delay_usec = 1;
510 if (eecd & E1000_EECD_ADDR_BITS) {
511 eeprom->page_size = 32;
512 eeprom->address_bits = 16;
514 eeprom->page_size = 8;
515 eeprom->address_bits = 8;
517 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
518 eeprom->use_eerd = true;
519 eeprom->use_eewr = true;
521 eeprom->type = e1000_eeprom_flash;
522 eeprom->word_size = 2048;
524 /* Ensure that the Autonomous FLASH update bit is cleared due to
525 * Flash update issue on parts which use a FLASH for NVM. */
526 eecd &= ~E1000_EECD_AUPDEN;
527 E1000_WRITE_REG(hw, EECD, eecd);
530 case e1000_80003es2lan:
531 eeprom->type = e1000_eeprom_spi;
532 eeprom->opcode_bits = 8;
533 eeprom->delay_usec = 1;
534 if (eecd & E1000_EECD_ADDR_BITS) {
535 eeprom->page_size = 32;
536 eeprom->address_bits = 16;
538 eeprom->page_size = 8;
539 eeprom->address_bits = 8;
541 eeprom->use_eerd = true;
542 eeprom->use_eewr = false;
545 /* i210 has 4k of iNVM mapped as EEPROM */
546 eeprom->type = e1000_eeprom_invm;
547 eeprom->opcode_bits = 8;
548 eeprom->delay_usec = 1;
549 eeprom->page_size = 32;
550 eeprom->address_bits = 16;
551 eeprom->use_eerd = true;
552 eeprom->use_eewr = false;
558 if (eeprom->type == e1000_eeprom_spi ||
559 eeprom->type == e1000_eeprom_invm) {
560 /* eeprom_size will be an enum [0..8] that maps
561 * to eeprom sizes 128B to
562 * 32KB (incremented by powers of 2).
564 if (hw->mac_type <= e1000_82547_rev_2) {
565 /* Set to default value for initial eeprom read. */
566 eeprom->word_size = 64;
567 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
571 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
572 >> EEPROM_SIZE_SHIFT;
573 /* 256B eeprom size was not supported in earlier
574 * hardware, so we bump eeprom_size up one to
575 * ensure that "1" (which maps to 256B) is never
576 * the result used in the shifting logic below. */
580 eeprom_size = (uint16_t)((eecd &
581 E1000_EECD_SIZE_EX_MASK) >>
582 E1000_EECD_SIZE_EX_SHIFT);
585 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
590 /******************************************************************************
591 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
593 * hw - Struct containing variables accessed by shared code
594 *****************************************************************************/
596 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
598 uint32_t attempts = 100000;
600 int32_t done = E1000_ERR_EEPROM;
602 for (i = 0; i < attempts; i++) {
603 if (eerd == E1000_EEPROM_POLL_READ) {
604 if (hw->mac_type == e1000_igb)
605 reg = E1000_READ_REG(hw, I210_EERD);
607 reg = E1000_READ_REG(hw, EERD);
609 if (hw->mac_type == e1000_igb)
610 reg = E1000_READ_REG(hw, I210_EEWR);
612 reg = E1000_READ_REG(hw, EEWR);
615 if (reg & E1000_EEPROM_RW_REG_DONE) {
616 done = E1000_SUCCESS;
625 /******************************************************************************
626 * Reads a 16 bit word from the EEPROM using the EERD register.
628 * hw - Struct containing variables accessed by shared code
629 * offset - offset of word in the EEPROM to read
630 * data - word read from the EEPROM
631 * words - number of words to read
632 *****************************************************************************/
634 e1000_read_eeprom_eerd(struct e1000_hw *hw,
639 uint32_t i, eerd = 0;
642 for (i = 0; i < words; i++) {
643 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
644 E1000_EEPROM_RW_REG_START;
646 if (hw->mac_type == e1000_igb)
647 E1000_WRITE_REG(hw, I210_EERD, eerd);
649 E1000_WRITE_REG(hw, EERD, eerd);
651 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
656 if (hw->mac_type == e1000_igb) {
657 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
658 E1000_EEPROM_RW_REG_DATA);
660 data[i] = (E1000_READ_REG(hw, EERD) >>
661 E1000_EEPROM_RW_REG_DATA);
669 void e1000_release_eeprom(struct e1000_hw *hw)
675 eecd = E1000_READ_REG(hw, EECD);
677 if (hw->eeprom.type == e1000_eeprom_spi) {
678 eecd |= E1000_EECD_CS; /* Pull CS high */
679 eecd &= ~E1000_EECD_SK; /* Lower SCK */
681 E1000_WRITE_REG(hw, EECD, eecd);
683 udelay(hw->eeprom.delay_usec);
684 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
687 /* CS on Microwire is active-high */
688 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
690 E1000_WRITE_REG(hw, EECD, eecd);
692 /* Rising edge of clock */
693 eecd |= E1000_EECD_SK;
694 E1000_WRITE_REG(hw, EECD, eecd);
695 E1000_WRITE_FLUSH(hw);
696 udelay(hw->eeprom.delay_usec);
698 /* Falling edge of clock */
699 eecd &= ~E1000_EECD_SK;
700 E1000_WRITE_REG(hw, EECD, eecd);
701 E1000_WRITE_FLUSH(hw);
702 udelay(hw->eeprom.delay_usec);
705 /* Stop requesting EEPROM access */
706 if (hw->mac_type > e1000_82544) {
707 eecd &= ~E1000_EECD_REQ;
708 E1000_WRITE_REG(hw, EECD, eecd);
711 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
714 /******************************************************************************
715 * Reads a 16 bit word from the EEPROM.
717 * hw - Struct containing variables accessed by shared code
718 *****************************************************************************/
720 e1000_spi_eeprom_ready(struct e1000_hw *hw)
722 uint16_t retry_count = 0;
723 uint8_t spi_stat_reg;
727 /* Read "Status Register" repeatedly until the LSB is cleared. The
728 * EEPROM will signal that the command has been completed by clearing
729 * bit 0 of the internal status register. If it's not cleared within
730 * 5 milliseconds, then error out.
734 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
735 hw->eeprom.opcode_bits);
736 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
737 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
743 e1000_standby_eeprom(hw);
744 } while (retry_count < EEPROM_MAX_RETRY_SPI);
746 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
747 * only 0-5mSec on 5V devices)
749 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
750 DEBUGOUT("SPI EEPROM Status error\n");
751 return -E1000_ERR_EEPROM;
754 return E1000_SUCCESS;
757 /******************************************************************************
758 * Reads a 16 bit word from the EEPROM.
760 * hw - Struct containing variables accessed by shared code
761 * offset - offset of word in the EEPROM to read
762 * data - word read from the EEPROM
763 *****************************************************************************/
765 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
766 uint16_t words, uint16_t *data)
768 struct e1000_eeprom_info *eeprom = &hw->eeprom;
773 /* If eeprom is not yet detected, do so now */
774 if (eeprom->word_size == 0)
775 e1000_init_eeprom_params(hw);
777 /* A check for invalid values: offset too large, too many words,
778 * and not enough words.
780 if ((offset >= eeprom->word_size) ||
781 (words > eeprom->word_size - offset) ||
783 DEBUGOUT("\"words\" parameter out of bounds."
784 "Words = %d, size = %d\n", offset, eeprom->word_size);
785 return -E1000_ERR_EEPROM;
788 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
789 * directly. In this case, we need to acquire the EEPROM so that
790 * FW or other port software does not interrupt.
792 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
793 hw->eeprom.use_eerd == false) {
795 /* Prepare the EEPROM for bit-bang reading */
796 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
797 return -E1000_ERR_EEPROM;
800 /* Eerd register EEPROM access requires no eeprom aquire/release */
801 if (eeprom->use_eerd == true)
802 return e1000_read_eeprom_eerd(hw, offset, words, data);
804 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
805 * acquired the EEPROM at this point, so any returns should relase it */
806 if (eeprom->type == e1000_eeprom_spi) {
808 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
810 if (e1000_spi_eeprom_ready(hw)) {
811 e1000_release_eeprom(hw);
812 return -E1000_ERR_EEPROM;
815 e1000_standby_eeprom(hw);
817 /* Some SPI eeproms use the 8th address bit embedded in
819 if ((eeprom->address_bits == 8) && (offset >= 128))
820 read_opcode |= EEPROM_A8_OPCODE_SPI;
822 /* Send the READ command (opcode + addr) */
823 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
824 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
825 eeprom->address_bits);
827 /* Read the data. The address of the eeprom internally
828 * increments with each byte (spi) being read, saving on the
829 * overhead of eeprom setup and tear-down. The address
830 * counter will roll over if reading beyond the size of
831 * the eeprom, thus allowing the entire memory to be read
832 * starting from any offset. */
833 for (i = 0; i < words; i++) {
834 word_in = e1000_shift_in_ee_bits(hw, 16);
835 data[i] = (word_in >> 8) | (word_in << 8);
837 } else if (eeprom->type == e1000_eeprom_microwire) {
838 for (i = 0; i < words; i++) {
839 /* Send the READ command (opcode + addr) */
840 e1000_shift_out_ee_bits(hw,
841 EEPROM_READ_OPCODE_MICROWIRE,
842 eeprom->opcode_bits);
843 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
844 eeprom->address_bits);
846 /* Read the data. For microwire, each word requires
847 * the overhead of eeprom setup and tear-down. */
848 data[i] = e1000_shift_in_ee_bits(hw, 16);
849 e1000_standby_eeprom(hw);
853 /* End this read operation */
854 e1000_release_eeprom(hw);
856 return E1000_SUCCESS;
859 /******************************************************************************
860 * Verifies that the EEPROM has a valid checksum
862 * hw - Struct containing variables accessed by shared code
864 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
865 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
867 *****************************************************************************/
868 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
870 uint16_t i, checksum, checksum_reg, *buf;
874 /* Allocate a temporary buffer */
875 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
877 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
878 return -E1000_ERR_EEPROM;
881 /* Read the EEPROM */
882 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
883 E1000_ERR(hw, "Unable to read EEPROM!\n");
884 return -E1000_ERR_EEPROM;
887 /* Compute the checksum */
889 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
891 checksum = ((uint16_t)EEPROM_SUM) - checksum;
892 checksum_reg = buf[i];
895 if (checksum == checksum_reg)
898 /* Hrm, verification failed, print an error */
899 E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
900 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
901 checksum_reg, checksum);
903 return -E1000_ERR_EEPROM;
905 #endif /* CONFIG_E1000_NO_NVM */
907 /*****************************************************************************
908 * Set PHY to class A mode
909 * Assumes the following operations will follow to enable the new class mode.
910 * 1. Do a PHY soft reset
911 * 2. Restart auto-negotiation or force link.
913 * hw - Struct containing variables accessed by shared code
914 ****************************************************************************/
916 e1000_set_phy_mode(struct e1000_hw *hw)
918 #ifndef CONFIG_E1000_NO_NVM
920 uint16_t eeprom_data;
924 if ((hw->mac_type == e1000_82545_rev_3) &&
925 (hw->media_type == e1000_media_type_copper)) {
926 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
931 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
932 (eeprom_data & EEPROM_PHY_CLASS_A)) {
933 ret_val = e1000_write_phy_reg(hw,
934 M88E1000_PHY_PAGE_SELECT, 0x000B);
937 ret_val = e1000_write_phy_reg(hw,
938 M88E1000_PHY_GEN_CONTROL, 0x8104);
942 hw->phy_reset_disable = false;
946 return E1000_SUCCESS;
949 #ifndef CONFIG_E1000_NO_NVM
950 /***************************************************************************
952 * Obtaining software semaphore bit (SMBI) before resetting PHY.
954 * hw: Struct containing variables accessed by shared code
956 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
957 * E1000_SUCCESS at any other case.
959 ***************************************************************************/
961 e1000_get_software_semaphore(struct e1000_hw *hw)
963 int32_t timeout = hw->eeprom.word_size + 1;
968 if (hw->mac_type != e1000_80003es2lan)
969 return E1000_SUCCESS;
972 swsm = E1000_READ_REG(hw, SWSM);
973 /* If SMBI bit cleared, it is now set and we hold
975 if (!(swsm & E1000_SWSM_SMBI))
982 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
983 return -E1000_ERR_RESET;
986 return E1000_SUCCESS;
990 /***************************************************************************
991 * This function clears HW semaphore bits.
993 * hw: Struct containing variables accessed by shared code
997 ***************************************************************************/
999 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1001 #ifndef CONFIG_E1000_NO_NVM
1006 if (!hw->eeprom_semaphore_present)
1009 swsm = E1000_READ_REG(hw, SWSM);
1010 if (hw->mac_type == e1000_80003es2lan) {
1011 /* Release both semaphores. */
1012 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1014 swsm &= ~(E1000_SWSM_SWESMBI);
1015 E1000_WRITE_REG(hw, SWSM, swsm);
1019 /***************************************************************************
1021 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1022 * adapter or Eeprom access.
1024 * hw: Struct containing variables accessed by shared code
1026 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1027 * E1000_SUCCESS at any other case.
1029 ***************************************************************************/
1031 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1033 #ifndef CONFIG_E1000_NO_NVM
1039 if (!hw->eeprom_semaphore_present)
1040 return E1000_SUCCESS;
1042 if (hw->mac_type == e1000_80003es2lan) {
1043 /* Get the SW semaphore. */
1044 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1045 return -E1000_ERR_EEPROM;
1048 /* Get the FW semaphore. */
1049 timeout = hw->eeprom.word_size + 1;
1051 swsm = E1000_READ_REG(hw, SWSM);
1052 swsm |= E1000_SWSM_SWESMBI;
1053 E1000_WRITE_REG(hw, SWSM, swsm);
1054 /* if we managed to set the bit we got the semaphore. */
1055 swsm = E1000_READ_REG(hw, SWSM);
1056 if (swsm & E1000_SWSM_SWESMBI)
1064 /* Release semaphores */
1065 e1000_put_hw_eeprom_semaphore(hw);
1066 DEBUGOUT("Driver can't access the Eeprom - "
1067 "SWESMBI bit is set.\n");
1068 return -E1000_ERR_EEPROM;
1071 return E1000_SUCCESS;
1074 /* Take ownership of the PHY */
1076 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1078 uint32_t swfw_sync = 0;
1079 uint32_t swmask = mask;
1080 uint32_t fwmask = mask << 16;
1081 int32_t timeout = 200;
1085 if (e1000_get_hw_eeprom_semaphore(hw))
1086 return -E1000_ERR_SWFW_SYNC;
1088 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1089 if (!(swfw_sync & (fwmask | swmask)))
1092 /* firmware currently using resource (fwmask) */
1093 /* or other software thread currently using resource (swmask) */
1094 e1000_put_hw_eeprom_semaphore(hw);
1100 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1101 return -E1000_ERR_SWFW_SYNC;
1104 swfw_sync |= swmask;
1105 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1107 e1000_put_hw_eeprom_semaphore(hw);
1108 return E1000_SUCCESS;
1111 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1113 uint32_t swfw_sync = 0;
1116 while (e1000_get_hw_eeprom_semaphore(hw))
1119 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1121 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1123 e1000_put_hw_eeprom_semaphore(hw);
1126 static bool e1000_is_second_port(struct e1000_hw *hw)
1128 switch (hw->mac_type) {
1129 case e1000_80003es2lan:
1132 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1140 #ifndef CONFIG_E1000_NO_NVM
1141 /******************************************************************************
1142 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1143 * second function of dual function devices
1145 * nic - Struct containing variables accessed by shared code
1146 *****************************************************************************/
1148 e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1151 uint16_t eeprom_data;
1152 uint32_t reg_data = 0;
1157 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1159 if (hw->mac_type == e1000_igb) {
1160 /* i210 preloads MAC address into RAL/RAH registers */
1162 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1163 else if (offset == 1)
1165 else if (offset == 2)
1166 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1167 eeprom_data = reg_data & 0xffff;
1168 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1169 DEBUGOUT("EEPROM Read Error\n");
1170 return -E1000_ERR_EEPROM;
1172 enetaddr[i] = eeprom_data & 0xff;
1173 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1176 /* Invert the last bit if this is the second device */
1177 if (e1000_is_second_port(hw))
1184 /******************************************************************************
1185 * Initializes receive address filters.
1187 * hw - Struct containing variables accessed by shared code
1189 * Places the MAC address in receive address register 0 and clears the rest
1190 * of the receive addresss registers. Clears the multicast table. Assumes
1191 * the receiver is in reset when the routine is called.
1192 *****************************************************************************/
1194 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
1202 /* Setup the receive address. */
1203 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1204 addr_low = (enetaddr[0] |
1205 (enetaddr[1] << 8) |
1206 (enetaddr[2] << 16) | (enetaddr[3] << 24));
1208 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
1210 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1211 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1213 /* Zero out the other 15 receive addresses. */
1214 DEBUGOUT("Clearing RAR[1-15]\n");
1215 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1216 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1217 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1221 /******************************************************************************
1222 * Clears the VLAN filer table
1224 * hw - Struct containing variables accessed by shared code
1225 *****************************************************************************/
1227 e1000_clear_vfta(struct e1000_hw *hw)
1231 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1232 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1235 /******************************************************************************
1236 * Set the mac type member in the hw struct.
1238 * hw - Struct containing variables accessed by shared code
1239 *****************************************************************************/
1241 e1000_set_mac_type(struct e1000_hw *hw)
1245 switch (hw->device_id) {
1246 case E1000_DEV_ID_82542:
1247 switch (hw->revision_id) {
1248 case E1000_82542_2_0_REV_ID:
1249 hw->mac_type = e1000_82542_rev2_0;
1251 case E1000_82542_2_1_REV_ID:
1252 hw->mac_type = e1000_82542_rev2_1;
1255 /* Invalid 82542 revision ID */
1256 return -E1000_ERR_MAC_TYPE;
1259 case E1000_DEV_ID_82543GC_FIBER:
1260 case E1000_DEV_ID_82543GC_COPPER:
1261 hw->mac_type = e1000_82543;
1263 case E1000_DEV_ID_82544EI_COPPER:
1264 case E1000_DEV_ID_82544EI_FIBER:
1265 case E1000_DEV_ID_82544GC_COPPER:
1266 case E1000_DEV_ID_82544GC_LOM:
1267 hw->mac_type = e1000_82544;
1269 case E1000_DEV_ID_82540EM:
1270 case E1000_DEV_ID_82540EM_LOM:
1271 case E1000_DEV_ID_82540EP:
1272 case E1000_DEV_ID_82540EP_LOM:
1273 case E1000_DEV_ID_82540EP_LP:
1274 hw->mac_type = e1000_82540;
1276 case E1000_DEV_ID_82545EM_COPPER:
1277 case E1000_DEV_ID_82545EM_FIBER:
1278 hw->mac_type = e1000_82545;
1280 case E1000_DEV_ID_82545GM_COPPER:
1281 case E1000_DEV_ID_82545GM_FIBER:
1282 case E1000_DEV_ID_82545GM_SERDES:
1283 hw->mac_type = e1000_82545_rev_3;
1285 case E1000_DEV_ID_82546EB_COPPER:
1286 case E1000_DEV_ID_82546EB_FIBER:
1287 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1288 hw->mac_type = e1000_82546;
1290 case E1000_DEV_ID_82546GB_COPPER:
1291 case E1000_DEV_ID_82546GB_FIBER:
1292 case E1000_DEV_ID_82546GB_SERDES:
1293 case E1000_DEV_ID_82546GB_PCIE:
1294 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1295 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1296 hw->mac_type = e1000_82546_rev_3;
1298 case E1000_DEV_ID_82541EI:
1299 case E1000_DEV_ID_82541EI_MOBILE:
1300 case E1000_DEV_ID_82541ER_LOM:
1301 hw->mac_type = e1000_82541;
1303 case E1000_DEV_ID_82541ER:
1304 case E1000_DEV_ID_82541GI:
1305 case E1000_DEV_ID_82541GI_LF:
1306 case E1000_DEV_ID_82541GI_MOBILE:
1307 hw->mac_type = e1000_82541_rev_2;
1309 case E1000_DEV_ID_82547EI:
1310 case E1000_DEV_ID_82547EI_MOBILE:
1311 hw->mac_type = e1000_82547;
1313 case E1000_DEV_ID_82547GI:
1314 hw->mac_type = e1000_82547_rev_2;
1316 case E1000_DEV_ID_82571EB_COPPER:
1317 case E1000_DEV_ID_82571EB_FIBER:
1318 case E1000_DEV_ID_82571EB_SERDES:
1319 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1320 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1321 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1322 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1323 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1324 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1325 hw->mac_type = e1000_82571;
1327 case E1000_DEV_ID_82572EI_COPPER:
1328 case E1000_DEV_ID_82572EI_FIBER:
1329 case E1000_DEV_ID_82572EI_SERDES:
1330 case E1000_DEV_ID_82572EI:
1331 hw->mac_type = e1000_82572;
1333 case E1000_DEV_ID_82573E:
1334 case E1000_DEV_ID_82573E_IAMT:
1335 case E1000_DEV_ID_82573L:
1336 hw->mac_type = e1000_82573;
1338 case E1000_DEV_ID_82574L:
1339 hw->mac_type = e1000_82574;
1341 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1342 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1343 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1344 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1345 hw->mac_type = e1000_80003es2lan;
1347 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1348 case E1000_DEV_ID_ICH8_IGP_AMT:
1349 case E1000_DEV_ID_ICH8_IGP_C:
1350 case E1000_DEV_ID_ICH8_IFE:
1351 case E1000_DEV_ID_ICH8_IFE_GT:
1352 case E1000_DEV_ID_ICH8_IFE_G:
1353 case E1000_DEV_ID_ICH8_IGP_M:
1354 hw->mac_type = e1000_ich8lan;
1356 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1357 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1358 case PCI_DEVICE_ID_INTEL_I210_COPPER:
1359 case PCI_DEVICE_ID_INTEL_I211_COPPER:
1360 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1361 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1362 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1363 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1364 hw->mac_type = e1000_igb;
1367 /* Should never have loaded on this device */
1368 return -E1000_ERR_MAC_TYPE;
1370 return E1000_SUCCESS;
1373 /******************************************************************************
1374 * Reset the transmit and receive units; mask and clear all interrupts.
1376 * hw - Struct containing variables accessed by shared code
1377 *****************************************************************************/
1379 e1000_reset_hw(struct e1000_hw *hw)
1389 /* get the correct pba value for both PCI and PCIe*/
1390 if (hw->mac_type < e1000_82571)
1391 pba = E1000_DEFAULT_PCI_PBA;
1393 pba = E1000_DEFAULT_PCIE_PBA;
1395 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1396 if (hw->mac_type == e1000_82542_rev2_0) {
1397 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1398 pci_write_config_word(hw->pdev, PCI_COMMAND,
1399 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1402 /* Clear interrupt mask to stop board from generating interrupts */
1403 DEBUGOUT("Masking off all interrupts\n");
1404 if (hw->mac_type == e1000_igb)
1405 E1000_WRITE_REG(hw, I210_IAM, 0);
1406 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1408 /* Disable the Transmit and Receive units. Then delay to allow
1409 * any pending transactions to complete before we hit the MAC with
1412 E1000_WRITE_REG(hw, RCTL, 0);
1413 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1414 E1000_WRITE_FLUSH(hw);
1416 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1417 hw->tbi_compatibility_on = false;
1419 /* Delay to allow any outstanding PCI transactions to complete before
1420 * resetting the device
1424 /* Issue a global reset to the MAC. This will reset the chip's
1425 * transmit, receive, DMA, and link units. It will not effect
1426 * the current PCI configuration. The global reset bit is self-
1427 * clearing, and should clear within a microsecond.
1429 DEBUGOUT("Issuing a global reset to MAC\n");
1430 ctrl = E1000_READ_REG(hw, CTRL);
1432 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1434 /* Force a reload from the EEPROM if necessary */
1435 if (hw->mac_type == e1000_igb) {
1437 reg = E1000_READ_REG(hw, STATUS);
1438 if (reg & E1000_STATUS_PF_RST_DONE)
1439 DEBUGOUT("PF OK\n");
1440 reg = E1000_READ_REG(hw, I210_EECD);
1441 if (reg & E1000_EECD_AUTO_RD)
1442 DEBUGOUT("EEC OK\n");
1443 } else if (hw->mac_type < e1000_82540) {
1444 /* Wait for reset to complete */
1446 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1447 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1448 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1449 E1000_WRITE_FLUSH(hw);
1450 /* Wait for EEPROM reload */
1453 /* Wait for EEPROM reload (it happens automatically) */
1455 /* Dissable HW ARPs on ASF enabled adapters */
1456 manc = E1000_READ_REG(hw, MANC);
1457 manc &= ~(E1000_MANC_ARP_EN);
1458 E1000_WRITE_REG(hw, MANC, manc);
1461 /* Clear interrupt mask to stop board from generating interrupts */
1462 DEBUGOUT("Masking off all interrupts\n");
1463 if (hw->mac_type == e1000_igb)
1464 E1000_WRITE_REG(hw, I210_IAM, 0);
1465 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1467 /* Clear any pending interrupt events. */
1468 E1000_READ_REG(hw, ICR);
1470 /* If MWI was previously enabled, reenable it. */
1471 if (hw->mac_type == e1000_82542_rev2_0) {
1472 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1474 if (hw->mac_type != e1000_igb)
1475 E1000_WRITE_REG(hw, PBA, pba);
1478 /******************************************************************************
1480 * Initialize a number of hardware-dependent bits
1482 * hw: Struct containing variables accessed by shared code
1484 * This function contains hardware limitation workarounds for PCI-E adapters
1486 *****************************************************************************/
1488 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1490 if ((hw->mac_type >= e1000_82571) &&
1491 (!hw->initialize_hw_bits_disable)) {
1492 /* Settings common to all PCI-express silicon */
1493 uint32_t reg_ctrl, reg_ctrl_ext;
1494 uint32_t reg_tarc0, reg_tarc1;
1496 uint32_t reg_txdctl, reg_txdctl1;
1498 /* link autonegotiation/sync workarounds */
1499 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1500 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1502 /* Enable not-done TX descriptor counting */
1503 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1504 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1505 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1507 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1508 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1509 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1512 if (hw->mac_type == e1000_igb)
1515 switch (hw->mac_type) {
1518 /* Clear PHY TX compatible mode bits */
1519 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1520 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1522 /* link autonegotiation/sync workarounds */
1523 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1525 /* TX ring control fixes */
1526 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1528 /* Multiple read bit is reversed polarity */
1529 reg_tctl = E1000_READ_REG(hw, TCTL);
1530 if (reg_tctl & E1000_TCTL_MULR)
1531 reg_tarc1 &= ~(1 << 28);
1533 reg_tarc1 |= (1 << 28);
1535 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1539 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1540 reg_ctrl_ext &= ~(1 << 23);
1541 reg_ctrl_ext |= (1 << 22);
1543 /* TX byte count fix */
1544 reg_ctrl = E1000_READ_REG(hw, CTRL);
1545 reg_ctrl &= ~(1 << 29);
1547 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1548 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1550 case e1000_80003es2lan:
1551 /* improve small packet performace for fiber/serdes */
1552 if ((hw->media_type == e1000_media_type_fiber)
1553 || (hw->media_type ==
1554 e1000_media_type_internal_serdes)) {
1555 reg_tarc0 &= ~(1 << 20);
1558 /* Multiple read bit is reversed polarity */
1559 reg_tctl = E1000_READ_REG(hw, TCTL);
1560 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1561 if (reg_tctl & E1000_TCTL_MULR)
1562 reg_tarc1 &= ~(1 << 28);
1564 reg_tarc1 |= (1 << 28);
1566 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1569 /* Reduce concurrent DMA requests to 3 from 4 */
1570 if ((hw->revision_id < 3) ||
1571 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1572 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1573 reg_tarc0 |= ((1 << 29)|(1 << 28));
1575 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1576 reg_ctrl_ext |= (1 << 22);
1577 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1579 /* workaround TX hang with TSO=on */
1580 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1582 /* Multiple read bit is reversed polarity */
1583 reg_tctl = E1000_READ_REG(hw, TCTL);
1584 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1585 if (reg_tctl & E1000_TCTL_MULR)
1586 reg_tarc1 &= ~(1 << 28);
1588 reg_tarc1 |= (1 << 28);
1590 /* workaround TX hang with TSO=on */
1591 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1593 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1599 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1603 /******************************************************************************
1604 * Performs basic configuration of the adapter.
1606 * hw - Struct containing variables accessed by shared code
1608 * Assumes that the controller has previously been reset and is in a
1609 * post-reset uninitialized state. Initializes the receive address registers,
1610 * multicast table, and VLAN filter table. Calls routines to setup link
1611 * configuration and flow control settings. Clears all on-chip counters. Leaves
1612 * the transmit and receive units disabled and uninitialized.
1613 *****************************************************************************/
1615 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
1620 uint16_t pcix_cmd_word;
1621 uint16_t pcix_stat_hi_word;
1623 uint16_t stat_mmrbc;
1628 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1629 if ((hw->mac_type == e1000_ich8lan) &&
1630 ((hw->revision_id < 3) ||
1631 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1632 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1633 reg_data = E1000_READ_REG(hw, STATUS);
1634 reg_data &= ~0x80000000;
1635 E1000_WRITE_REG(hw, STATUS, reg_data);
1637 /* Do not need initialize Identification LED */
1639 /* Set the media type and TBI compatibility */
1640 e1000_set_media_type(hw);
1642 /* Must be called after e1000_set_media_type
1643 * because media_type is used */
1644 e1000_initialize_hardware_bits(hw);
1646 /* Disabling VLAN filtering. */
1647 DEBUGOUT("Initializing the IEEE VLAN\n");
1648 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1649 if (hw->mac_type != e1000_ich8lan) {
1650 if (hw->mac_type < e1000_82545_rev_3)
1651 E1000_WRITE_REG(hw, VET, 0);
1652 e1000_clear_vfta(hw);
1655 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1656 if (hw->mac_type == e1000_82542_rev2_0) {
1657 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1658 pci_write_config_word(hw->pdev, PCI_COMMAND,
1660 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1661 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1662 E1000_WRITE_FLUSH(hw);
1666 /* Setup the receive address. This involves initializing all of the Receive
1667 * Address Registers (RARs 0 - 15).
1669 e1000_init_rx_addrs(hw, enetaddr);
1671 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1672 if (hw->mac_type == e1000_82542_rev2_0) {
1673 E1000_WRITE_REG(hw, RCTL, 0);
1674 E1000_WRITE_FLUSH(hw);
1676 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1679 /* Zero out the Multicast HASH table */
1680 DEBUGOUT("Zeroing the MTA\n");
1681 mta_size = E1000_MC_TBL_SIZE;
1682 if (hw->mac_type == e1000_ich8lan)
1683 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1684 for (i = 0; i < mta_size; i++) {
1685 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1686 /* use write flush to prevent Memory Write Block (MWB) from
1687 * occuring when accessing our register space */
1688 E1000_WRITE_FLUSH(hw);
1691 switch (hw->mac_type) {
1692 case e1000_82545_rev_3:
1693 case e1000_82546_rev_3:
1697 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1698 if (hw->bus_type == e1000_bus_type_pcix) {
1699 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1701 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1702 &pcix_stat_hi_word);
1704 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1705 PCIX_COMMAND_MMRBC_SHIFT;
1707 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1708 PCIX_STATUS_HI_MMRBC_SHIFT;
1709 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1710 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1711 if (cmd_mmrbc > stat_mmrbc) {
1712 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1713 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1714 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1721 /* More time needed for PHY to initialize */
1722 if (hw->mac_type == e1000_ich8lan)
1724 if (hw->mac_type == e1000_igb)
1727 /* Call a subroutine to configure the link and setup flow control. */
1728 ret_val = e1000_setup_link(hw);
1730 /* Set the transmit descriptor write-back policy */
1731 if (hw->mac_type > e1000_82544) {
1732 ctrl = E1000_READ_REG(hw, TXDCTL);
1734 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1735 E1000_TXDCTL_FULL_TX_DESC_WB;
1736 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1739 /* Set the receive descriptor write back policy */
1740 if (hw->mac_type >= e1000_82571) {
1741 ctrl = E1000_READ_REG(hw, RXDCTL);
1743 (ctrl & ~E1000_RXDCTL_WTHRESH) |
1744 E1000_RXDCTL_FULL_RX_DESC_WB;
1745 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1748 switch (hw->mac_type) {
1751 case e1000_80003es2lan:
1752 /* Enable retransmit on late collisions */
1753 reg_data = E1000_READ_REG(hw, TCTL);
1754 reg_data |= E1000_TCTL_RTLC;
1755 E1000_WRITE_REG(hw, TCTL, reg_data);
1757 /* Configure Gigabit Carry Extend Padding */
1758 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1759 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1760 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1761 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1763 /* Configure Transmit Inter-Packet Gap */
1764 reg_data = E1000_READ_REG(hw, TIPG);
1765 reg_data &= ~E1000_TIPG_IPGT_MASK;
1766 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1767 E1000_WRITE_REG(hw, TIPG, reg_data);
1769 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1770 reg_data &= ~0x00100000;
1771 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1776 ctrl = E1000_READ_REG(hw, TXDCTL1);
1777 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1778 | E1000_TXDCTL_FULL_TX_DESC_WB;
1779 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1783 reg_data = E1000_READ_REG(hw, GCR);
1784 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1785 E1000_WRITE_REG(hw, GCR, reg_data);
1790 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1791 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1792 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1793 /* Relaxed ordering must be disabled to avoid a parity
1794 * error crash in a PCI slot. */
1795 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1796 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1802 /******************************************************************************
1803 * Configures flow control and link settings.
1805 * hw - Struct containing variables accessed by shared code
1807 * Determines which flow control settings to use. Calls the apropriate media-
1808 * specific link configuration function. Configures the flow control settings.
1809 * Assuming the adapter has a valid link partner, a valid link should be
1810 * established. Assumes the hardware has previously been reset and the
1811 * transmitter and receiver are not enabled.
1812 *****************************************************************************/
1814 e1000_setup_link(struct e1000_hw *hw)
1817 #ifndef CONFIG_E1000_NO_NVM
1819 uint16_t eeprom_data;
1824 /* In the case of the phy reset being blocked, we already have a link.
1825 * We do not have to set it up again. */
1826 if (e1000_check_phy_reset_block(hw))
1827 return E1000_SUCCESS;
1829 #ifndef CONFIG_E1000_NO_NVM
1830 /* Read and store word 0x0F of the EEPROM. This word contains bits
1831 * that determine the hardware's default PAUSE (flow control) mode,
1832 * a bit that determines whether the HW defaults to enabling or
1833 * disabling auto-negotiation, and the direction of the
1834 * SW defined pins. If there is no SW over-ride of the flow
1835 * control setting, then the variable hw->fc will
1836 * be initialized based on a value in the EEPROM.
1838 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1839 &eeprom_data) < 0) {
1840 DEBUGOUT("EEPROM Read Error\n");
1841 return -E1000_ERR_EEPROM;
1844 if (hw->fc == e1000_fc_default) {
1845 switch (hw->mac_type) {
1850 hw->fc = e1000_fc_full;
1853 #ifndef CONFIG_E1000_NO_NVM
1854 ret_val = e1000_read_eeprom(hw,
1855 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1857 DEBUGOUT("EEPROM Read Error\n");
1858 return -E1000_ERR_EEPROM;
1860 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1861 hw->fc = e1000_fc_none;
1862 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1863 EEPROM_WORD0F_ASM_DIR)
1864 hw->fc = e1000_fc_tx_pause;
1867 hw->fc = e1000_fc_full;
1872 /* We want to save off the original Flow Control configuration just
1873 * in case we get disconnected and then reconnected into a different
1874 * hub or switch with different Flow Control capabilities.
1876 if (hw->mac_type == e1000_82542_rev2_0)
1877 hw->fc &= (~e1000_fc_tx_pause);
1879 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1880 hw->fc &= (~e1000_fc_rx_pause);
1882 hw->original_fc = hw->fc;
1884 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1886 #ifndef CONFIG_E1000_NO_NVM
1887 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1888 * polarity value for the SW controlled pins, and setup the
1889 * Extended Device Control reg with that info.
1890 * This is needed because one of the SW controlled pins is used for
1891 * signal detection. So this should be done before e1000_setup_pcs_link()
1892 * or e1000_phy_setup() is called.
1894 if (hw->mac_type == e1000_82543) {
1895 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1897 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1901 /* Call the necessary subroutine to configure the link. */
1902 ret_val = (hw->media_type == e1000_media_type_fiber) ?
1903 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
1908 /* Initialize the flow control address, type, and PAUSE timer
1909 * registers to their default values. This is done even if flow
1910 * control is disabled, because it does not hurt anything to
1911 * initialize these registers.
1913 DEBUGOUT("Initializing the Flow Control address, type"
1914 "and timer regs\n");
1916 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1917 if (hw->mac_type != e1000_ich8lan) {
1918 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1919 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1920 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1923 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1925 /* Set the flow control receive threshold registers. Normally,
1926 * these registers will be set to a default threshold that may be
1927 * adjusted later by the driver's runtime code. However, if the
1928 * ability to transmit pause frames in not enabled, then these
1929 * registers will be set to 0.
1931 if (!(hw->fc & e1000_fc_tx_pause)) {
1932 E1000_WRITE_REG(hw, FCRTL, 0);
1933 E1000_WRITE_REG(hw, FCRTH, 0);
1935 /* We need to set up the Receive Threshold high and low water marks
1936 * as well as (optionally) enabling the transmission of XON frames.
1938 if (hw->fc_send_xon) {
1939 E1000_WRITE_REG(hw, FCRTL,
1940 (hw->fc_low_water | E1000_FCRTL_XONE));
1941 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1943 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1944 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1950 /******************************************************************************
1951 * Sets up link for a fiber based adapter
1953 * hw - Struct containing variables accessed by shared code
1955 * Manipulates Physical Coding Sublayer functions in order to configure
1956 * link. Assumes the hardware has been previously reset and the transmitter
1957 * and receiver are not enabled.
1958 *****************************************************************************/
1960 e1000_setup_fiber_link(struct e1000_hw *hw)
1970 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1971 * set when the optics detect a signal. On older adapters, it will be
1972 * cleared when there is a signal
1974 ctrl = E1000_READ_REG(hw, CTRL);
1975 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1976 signal = E1000_CTRL_SWDPIN1;
1980 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
1982 /* Take the link out of reset */
1983 ctrl &= ~(E1000_CTRL_LRST);
1985 e1000_config_collision_dist(hw);
1987 /* Check for a software override of the flow control settings, and setup
1988 * the device accordingly. If auto-negotiation is enabled, then software
1989 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1990 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1991 * auto-negotiation is disabled, then software will have to manually
1992 * configure the two flow control enable bits in the CTRL register.
1994 * The possible values of the "fc" parameter are:
1995 * 0: Flow control is completely disabled
1996 * 1: Rx flow control is enabled (we can receive pause frames, but
1997 * not send pause frames).
1998 * 2: Tx flow control is enabled (we can send pause frames but we do
1999 * not support receiving pause frames).
2000 * 3: Both Rx and TX flow control (symmetric) are enabled.
2004 /* Flow control is completely disabled by a software over-ride. */
2005 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2007 case e1000_fc_rx_pause:
2008 /* RX Flow control is enabled and TX Flow control is disabled by a
2009 * software over-ride. Since there really isn't a way to advertise
2010 * that we are capable of RX Pause ONLY, we will advertise that we
2011 * support both symmetric and asymmetric RX PAUSE. Later, we will
2012 * disable the adapter's ability to send PAUSE frames.
2014 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2016 case e1000_fc_tx_pause:
2017 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2018 * software over-ride.
2020 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2023 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2024 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2027 DEBUGOUT("Flow control param set incorrectly\n");
2028 return -E1000_ERR_CONFIG;
2032 /* Since auto-negotiation is enabled, take the link out of reset (the link
2033 * will be in reset, because we previously reset the chip). This will
2034 * restart auto-negotiation. If auto-neogtiation is successful then the
2035 * link-up status bit will be set and the flow control enable bits (RFCE
2036 * and TFCE) will be set according to their negotiated value.
2038 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2040 E1000_WRITE_REG(hw, TXCW, txcw);
2041 E1000_WRITE_REG(hw, CTRL, ctrl);
2042 E1000_WRITE_FLUSH(hw);
2047 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2048 * indication in the Device Status Register. Time-out if a link isn't
2049 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2050 * less than 500 milliseconds even if the other end is doing it in SW).
2052 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2053 DEBUGOUT("Looking for Link\n");
2054 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2056 status = E1000_READ_REG(hw, STATUS);
2057 if (status & E1000_STATUS_LU)
2060 if (i == (LINK_UP_TIMEOUT / 10)) {
2061 /* AutoNeg failed to achieve a link, so we'll call
2062 * e1000_check_for_link. This routine will force the link up if we
2063 * detect a signal. This will allow us to communicate with
2064 * non-autonegotiating link partners.
2066 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2067 hw->autoneg_failed = 1;
2068 ret_val = e1000_check_for_link(hw);
2070 DEBUGOUT("Error while checking for link\n");
2073 hw->autoneg_failed = 0;
2075 hw->autoneg_failed = 0;
2076 DEBUGOUT("Valid Link Found\n");
2079 DEBUGOUT("No Signal Detected\n");
2080 return -E1000_ERR_NOLINK;
2085 /******************************************************************************
2086 * Make sure we have a valid PHY and change PHY mode before link setup.
2088 * hw - Struct containing variables accessed by shared code
2089 ******************************************************************************/
2091 e1000_copper_link_preconfig(struct e1000_hw *hw)
2099 ctrl = E1000_READ_REG(hw, CTRL);
2100 /* With 82543, we need to force speed and duplex on the MAC equal to what
2101 * the PHY speed and duplex configuration is. In addition, we need to
2102 * perform a hardware reset on the PHY to take it out of reset.
2104 if (hw->mac_type > e1000_82543) {
2105 ctrl |= E1000_CTRL_SLU;
2106 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2107 E1000_WRITE_REG(hw, CTRL, ctrl);
2109 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2111 E1000_WRITE_REG(hw, CTRL, ctrl);
2112 ret_val = e1000_phy_hw_reset(hw);
2117 /* Make sure we have a valid PHY */
2118 ret_val = e1000_detect_gig_phy(hw);
2120 DEBUGOUT("Error, did not detect valid phy.\n");
2123 DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2125 /* Set PHY to class A mode (if necessary) */
2126 ret_val = e1000_set_phy_mode(hw);
2129 if ((hw->mac_type == e1000_82545_rev_3) ||
2130 (hw->mac_type == e1000_82546_rev_3)) {
2131 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2133 phy_data |= 0x00000008;
2134 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2138 if (hw->mac_type <= e1000_82543 ||
2139 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2140 hw->mac_type == e1000_82541_rev_2
2141 || hw->mac_type == e1000_82547_rev_2)
2142 hw->phy_reset_disable = false;
2144 return E1000_SUCCESS;
2147 /*****************************************************************************
2149 * This function sets the lplu state according to the active flag. When
2150 * activating lplu this function also disables smart speed and vise versa.
2151 * lplu will not be activated unless the device autonegotiation advertisment
2152 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2153 * hw: Struct containing variables accessed by shared code
2154 * active - true to enable lplu false to disable lplu.
2156 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2157 * E1000_SUCCESS at any other case.
2159 ****************************************************************************/
2162 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2164 uint32_t phy_ctrl = 0;
2169 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2170 && hw->phy_type != e1000_phy_igp_3)
2171 return E1000_SUCCESS;
2173 /* During driver activity LPLU should not be used or it will attain link
2174 * from the lowest speeds starting from 10Mbps. The capability is used
2175 * for Dx transitions and states */
2176 if (hw->mac_type == e1000_82541_rev_2
2177 || hw->mac_type == e1000_82547_rev_2) {
2178 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2182 } else if (hw->mac_type == e1000_ich8lan) {
2183 /* MAC writes into PHY register based on the state transition
2184 * and start auto-negotiation. SW driver can overwrite the
2185 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2186 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2188 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2195 if (hw->mac_type == e1000_82541_rev_2 ||
2196 hw->mac_type == e1000_82547_rev_2) {
2197 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2198 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2203 if (hw->mac_type == e1000_ich8lan) {
2204 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2205 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2207 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2208 ret_val = e1000_write_phy_reg(hw,
2209 IGP02E1000_PHY_POWER_MGMT, phy_data);
2215 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2216 * Dx states where the power conservation is most important. During
2217 * driver activity we should enable SmartSpeed, so performance is
2219 if (hw->smart_speed == e1000_smart_speed_on) {
2220 ret_val = e1000_read_phy_reg(hw,
2221 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2225 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2226 ret_val = e1000_write_phy_reg(hw,
2227 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2230 } else if (hw->smart_speed == e1000_smart_speed_off) {
2231 ret_val = e1000_read_phy_reg(hw,
2232 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2236 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2237 ret_val = e1000_write_phy_reg(hw,
2238 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2243 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2244 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2245 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2247 if (hw->mac_type == e1000_82541_rev_2 ||
2248 hw->mac_type == e1000_82547_rev_2) {
2249 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2250 ret_val = e1000_write_phy_reg(hw,
2251 IGP01E1000_GMII_FIFO, phy_data);
2255 if (hw->mac_type == e1000_ich8lan) {
2256 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2257 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2259 phy_data |= IGP02E1000_PM_D3_LPLU;
2260 ret_val = e1000_write_phy_reg(hw,
2261 IGP02E1000_PHY_POWER_MGMT, phy_data);
2267 /* When LPLU is enabled we should disable SmartSpeed */
2268 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2273 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2274 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2279 return E1000_SUCCESS;
2282 /*****************************************************************************
2284 * This function sets the lplu d0 state according to the active flag. When
2285 * activating lplu this function also disables smart speed and vise versa.
2286 * lplu will not be activated unless the device autonegotiation advertisment
2287 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2288 * hw: Struct containing variables accessed by shared code
2289 * active - true to enable lplu false to disable lplu.
2291 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2292 * E1000_SUCCESS at any other case.
2294 ****************************************************************************/
2297 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2299 uint32_t phy_ctrl = 0;
2304 if (hw->mac_type <= e1000_82547_rev_2)
2305 return E1000_SUCCESS;
2307 if (hw->mac_type == e1000_ich8lan) {
2308 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2309 } else if (hw->mac_type == e1000_igb) {
2310 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2312 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2319 if (hw->mac_type == e1000_ich8lan) {
2320 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2321 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2322 } else if (hw->mac_type == e1000_igb) {
2323 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2324 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2326 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2327 ret_val = e1000_write_phy_reg(hw,
2328 IGP02E1000_PHY_POWER_MGMT, phy_data);
2333 if (hw->mac_type == e1000_igb)
2334 return E1000_SUCCESS;
2336 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2337 * Dx states where the power conservation is most important. During
2338 * driver activity we should enable SmartSpeed, so performance is
2340 if (hw->smart_speed == e1000_smart_speed_on) {
2341 ret_val = e1000_read_phy_reg(hw,
2342 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2346 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2347 ret_val = e1000_write_phy_reg(hw,
2348 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2351 } else if (hw->smart_speed == e1000_smart_speed_off) {
2352 ret_val = e1000_read_phy_reg(hw,
2353 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2357 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2358 ret_val = e1000_write_phy_reg(hw,
2359 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2367 if (hw->mac_type == e1000_ich8lan) {
2368 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2369 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2370 } else if (hw->mac_type == e1000_igb) {
2371 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2372 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2374 phy_data |= IGP02E1000_PM_D0_LPLU;
2375 ret_val = e1000_write_phy_reg(hw,
2376 IGP02E1000_PHY_POWER_MGMT, phy_data);
2381 if (hw->mac_type == e1000_igb)
2382 return E1000_SUCCESS;
2384 /* When LPLU is enabled we should disable SmartSpeed */
2385 ret_val = e1000_read_phy_reg(hw,
2386 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2390 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2391 ret_val = e1000_write_phy_reg(hw,
2392 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2397 return E1000_SUCCESS;
2400 /********************************************************************
2401 * Copper link setup for e1000_phy_igp series.
2403 * hw - Struct containing variables accessed by shared code
2404 *********************************************************************/
2406 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2414 if (hw->phy_reset_disable)
2415 return E1000_SUCCESS;
2417 ret_val = e1000_phy_reset(hw);
2419 DEBUGOUT("Error Resetting the PHY\n");
2423 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2425 if (hw->mac_type != e1000_ich8lan) {
2426 /* Configure activity LED after PHY reset */
2427 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2428 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2429 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2430 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2433 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2434 if (hw->phy_type == e1000_phy_igp) {
2435 /* disable lplu d3 during driver init */
2436 ret_val = e1000_set_d3_lplu_state(hw, false);
2438 DEBUGOUT("Error Disabling LPLU D3\n");
2443 /* disable lplu d0 during driver init */
2444 ret_val = e1000_set_d0_lplu_state(hw, false);
2446 DEBUGOUT("Error Disabling LPLU D0\n");
2449 /* Configure mdi-mdix settings */
2450 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2454 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2455 hw->dsp_config_state = e1000_dsp_config_disabled;
2456 /* Force MDI for earlier revs of the IGP PHY */
2457 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2458 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2462 hw->dsp_config_state = e1000_dsp_config_enabled;
2463 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2467 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2470 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2474 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2478 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2482 /* set auto-master slave resolution settings */
2484 e1000_ms_type phy_ms_setting = hw->master_slave;
2486 if (hw->ffe_config_state == e1000_ffe_config_active)
2487 hw->ffe_config_state = e1000_ffe_config_enabled;
2489 if (hw->dsp_config_state == e1000_dsp_config_activated)
2490 hw->dsp_config_state = e1000_dsp_config_enabled;
2492 /* when autonegotiation advertisment is only 1000Mbps then we
2493 * should disable SmartSpeed and enable Auto MasterSlave
2494 * resolution as hardware default. */
2495 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2496 /* Disable SmartSpeed */
2497 ret_val = e1000_read_phy_reg(hw,
2498 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2501 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2502 ret_val = e1000_write_phy_reg(hw,
2503 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2506 /* Set auto Master/Slave resolution process */
2507 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2511 phy_data &= ~CR_1000T_MS_ENABLE;
2512 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2518 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2522 /* load defaults for future use */
2523 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2524 ((phy_data & CR_1000T_MS_VALUE) ?
2525 e1000_ms_force_master :
2526 e1000_ms_force_slave) :
2529 switch (phy_ms_setting) {
2530 case e1000_ms_force_master:
2531 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2533 case e1000_ms_force_slave:
2534 phy_data |= CR_1000T_MS_ENABLE;
2535 phy_data &= ~(CR_1000T_MS_VALUE);
2538 phy_data &= ~CR_1000T_MS_ENABLE;
2542 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2547 return E1000_SUCCESS;
2550 /*****************************************************************************
2551 * This function checks the mode of the firmware.
2553 * returns - true when the mode is IAMT or false.
2554 ****************************************************************************/
2556 e1000_check_mng_mode(struct e1000_hw *hw)
2561 fwsm = E1000_READ_REG(hw, FWSM);
2563 if (hw->mac_type == e1000_ich8lan) {
2564 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2565 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2567 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2568 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2575 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2577 uint16_t swfw = E1000_SWFW_PHY0_SM;
2581 if (e1000_is_second_port(hw))
2582 swfw = E1000_SWFW_PHY1_SM;
2584 if (e1000_swfw_sync_acquire(hw, swfw))
2585 return -E1000_ERR_SWFW_SYNC;
2587 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2588 & E1000_KUMCTRLSTA_OFFSET) | data;
2589 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2592 return E1000_SUCCESS;
2596 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2598 uint16_t swfw = E1000_SWFW_PHY0_SM;
2602 if (e1000_is_second_port(hw))
2603 swfw = E1000_SWFW_PHY1_SM;
2605 if (e1000_swfw_sync_acquire(hw, swfw)) {
2606 debug("%s[%i]\n", __func__, __LINE__);
2607 return -E1000_ERR_SWFW_SYNC;
2610 /* Write register address */
2611 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2612 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2613 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2616 /* Read the data returned */
2617 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2618 *data = (uint16_t)reg_val;
2620 return E1000_SUCCESS;
2623 /********************************************************************
2624 * Copper link setup for e1000_phy_gg82563 series.
2626 * hw - Struct containing variables accessed by shared code
2627 *********************************************************************/
2629 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2637 if (!hw->phy_reset_disable) {
2638 /* Enable CRS on TX for half-duplex operation. */
2639 ret_val = e1000_read_phy_reg(hw,
2640 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2644 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2645 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2646 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2648 ret_val = e1000_write_phy_reg(hw,
2649 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2654 * MDI/MDI-X = 0 (default)
2655 * 0 - Auto for all speeds
2658 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2660 ret_val = e1000_read_phy_reg(hw,
2661 GG82563_PHY_SPEC_CTRL, &phy_data);
2665 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2669 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2672 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2676 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2681 * disable_polarity_correction = 0 (default)
2682 * Automatic Correction for Reversed Cable Polarity
2686 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2687 ret_val = e1000_write_phy_reg(hw,
2688 GG82563_PHY_SPEC_CTRL, phy_data);
2693 /* SW Reset the PHY so all changes take effect */
2694 ret_val = e1000_phy_reset(hw);
2696 DEBUGOUT("Error Resetting the PHY\n");
2699 } /* phy_reset_disable */
2701 if (hw->mac_type == e1000_80003es2lan) {
2702 /* Bypass RX and TX FIFO's */
2703 ret_val = e1000_write_kmrn_reg(hw,
2704 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2705 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2706 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2710 ret_val = e1000_read_phy_reg(hw,
2711 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2715 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2716 ret_val = e1000_write_phy_reg(hw,
2717 GG82563_PHY_SPEC_CTRL_2, phy_data);
2722 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2723 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2724 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2726 ret_val = e1000_read_phy_reg(hw,
2727 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2731 /* Do not init these registers when the HW is in IAMT mode, since the
2732 * firmware will have already initialized them. We only initialize
2733 * them if the HW is not in IAMT mode.
2735 if (e1000_check_mng_mode(hw) == false) {
2736 /* Enable Electrical Idle on the PHY */
2737 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2738 ret_val = e1000_write_phy_reg(hw,
2739 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2743 ret_val = e1000_read_phy_reg(hw,
2744 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2748 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2749 ret_val = e1000_write_phy_reg(hw,
2750 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2756 /* Workaround: Disable padding in Kumeran interface in the MAC
2757 * and in the PHY to avoid CRC errors.
2759 ret_val = e1000_read_phy_reg(hw,
2760 GG82563_PHY_INBAND_CTRL, &phy_data);
2763 phy_data |= GG82563_ICR_DIS_PADDING;
2764 ret_val = e1000_write_phy_reg(hw,
2765 GG82563_PHY_INBAND_CTRL, phy_data);
2769 return E1000_SUCCESS;
2772 /********************************************************************
2773 * Copper link setup for e1000_phy_m88 series.
2775 * hw - Struct containing variables accessed by shared code
2776 *********************************************************************/
2778 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2785 if (hw->phy_reset_disable)
2786 return E1000_SUCCESS;
2788 /* Enable CRS on TX. This must be set for half-duplex operation. */
2789 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2793 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2796 * MDI/MDI-X = 0 (default)
2797 * 0 - Auto for all speeds
2800 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2802 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2806 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2809 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2812 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2816 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2821 * disable_polarity_correction = 0 (default)
2822 * Automatic Correction for Reversed Cable Polarity
2826 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2827 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2831 if (hw->phy_revision < M88E1011_I_REV_4) {
2832 /* Force TX_CLK in the Extended PHY Specific Control Register
2835 ret_val = e1000_read_phy_reg(hw,
2836 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2840 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2842 if ((hw->phy_revision == E1000_REVISION_2) &&
2843 (hw->phy_id == M88E1111_I_PHY_ID)) {
2844 /* Vidalia Phy, set the downshift counter to 5x */
2845 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2846 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2847 ret_val = e1000_write_phy_reg(hw,
2848 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2852 /* Configure Master and Slave downshift values */
2853 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2854 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2855 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2856 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2857 ret_val = e1000_write_phy_reg(hw,
2858 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2864 /* SW Reset the PHY so all changes take effect */
2865 ret_val = e1000_phy_reset(hw);
2867 DEBUGOUT("Error Resetting the PHY\n");
2871 return E1000_SUCCESS;
2874 /********************************************************************
2875 * Setup auto-negotiation and flow control advertisements,
2876 * and then perform auto-negotiation.
2878 * hw - Struct containing variables accessed by shared code
2879 *********************************************************************/
2881 e1000_copper_link_autoneg(struct e1000_hw *hw)
2888 /* Perform some bounds checking on the hw->autoneg_advertised
2889 * parameter. If this variable is zero, then set it to the default.
2891 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2893 /* If autoneg_advertised is zero, we assume it was not defaulted
2894 * by the calling code so we set to advertise full capability.
2896 if (hw->autoneg_advertised == 0)
2897 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2899 /* IFE phy only supports 10/100 */
2900 if (hw->phy_type == e1000_phy_ife)
2901 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2903 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2904 ret_val = e1000_phy_setup_autoneg(hw);
2906 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2909 DEBUGOUT("Restarting Auto-Neg\n");
2911 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2912 * the Auto Neg Restart bit in the PHY control register.
2914 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2918 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2919 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2923 /* Does the user want to wait for Auto-Neg to complete here, or
2924 * check at a later time (for example, callback routine).
2926 /* If we do not wait for autonegtation to complete I
2927 * do not see a valid link status.
2928 * wait_autoneg_complete = 1 .
2930 if (hw->wait_autoneg_complete) {
2931 ret_val = e1000_wait_autoneg(hw);
2933 DEBUGOUT("Error while waiting for autoneg"
2939 hw->get_link_status = true;
2941 return E1000_SUCCESS;
2944 /******************************************************************************
2945 * Config the MAC and the PHY after link is up.
2946 * 1) Set up the MAC to the current PHY speed/duplex
2947 * if we are on 82543. If we
2948 * are on newer silicon, we only need to configure
2949 * collision distance in the Transmit Control Register.
2950 * 2) Set up flow control on the MAC to that established with
2952 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2954 * hw - Struct containing variables accessed by shared code
2955 ******************************************************************************/
2957 e1000_copper_link_postconfig(struct e1000_hw *hw)
2962 if (hw->mac_type >= e1000_82544) {
2963 e1000_config_collision_dist(hw);
2965 ret_val = e1000_config_mac_to_phy(hw);
2967 DEBUGOUT("Error configuring MAC to PHY settings\n");
2971 ret_val = e1000_config_fc_after_link_up(hw);
2973 DEBUGOUT("Error Configuring Flow Control\n");
2976 return E1000_SUCCESS;
2979 /******************************************************************************
2980 * Detects which PHY is present and setup the speed and duplex
2982 * hw - Struct containing variables accessed by shared code
2983 ******************************************************************************/
2985 e1000_setup_copper_link(struct e1000_hw *hw)
2994 switch (hw->mac_type) {
2995 case e1000_80003es2lan:
2997 /* Set the mac to wait the maximum time between each
2998 * iteration and increase the max iterations when
2999 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3000 ret_val = e1000_write_kmrn_reg(hw,
3001 GG82563_REG(0x34, 4), 0xFFFF);
3004 ret_val = e1000_read_kmrn_reg(hw,
3005 GG82563_REG(0x34, 9), ®_data);
3009 ret_val = e1000_write_kmrn_reg(hw,
3010 GG82563_REG(0x34, 9), reg_data);
3017 /* Check if it is a valid PHY and set PHY mode if necessary. */
3018 ret_val = e1000_copper_link_preconfig(hw);
3021 switch (hw->mac_type) {
3022 case e1000_80003es2lan:
3023 /* Kumeran registers are written-only */
3025 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3026 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3027 ret_val = e1000_write_kmrn_reg(hw,
3028 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3036 if (hw->phy_type == e1000_phy_igp ||
3037 hw->phy_type == e1000_phy_igp_3 ||
3038 hw->phy_type == e1000_phy_igp_2) {
3039 ret_val = e1000_copper_link_igp_setup(hw);
3042 } else if (hw->phy_type == e1000_phy_m88 ||
3043 hw->phy_type == e1000_phy_igb) {
3044 ret_val = e1000_copper_link_mgp_setup(hw);
3047 } else if (hw->phy_type == e1000_phy_gg82563) {
3048 ret_val = e1000_copper_link_ggp_setup(hw);
3054 /* Setup autoneg and flow control advertisement
3055 * and perform autonegotiation */
3056 ret_val = e1000_copper_link_autoneg(hw);
3060 /* Check link status. Wait up to 100 microseconds for link to become
3063 for (i = 0; i < 10; i++) {
3064 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3067 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3071 if (phy_data & MII_SR_LINK_STATUS) {
3072 /* Config the MAC and PHY after link is up */
3073 ret_val = e1000_copper_link_postconfig(hw);
3077 DEBUGOUT("Valid link established!!!\n");
3078 return E1000_SUCCESS;
3083 DEBUGOUT("Unable to establish link!!!\n");
3084 return E1000_SUCCESS;
3087 /******************************************************************************
3088 * Configures PHY autoneg and flow control advertisement settings
3090 * hw - Struct containing variables accessed by shared code
3091 ******************************************************************************/
3093 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3096 uint16_t mii_autoneg_adv_reg;
3097 uint16_t mii_1000t_ctrl_reg;
3101 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3102 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3106 if (hw->phy_type != e1000_phy_ife) {
3107 /* Read the MII 1000Base-T Control Register (Address 9). */
3108 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3109 &mii_1000t_ctrl_reg);
3113 mii_1000t_ctrl_reg = 0;
3115 /* Need to parse both autoneg_advertised and fc and set up
3116 * the appropriate PHY registers. First we will parse for
3117 * autoneg_advertised software override. Since we can advertise
3118 * a plethora of combinations, we need to check each bit
3122 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3123 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3124 * the 1000Base-T Control Register (Address 9).
3126 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3127 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3129 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3131 /* Do we want to advertise 10 Mb Half Duplex? */
3132 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3133 DEBUGOUT("Advertise 10mb Half duplex\n");
3134 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3137 /* Do we want to advertise 10 Mb Full Duplex? */
3138 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3139 DEBUGOUT("Advertise 10mb Full duplex\n");
3140 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3143 /* Do we want to advertise 100 Mb Half Duplex? */
3144 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3145 DEBUGOUT("Advertise 100mb Half duplex\n");
3146 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3149 /* Do we want to advertise 100 Mb Full Duplex? */
3150 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3151 DEBUGOUT("Advertise 100mb Full duplex\n");
3152 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3155 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3156 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3158 ("Advertise 1000mb Half duplex requested, request denied!\n");
3161 /* Do we want to advertise 1000 Mb Full Duplex? */
3162 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3163 DEBUGOUT("Advertise 1000mb Full duplex\n");
3164 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3167 /* Check for a software override of the flow control settings, and
3168 * setup the PHY advertisement registers accordingly. If
3169 * auto-negotiation is enabled, then software will have to set the
3170 * "PAUSE" bits to the correct value in the Auto-Negotiation
3171 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3173 * The possible values of the "fc" parameter are:
3174 * 0: Flow control is completely disabled
3175 * 1: Rx flow control is enabled (we can receive pause frames
3176 * but not send pause frames).
3177 * 2: Tx flow control is enabled (we can send pause frames
3178 * but we do not support receiving pause frames).
3179 * 3: Both Rx and TX flow control (symmetric) are enabled.
3180 * other: No software override. The flow control configuration
3181 * in the EEPROM is used.
3184 case e1000_fc_none: /* 0 */
3185 /* Flow control (RX & TX) is completely disabled by a
3186 * software over-ride.
3188 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3190 case e1000_fc_rx_pause: /* 1 */
3191 /* RX Flow control is enabled, and TX Flow control is
3192 * disabled, by a software over-ride.
3194 /* Since there really isn't a way to advertise that we are
3195 * capable of RX Pause ONLY, we will advertise that we
3196 * support both symmetric and asymmetric RX PAUSE. Later
3197 * (in e1000_config_fc_after_link_up) we will disable the
3198 *hw's ability to send PAUSE frames.
3200 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3202 case e1000_fc_tx_pause: /* 2 */
3203 /* TX Flow control is enabled, and RX Flow control is
3204 * disabled, by a software over-ride.
3206 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3207 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3209 case e1000_fc_full: /* 3 */
3210 /* Flow control (both RX and TX) is enabled by a software
3213 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3216 DEBUGOUT("Flow control param set incorrectly\n");
3217 return -E1000_ERR_CONFIG;
3220 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3224 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3226 if (hw->phy_type != e1000_phy_ife) {
3227 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3228 mii_1000t_ctrl_reg);
3233 return E1000_SUCCESS;
3236 /******************************************************************************
3237 * Sets the collision distance in the Transmit Control register
3239 * hw - Struct containing variables accessed by shared code
3241 * Link should have been established previously. Reads the speed and duplex
3242 * information from the Device Status register.
3243 ******************************************************************************/
3245 e1000_config_collision_dist(struct e1000_hw *hw)
3247 uint32_t tctl, coll_dist;
3251 if (hw->mac_type < e1000_82543)
3252 coll_dist = E1000_COLLISION_DISTANCE_82542;
3254 coll_dist = E1000_COLLISION_DISTANCE;
3256 tctl = E1000_READ_REG(hw, TCTL);
3258 tctl &= ~E1000_TCTL_COLD;
3259 tctl |= coll_dist << E1000_COLD_SHIFT;
3261 E1000_WRITE_REG(hw, TCTL, tctl);
3262 E1000_WRITE_FLUSH(hw);
3265 /******************************************************************************
3266 * Sets MAC speed and duplex settings to reflect the those in the PHY
3268 * hw - Struct containing variables accessed by shared code
3269 * mii_reg - data to write to the MII control register
3271 * The contents of the PHY register containing the needed information need to
3273 ******************************************************************************/
3275 e1000_config_mac_to_phy(struct e1000_hw *hw)
3282 /* Read the Device Control Register and set the bits to Force Speed
3285 ctrl = E1000_READ_REG(hw, CTRL);
3286 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3287 ctrl &= ~(E1000_CTRL_ILOS);
3288 ctrl |= (E1000_CTRL_SPD_SEL);
3290 /* Set up duplex in the Device Control and Transmit Control
3291 * registers depending on negotiated values.
3293 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3294 DEBUGOUT("PHY Read Error\n");
3295 return -E1000_ERR_PHY;
3297 if (phy_data & M88E1000_PSSR_DPLX)
3298 ctrl |= E1000_CTRL_FD;
3300 ctrl &= ~E1000_CTRL_FD;
3302 e1000_config_collision_dist(hw);
3304 /* Set up speed in the Device Control register depending on
3305 * negotiated values.
3307 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3308 ctrl |= E1000_CTRL_SPD_1000;
3309 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3310 ctrl |= E1000_CTRL_SPD_100;
3311 /* Write the configured values back to the Device Control Reg. */
3312 E1000_WRITE_REG(hw, CTRL, ctrl);
3316 /******************************************************************************
3317 * Forces the MAC's flow control settings.
3319 * hw - Struct containing variables accessed by shared code
3321 * Sets the TFCE and RFCE bits in the device control register to reflect
3322 * the adapter settings. TFCE and RFCE need to be explicitly set by
3323 * software when a Copper PHY is used because autonegotiation is managed
3324 * by the PHY rather than the MAC. Software must also configure these
3325 * bits when link is forced on a fiber connection.
3326 *****************************************************************************/
3328 e1000_force_mac_fc(struct e1000_hw *hw)
3334 /* Get the current configuration of the Device Control Register */
3335 ctrl = E1000_READ_REG(hw, CTRL);
3337 /* Because we didn't get link via the internal auto-negotiation
3338 * mechanism (we either forced link or we got link via PHY
3339 * auto-neg), we have to manually enable/disable transmit an
3340 * receive flow control.
3342 * The "Case" statement below enables/disable flow control
3343 * according to the "hw->fc" parameter.
3345 * The possible values of the "fc" parameter are:
3346 * 0: Flow control is completely disabled
3347 * 1: Rx flow control is enabled (we can receive pause
3348 * frames but not send pause frames).
3349 * 2: Tx flow control is enabled (we can send pause frames
3350 * frames but we do not receive pause frames).
3351 * 3: Both Rx and TX flow control (symmetric) is enabled.
3352 * other: No other values should be possible at this point.
3357 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3359 case e1000_fc_rx_pause:
3360 ctrl &= (~E1000_CTRL_TFCE);
3361 ctrl |= E1000_CTRL_RFCE;
3363 case e1000_fc_tx_pause:
3364 ctrl &= (~E1000_CTRL_RFCE);
3365 ctrl |= E1000_CTRL_TFCE;
3368 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3371 DEBUGOUT("Flow control param set incorrectly\n");
3372 return -E1000_ERR_CONFIG;
3375 /* Disable TX Flow Control for 82542 (rev 2.0) */
3376 if (hw->mac_type == e1000_82542_rev2_0)
3377 ctrl &= (~E1000_CTRL_TFCE);
3379 E1000_WRITE_REG(hw, CTRL, ctrl);
3383 /******************************************************************************
3384 * Configures flow control settings after link is established
3386 * hw - Struct containing variables accessed by shared code
3388 * Should be called immediately after a valid link has been established.
3389 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3390 * and autonegotiation is enabled, the MAC flow control settings will be set
3391 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3392 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3393 *****************************************************************************/
3395 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3398 uint16_t mii_status_reg;
3399 uint16_t mii_nway_adv_reg;
3400 uint16_t mii_nway_lp_ability_reg;
3406 /* Check for the case where we have fiber media and auto-neg failed
3407 * so we had to force link. In this case, we need to force the
3408 * configuration of the MAC to match the "fc" parameter.
3410 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3411 || ((hw->media_type == e1000_media_type_internal_serdes)
3412 && (hw->autoneg_failed))
3413 || ((hw->media_type == e1000_media_type_copper)
3414 && (!hw->autoneg))) {
3415 ret_val = e1000_force_mac_fc(hw);
3417 DEBUGOUT("Error forcing flow control settings\n");
3422 /* Check for the case where we have copper media and auto-neg is
3423 * enabled. In this case, we need to check and see if Auto-Neg
3424 * has completed, and if so, how the PHY and link partner has
3425 * flow control configured.
3427 if (hw->media_type == e1000_media_type_copper) {
3428 /* Read the MII Status Register and check to see if AutoNeg
3429 * has completed. We read this twice because this reg has
3430 * some "sticky" (latched) bits.
3432 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3433 DEBUGOUT("PHY Read Error\n");
3434 return -E1000_ERR_PHY;
3436 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3437 DEBUGOUT("PHY Read Error\n");
3438 return -E1000_ERR_PHY;
3441 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3442 /* The AutoNeg process has completed, so we now need to
3443 * read both the Auto Negotiation Advertisement Register
3444 * (Address 4) and the Auto_Negotiation Base Page Ability
3445 * Register (Address 5) to determine how flow control was
3448 if (e1000_read_phy_reg
3449 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3450 DEBUGOUT("PHY Read Error\n");
3451 return -E1000_ERR_PHY;
3453 if (e1000_read_phy_reg
3454 (hw, PHY_LP_ABILITY,
3455 &mii_nway_lp_ability_reg) < 0) {
3456 DEBUGOUT("PHY Read Error\n");
3457 return -E1000_ERR_PHY;
3460 /* Two bits in the Auto Negotiation Advertisement Register
3461 * (Address 4) and two bits in the Auto Negotiation Base
3462 * Page Ability Register (Address 5) determine flow control
3463 * for both the PHY and the link partner. The following
3464 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3465 * 1999, describes these PAUSE resolution bits and how flow
3466 * control is determined based upon these settings.
3467 * NOTE: DC = Don't Care
3469 * LOCAL DEVICE | LINK PARTNER
3470 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3471 *-------|---------|-------|---------|--------------------
3472 * 0 | 0 | DC | DC | e1000_fc_none
3473 * 0 | 1 | 0 | DC | e1000_fc_none
3474 * 0 | 1 | 1 | 0 | e1000_fc_none
3475 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3476 * 1 | 0 | 0 | DC | e1000_fc_none
3477 * 1 | DC | 1 | DC | e1000_fc_full
3478 * 1 | 1 | 0 | 0 | e1000_fc_none
3479 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3482 /* Are both PAUSE bits set to 1? If so, this implies
3483 * Symmetric Flow Control is enabled at both ends. The
3484 * ASM_DIR bits are irrelevant per the spec.
3486 * For Symmetric Flow Control:
3488 * LOCAL DEVICE | LINK PARTNER
3489 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3490 *-------|---------|-------|---------|--------------------
3491 * 1 | DC | 1 | DC | e1000_fc_full
3494 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3495 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3496 /* Now we need to check if the user selected RX ONLY
3497 * of pause frames. In this case, we had to advertise
3498 * FULL flow control because we could not advertise RX
3499 * ONLY. Hence, we must now check to see if we need to
3500 * turn OFF the TRANSMISSION of PAUSE frames.
3502 if (hw->original_fc == e1000_fc_full) {
3503 hw->fc = e1000_fc_full;
3504 DEBUGOUT("Flow Control = FULL.\r\n");
3506 hw->fc = e1000_fc_rx_pause;
3508 ("Flow Control = RX PAUSE frames only.\r\n");
3511 /* For receiving PAUSE frames ONLY.
3513 * LOCAL DEVICE | LINK PARTNER
3514 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3515 *-------|---------|-------|---------|--------------------
3516 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3519 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3520 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3521 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3522 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3524 hw->fc = e1000_fc_tx_pause;
3526 ("Flow Control = TX PAUSE frames only.\r\n");
3528 /* For transmitting PAUSE frames ONLY.
3530 * LOCAL DEVICE | LINK PARTNER
3531 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3532 *-------|---------|-------|---------|--------------------
3533 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3536 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3537 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3538 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3539 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3541 hw->fc = e1000_fc_rx_pause;
3543 ("Flow Control = RX PAUSE frames only.\r\n");
3545 /* Per the IEEE spec, at this point flow control should be
3546 * disabled. However, we want to consider that we could
3547 * be connected to a legacy switch that doesn't advertise
3548 * desired flow control, but can be forced on the link
3549 * partner. So if we advertised no flow control, that is
3550 * what we will resolve to. If we advertised some kind of
3551 * receive capability (Rx Pause Only or Full Flow Control)
3552 * and the link partner advertised none, we will configure
3553 * ourselves to enable Rx Flow Control only. We can do
3554 * this safely for two reasons: If the link partner really
3555 * didn't want flow control enabled, and we enable Rx, no
3556 * harm done since we won't be receiving any PAUSE frames
3557 * anyway. If the intent on the link partner was to have
3558 * flow control enabled, then by us enabling RX only, we
3559 * can at least receive pause frames and process them.
3560 * This is a good idea because in most cases, since we are
3561 * predominantly a server NIC, more times than not we will
3562 * be asked to delay transmission of packets than asking
3563 * our link partner to pause transmission of frames.
3565 else if (hw->original_fc == e1000_fc_none ||
3566 hw->original_fc == e1000_fc_tx_pause) {
3567 hw->fc = e1000_fc_none;
3568 DEBUGOUT("Flow Control = NONE.\r\n");
3570 hw->fc = e1000_fc_rx_pause;
3572 ("Flow Control = RX PAUSE frames only.\r\n");
3575 /* Now we need to do one last check... If we auto-
3576 * negotiated to HALF DUPLEX, flow control should not be
3577 * enabled per IEEE 802.3 spec.
3579 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3581 if (duplex == HALF_DUPLEX)
3582 hw->fc = e1000_fc_none;
3584 /* Now we call a subroutine to actually force the MAC
3585 * controller to use the correct flow control settings.
3587 ret_val = e1000_force_mac_fc(hw);
3590 ("Error forcing flow control settings\n");
3595 ("Copper PHY and Auto Neg has not completed.\r\n");
3598 return E1000_SUCCESS;
3601 /******************************************************************************
3602 * Checks to see if the link status of the hardware has changed.
3604 * hw - Struct containing variables accessed by shared code
3606 * Called by any function that needs to check the link status of the adapter.
3607 *****************************************************************************/
3609 e1000_check_for_link(struct e1000_hw *hw)
3618 uint16_t lp_capability;
3622 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3623 * set when the optics detect a signal. On older adapters, it will be
3624 * cleared when there is a signal
3626 ctrl = E1000_READ_REG(hw, CTRL);
3627 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3628 signal = E1000_CTRL_SWDPIN1;
3632 status = E1000_READ_REG(hw, STATUS);
3633 rxcw = E1000_READ_REG(hw, RXCW);
3634 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3636 /* If we have a copper PHY then we only want to go out to the PHY
3637 * registers to see if Auto-Neg has completed and/or if our link
3638 * status has changed. The get_link_status flag will be set if we
3639 * receive a Link Status Change interrupt or we have Rx Sequence
3642 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3643 /* First we want to see if the MII Status Register reports
3644 * link. If so, then we want to get the current speed/duplex
3646 * Read the register twice since the link bit is sticky.
3648 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3649 DEBUGOUT("PHY Read Error\n");
3650 return -E1000_ERR_PHY;
3652 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3653 DEBUGOUT("PHY Read Error\n");
3654 return -E1000_ERR_PHY;
3657 if (phy_data & MII_SR_LINK_STATUS) {
3658 hw->get_link_status = false;
3660 /* No link detected */
3661 return -E1000_ERR_NOLINK;
3664 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3665 * have Si on board that is 82544 or newer, Auto
3666 * Speed Detection takes care of MAC speed/duplex
3667 * configuration. So we only need to configure Collision
3668 * Distance in the MAC. Otherwise, we need to force
3669 * speed/duplex on the MAC to the current PHY speed/duplex
3672 if (hw->mac_type >= e1000_82544)
3673 e1000_config_collision_dist(hw);
3675 ret_val = e1000_config_mac_to_phy(hw);
3678 ("Error configuring MAC to PHY settings\n");
3683 /* Configure Flow Control now that Auto-Neg has completed. First, we
3684 * need to restore the desired flow control settings because we may
3685 * have had to re-autoneg with a different link partner.
3687 ret_val = e1000_config_fc_after_link_up(hw);
3689 DEBUGOUT("Error configuring flow control\n");
3693 /* At this point we know that we are on copper and we have
3694 * auto-negotiated link. These are conditions for checking the link
3695 * parter capability register. We use the link partner capability to
3696 * determine if TBI Compatibility needs to be turned on or off. If
3697 * the link partner advertises any speed in addition to Gigabit, then
3698 * we assume that they are GMII-based, and TBI compatibility is not
3699 * needed. If no other speeds are advertised, we assume the link
3700 * partner is TBI-based, and we turn on TBI Compatibility.
3702 if (hw->tbi_compatibility_en) {
3703 if (e1000_read_phy_reg
3704 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3705 DEBUGOUT("PHY Read Error\n");
3706 return -E1000_ERR_PHY;
3708 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3709 NWAY_LPAR_10T_FD_CAPS |
3710 NWAY_LPAR_100TX_HD_CAPS |
3711 NWAY_LPAR_100TX_FD_CAPS |
3712 NWAY_LPAR_100T4_CAPS)) {
3713 /* If our link partner advertises anything in addition to
3714 * gigabit, we do not need to enable TBI compatibility.
3716 if (hw->tbi_compatibility_on) {
3717 /* If we previously were in the mode, turn it off. */
3718 rctl = E1000_READ_REG(hw, RCTL);
3719 rctl &= ~E1000_RCTL_SBP;
3720 E1000_WRITE_REG(hw, RCTL, rctl);
3721 hw->tbi_compatibility_on = false;
3724 /* If TBI compatibility is was previously off, turn it on. For
3725 * compatibility with a TBI link partner, we will store bad
3726 * packets. Some frames have an additional byte on the end and
3727 * will look like CRC errors to to the hardware.
3729 if (!hw->tbi_compatibility_on) {
3730 hw->tbi_compatibility_on = true;
3731 rctl = E1000_READ_REG(hw, RCTL);
3732 rctl |= E1000_RCTL_SBP;
3733 E1000_WRITE_REG(hw, RCTL, rctl);
3738 /* If we don't have link (auto-negotiation failed or link partner cannot
3739 * auto-negotiate), the cable is plugged in (we have signal), and our
3740 * link partner is not trying to auto-negotiate with us (we are receiving
3741 * idles or data), we need to force link up. We also need to give
3742 * auto-negotiation time to complete, in case the cable was just plugged
3743 * in. The autoneg_failed flag does this.
3745 else if ((hw->media_type == e1000_media_type_fiber) &&
3746 (!(status & E1000_STATUS_LU)) &&
3747 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3748 (!(rxcw & E1000_RXCW_C))) {
3749 if (hw->autoneg_failed == 0) {
3750 hw->autoneg_failed = 1;
3753 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3755 /* Disable auto-negotiation in the TXCW register */
3756 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3758 /* Force link-up and also force full-duplex. */
3759 ctrl = E1000_READ_REG(hw, CTRL);
3760 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3761 E1000_WRITE_REG(hw, CTRL, ctrl);
3763 /* Configure Flow Control after forcing link up. */
3764 ret_val = e1000_config_fc_after_link_up(hw);
3766 DEBUGOUT("Error configuring flow control\n");
3770 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3771 * auto-negotiation in the TXCW register and disable forced link in the
3772 * Device Control register in an attempt to auto-negotiate with our link
3775 else if ((hw->media_type == e1000_media_type_fiber) &&
3776 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3778 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3779 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3780 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3785 /******************************************************************************
3786 * Configure the MAC-to-PHY interface for 10/100Mbps
3788 * hw - Struct containing variables accessed by shared code
3789 ******************************************************************************/
3791 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3793 int32_t ret_val = E1000_SUCCESS;
3799 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3800 ret_val = e1000_write_kmrn_reg(hw,
3801 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3805 /* Configure Transmit Inter-Packet Gap */
3806 tipg = E1000_READ_REG(hw, TIPG);
3807 tipg &= ~E1000_TIPG_IPGT_MASK;
3808 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3809 E1000_WRITE_REG(hw, TIPG, tipg);
3811 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3816 if (duplex == HALF_DUPLEX)
3817 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3819 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3821 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3827 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3829 int32_t ret_val = E1000_SUCCESS;
3835 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3836 ret_val = e1000_write_kmrn_reg(hw,
3837 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3841 /* Configure Transmit Inter-Packet Gap */
3842 tipg = E1000_READ_REG(hw, TIPG);
3843 tipg &= ~E1000_TIPG_IPGT_MASK;
3844 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3845 E1000_WRITE_REG(hw, TIPG, tipg);
3847 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3852 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3853 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3858 /******************************************************************************
3859 * Detects the current speed and duplex settings of the hardware.
3861 * hw - Struct containing variables accessed by shared code
3862 * speed - Speed of the connection
3863 * duplex - Duplex setting of the connection
3864 *****************************************************************************/
3866 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3875 if (hw->mac_type >= e1000_82543) {
3876 status = E1000_READ_REG(hw, STATUS);
3877 if (status & E1000_STATUS_SPEED_1000) {
3878 *speed = SPEED_1000;
3879 DEBUGOUT("1000 Mbs, ");
3880 } else if (status & E1000_STATUS_SPEED_100) {
3882 DEBUGOUT("100 Mbs, ");
3885 DEBUGOUT("10 Mbs, ");
3888 if (status & E1000_STATUS_FD) {
3889 *duplex = FULL_DUPLEX;
3890 DEBUGOUT("Full Duplex\r\n");
3892 *duplex = HALF_DUPLEX;
3893 DEBUGOUT(" Half Duplex\r\n");
3896 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3897 *speed = SPEED_1000;
3898 *duplex = FULL_DUPLEX;
3901 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3902 * even if it is operating at half duplex. Here we set the duplex
3903 * settings to match the duplex in the link partner's capabilities.
3905 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3906 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3910 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3911 *duplex = HALF_DUPLEX;
3913 ret_val = e1000_read_phy_reg(hw,
3914 PHY_LP_ABILITY, &phy_data);
3917 if ((*speed == SPEED_100 &&
3918 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3919 || (*speed == SPEED_10
3920 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3921 *duplex = HALF_DUPLEX;
3925 if ((hw->mac_type == e1000_80003es2lan) &&
3926 (hw->media_type == e1000_media_type_copper)) {
3927 if (*speed == SPEED_1000)
3928 ret_val = e1000_configure_kmrn_for_1000(hw);
3930 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3934 return E1000_SUCCESS;
3937 /******************************************************************************
3938 * Blocks until autoneg completes or times out (~4.5 seconds)
3940 * hw - Struct containing variables accessed by shared code
3941 ******************************************************************************/
3943 e1000_wait_autoneg(struct e1000_hw *hw)
3949 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3951 /* We will wait for autoneg to complete or timeout to expire. */
3952 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3953 /* Read the MII Status Register and wait for Auto-Neg
3954 * Complete bit to be set.
3956 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3957 DEBUGOUT("PHY Read Error\n");
3958 return -E1000_ERR_PHY;
3960 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3961 DEBUGOUT("PHY Read Error\n");
3962 return -E1000_ERR_PHY;
3964 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3965 DEBUGOUT("Auto-Neg complete.\n");
3970 DEBUGOUT("Auto-Neg timedout.\n");
3971 return -E1000_ERR_TIMEOUT;
3974 /******************************************************************************
3975 * Raises the Management Data Clock
3977 * hw - Struct containing variables accessed by shared code
3978 * ctrl - Device control register's current value
3979 ******************************************************************************/
3981 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3983 /* Raise the clock input to the Management Data Clock (by setting the MDC
3984 * bit), and then delay 2 microseconds.
3986 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3987 E1000_WRITE_FLUSH(hw);
3991 /******************************************************************************
3992 * Lowers the Management Data Clock
3994 * hw - Struct containing variables accessed by shared code
3995 * ctrl - Device control register's current value
3996 ******************************************************************************/
3998 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4000 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4001 * bit), and then delay 2 microseconds.
4003 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4004 E1000_WRITE_FLUSH(hw);
4008 /******************************************************************************
4009 * Shifts data bits out to the PHY
4011 * hw - Struct containing variables accessed by shared code
4012 * data - Data to send out to the PHY
4013 * count - Number of bits to shift out
4015 * Bits are shifted out in MSB to LSB order.
4016 ******************************************************************************/
4018 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4023 /* We need to shift "count" number of bits out to the PHY. So, the value
4024 * in the "data" parameter will be shifted out to the PHY one bit at a
4025 * time. In order to do this, "data" must be broken down into bits.
4028 mask <<= (count - 1);
4030 ctrl = E1000_READ_REG(hw, CTRL);
4032 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4033 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4036 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4037 * then raising and lowering the Management Data Clock. A "0" is
4038 * shifted out to the PHY by setting the MDIO bit to "0" and then
4039 * raising and lowering the clock.
4042 ctrl |= E1000_CTRL_MDIO;
4044 ctrl &= ~E1000_CTRL_MDIO;
4046 E1000_WRITE_REG(hw, CTRL, ctrl);
4047 E1000_WRITE_FLUSH(hw);
4051 e1000_raise_mdi_clk(hw, &ctrl);
4052 e1000_lower_mdi_clk(hw, &ctrl);
4058 /******************************************************************************
4059 * Shifts data bits in from the PHY
4061 * hw - Struct containing variables accessed by shared code
4063 * Bits are shifted in in MSB to LSB order.
4064 ******************************************************************************/
4066 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4072 /* In order to read a register from the PHY, we need to shift in a total
4073 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4074 * to avoid contention on the MDIO pin when a read operation is performed.
4075 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4076 * by raising the input to the Management Data Clock (setting the MDC bit),
4077 * and then reading the value of the MDIO bit.
4079 ctrl = E1000_READ_REG(hw, CTRL);
4081 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4082 ctrl &= ~E1000_CTRL_MDIO_DIR;
4083 ctrl &= ~E1000_CTRL_MDIO;
4085 E1000_WRITE_REG(hw, CTRL, ctrl);
4086 E1000_WRITE_FLUSH(hw);
4088 /* Raise and Lower the clock before reading in the data. This accounts for
4089 * the turnaround bits. The first clock occurred when we clocked out the
4090 * last bit of the Register Address.
4092 e1000_raise_mdi_clk(hw, &ctrl);
4093 e1000_lower_mdi_clk(hw, &ctrl);
4095 for (data = 0, i = 0; i < 16; i++) {
4097 e1000_raise_mdi_clk(hw, &ctrl);
4098 ctrl = E1000_READ_REG(hw, CTRL);
4099 /* Check to see if we shifted in a "1". */
4100 if (ctrl & E1000_CTRL_MDIO)
4102 e1000_lower_mdi_clk(hw, &ctrl);
4105 e1000_raise_mdi_clk(hw, &ctrl);
4106 e1000_lower_mdi_clk(hw, &ctrl);
4111 /*****************************************************************************
4112 * Reads the value from a PHY register
4114 * hw - Struct containing variables accessed by shared code
4115 * reg_addr - address of the PHY register to read
4116 ******************************************************************************/
4118 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4122 const uint32_t phy_addr = 1;
4124 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4125 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4126 return -E1000_ERR_PARAM;
4129 if (hw->mac_type > e1000_82543) {
4130 /* Set up Op-code, Phy Address, and register address in the MDI
4131 * Control register. The MAC will take care of interfacing with the
4132 * PHY to retrieve the desired data.
4134 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4135 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4136 (E1000_MDIC_OP_READ));
4138 E1000_WRITE_REG(hw, MDIC, mdic);
4140 /* Poll the ready bit to see if the MDI read completed */
4141 for (i = 0; i < 64; i++) {
4143 mdic = E1000_READ_REG(hw, MDIC);
4144 if (mdic & E1000_MDIC_READY)
4147 if (!(mdic & E1000_MDIC_READY)) {
4148 DEBUGOUT("MDI Read did not complete\n");
4149 return -E1000_ERR_PHY;
4151 if (mdic & E1000_MDIC_ERROR) {
4152 DEBUGOUT("MDI Error\n");
4153 return -E1000_ERR_PHY;
4155 *phy_data = (uint16_t) mdic;
4157 /* We must first send a preamble through the MDIO pin to signal the
4158 * beginning of an MII instruction. This is done by sending 32
4159 * consecutive "1" bits.
4161 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4163 /* Now combine the next few fields that are required for a read
4164 * operation. We use this method instead of calling the
4165 * e1000_shift_out_mdi_bits routine five different times. The format of
4166 * a MII read instruction consists of a shift out of 14 bits and is
4167 * defined as follows:
4168 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4169 * followed by a shift in of 18 bits. This first two bits shifted in
4170 * are TurnAround bits used to avoid contention on the MDIO pin when a
4171 * READ operation is performed. These two bits are thrown away
4172 * followed by a shift in of 16 bits which contains the desired data.
4174 mdic = ((reg_addr) | (phy_addr << 5) |
4175 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4177 e1000_shift_out_mdi_bits(hw, mdic, 14);
4179 /* Now that we've shifted out the read command to the MII, we need to
4180 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4183 *phy_data = e1000_shift_in_mdi_bits(hw);
4188 /******************************************************************************
4189 * Writes a value to a PHY register
4191 * hw - Struct containing variables accessed by shared code
4192 * reg_addr - address of the PHY register to write
4193 * data - data to write to the PHY
4194 ******************************************************************************/
4196 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4200 const uint32_t phy_addr = 1;
4202 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4203 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4204 return -E1000_ERR_PARAM;
4207 if (hw->mac_type > e1000_82543) {
4208 /* Set up Op-code, Phy Address, register address, and data intended
4209 * for the PHY register in the MDI Control register. The MAC will take
4210 * care of interfacing with the PHY to send the desired data.
4212 mdic = (((uint32_t) phy_data) |
4213 (reg_addr << E1000_MDIC_REG_SHIFT) |
4214 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4215 (E1000_MDIC_OP_WRITE));
4217 E1000_WRITE_REG(hw, MDIC, mdic);
4219 /* Poll the ready bit to see if the MDI read completed */
4220 for (i = 0; i < 64; i++) {
4222 mdic = E1000_READ_REG(hw, MDIC);
4223 if (mdic & E1000_MDIC_READY)
4226 if (!(mdic & E1000_MDIC_READY)) {
4227 DEBUGOUT("MDI Write did not complete\n");
4228 return -E1000_ERR_PHY;
4231 /* We'll need to use the SW defined pins to shift the write command
4232 * out to the PHY. We first send a preamble to the PHY to signal the
4233 * beginning of the MII instruction. This is done by sending 32
4234 * consecutive "1" bits.
4236 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4238 /* Now combine the remaining required fields that will indicate a
4239 * write operation. We use this method instead of calling the
4240 * e1000_shift_out_mdi_bits routine for each field in the command. The
4241 * format of a MII write instruction is as follows:
4242 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4244 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4245 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4247 mdic |= (uint32_t) phy_data;
4249 e1000_shift_out_mdi_bits(hw, mdic, 32);
4254 /******************************************************************************
4255 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4256 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4257 * the caller to figure out how to deal with it.
4259 * hw - Struct containing variables accessed by shared code
4261 * returns: - E1000_BLK_PHY_RESET
4264 *****************************************************************************/
4266 e1000_check_phy_reset_block(struct e1000_hw *hw)
4271 if (hw->mac_type == e1000_ich8lan) {
4272 fwsm = E1000_READ_REG(hw, FWSM);
4273 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4274 : E1000_BLK_PHY_RESET;
4277 if (hw->mac_type > e1000_82547_rev_2)
4278 manc = E1000_READ_REG(hw, MANC);
4279 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4280 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4283 /***************************************************************************
4284 * Checks if the PHY configuration is done
4286 * hw: Struct containing variables accessed by shared code
4288 * returns: - E1000_ERR_RESET if fail to reset MAC
4289 * E1000_SUCCESS at any other case.
4291 ***************************************************************************/
4293 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4295 int32_t timeout = PHY_CFG_TIMEOUT;
4296 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4300 switch (hw->mac_type) {
4305 case e1000_80003es2lan:
4306 /* Separate *_CFG_DONE_* bit for each port */
4307 if (e1000_is_second_port(hw))
4308 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4315 if (hw->mac_type == e1000_igb) {
4316 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4319 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4326 DEBUGOUT("MNG configuration cycle has not "
4328 return -E1000_ERR_RESET;
4333 return E1000_SUCCESS;
4336 /******************************************************************************
4337 * Returns the PHY to the power-on reset state
4339 * hw - Struct containing variables accessed by shared code
4340 ******************************************************************************/
4342 e1000_phy_hw_reset(struct e1000_hw *hw)
4344 uint16_t swfw = E1000_SWFW_PHY0_SM;
4345 uint32_t ctrl, ctrl_ext;
4351 /* In the case of the phy reset being blocked, it's not an error, we
4352 * simply return success without performing the reset. */
4353 ret_val = e1000_check_phy_reset_block(hw);
4355 return E1000_SUCCESS;
4357 DEBUGOUT("Resetting Phy...\n");
4359 if (hw->mac_type > e1000_82543) {
4360 if (e1000_is_second_port(hw))
4361 swfw = E1000_SWFW_PHY1_SM;
4363 if (e1000_swfw_sync_acquire(hw, swfw)) {
4364 DEBUGOUT("Unable to acquire swfw sync\n");
4365 return -E1000_ERR_SWFW_SYNC;
4368 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4369 * bit. Then, take it out of reset.
4371 ctrl = E1000_READ_REG(hw, CTRL);
4372 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4373 E1000_WRITE_FLUSH(hw);
4375 if (hw->mac_type < e1000_82571)
4380 E1000_WRITE_REG(hw, CTRL, ctrl);
4381 E1000_WRITE_FLUSH(hw);
4383 if (hw->mac_type >= e1000_82571)
4387 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4388 * bit to put the PHY into reset. Then, take it out of reset.
4390 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4391 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4392 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4393 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4394 E1000_WRITE_FLUSH(hw);
4396 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4397 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4398 E1000_WRITE_FLUSH(hw);
4402 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4403 /* Configure activity LED after PHY reset */
4404 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4405 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4406 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4407 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4410 e1000_swfw_sync_release(hw, swfw);
4412 /* Wait for FW to finish PHY configuration. */
4413 ret_val = e1000_get_phy_cfg_done(hw);
4414 if (ret_val != E1000_SUCCESS)
4420 /******************************************************************************
4421 * IGP phy init script - initializes the GbE PHY
4423 * hw - Struct containing variables accessed by shared code
4424 *****************************************************************************/
4426 e1000_phy_init_script(struct e1000_hw *hw)
4429 uint16_t phy_saved_data;
4432 if (hw->phy_init_script) {
4435 /* Save off the current value of register 0x2F5B to be
4436 * restored at the end of this routine. */
4437 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4439 /* Disabled the PHY transmitter */
4440 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4444 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4448 switch (hw->mac_type) {
4451 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4453 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4455 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4457 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4459 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4461 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4463 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4465 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4467 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4470 case e1000_82541_rev_2:
4471 case e1000_82547_rev_2:
4472 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4478 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4482 /* Now enable the transmitter */
4484 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4486 if (hw->mac_type == e1000_82547) {
4487 uint16_t fused, fine, coarse;
4489 /* Move to analog registers page */
4490 e1000_read_phy_reg(hw,
4491 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4493 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4494 e1000_read_phy_reg(hw,
4495 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4497 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4499 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4502 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4504 IGP01E1000_ANALOG_FUSE_COARSE_10;
4505 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4507 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4508 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4511 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4513 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4515 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4517 e1000_write_phy_reg(hw,
4518 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4519 e1000_write_phy_reg(hw,
4520 IGP01E1000_ANALOG_FUSE_BYPASS,
4521 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4527 /******************************************************************************
4530 * hw - Struct containing variables accessed by shared code
4532 * Sets bit 15 of the MII Control register
4533 ******************************************************************************/
4535 e1000_phy_reset(struct e1000_hw *hw)
4542 /* In the case of the phy reset being blocked, it's not an error, we
4543 * simply return success without performing the reset. */
4544 ret_val = e1000_check_phy_reset_block(hw);
4546 return E1000_SUCCESS;
4548 switch (hw->phy_type) {
4550 case e1000_phy_igp_2:
4551 case e1000_phy_igp_3:
4554 ret_val = e1000_phy_hw_reset(hw);
4559 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4563 phy_data |= MII_CR_RESET;
4564 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4572 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4573 e1000_phy_init_script(hw);
4575 return E1000_SUCCESS;
4578 static int e1000_set_phy_type (struct e1000_hw *hw)
4582 if (hw->mac_type == e1000_undefined)
4583 return -E1000_ERR_PHY_TYPE;
4585 switch (hw->phy_id) {
4586 case M88E1000_E_PHY_ID:
4587 case M88E1000_I_PHY_ID:
4588 case M88E1011_I_PHY_ID:
4589 case M88E1111_I_PHY_ID:
4590 hw->phy_type = e1000_phy_m88;
4592 case IGP01E1000_I_PHY_ID:
4593 if (hw->mac_type == e1000_82541 ||
4594 hw->mac_type == e1000_82541_rev_2 ||
4595 hw->mac_type == e1000_82547 ||
4596 hw->mac_type == e1000_82547_rev_2) {
4597 hw->phy_type = e1000_phy_igp;
4600 case IGP03E1000_E_PHY_ID:
4601 hw->phy_type = e1000_phy_igp_3;
4604 case IFE_PLUS_E_PHY_ID:
4605 case IFE_C_E_PHY_ID:
4606 hw->phy_type = e1000_phy_ife;
4608 case GG82563_E_PHY_ID:
4609 if (hw->mac_type == e1000_80003es2lan) {
4610 hw->phy_type = e1000_phy_gg82563;
4613 case BME1000_E_PHY_ID:
4614 hw->phy_type = e1000_phy_bm;
4617 hw->phy_type = e1000_phy_igb;
4621 /* Should never have loaded on this device */
4622 hw->phy_type = e1000_phy_undefined;
4623 return -E1000_ERR_PHY_TYPE;
4626 return E1000_SUCCESS;
4629 /******************************************************************************
4630 * Probes the expected PHY address for known PHY IDs
4632 * hw - Struct containing variables accessed by shared code
4633 ******************************************************************************/
4635 e1000_detect_gig_phy(struct e1000_hw *hw)
4637 int32_t phy_init_status, ret_val;
4638 uint16_t phy_id_high, phy_id_low;
4643 /* The 82571 firmware may still be configuring the PHY. In this
4644 * case, we cannot access the PHY until the configuration is done. So
4645 * we explicitly set the PHY values. */
4646 if (hw->mac_type == e1000_82571 ||
4647 hw->mac_type == e1000_82572) {
4648 hw->phy_id = IGP01E1000_I_PHY_ID;
4649 hw->phy_type = e1000_phy_igp_2;
4650 return E1000_SUCCESS;
4653 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4654 * work- around that forces PHY page 0 to be set or the reads fail.
4655 * The rest of the code in this routine uses e1000_read_phy_reg to
4656 * read the PHY ID. So for ESB-2 we need to have this set so our
4657 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4658 * the routines below will figure this out as well. */
4659 if (hw->mac_type == e1000_80003es2lan)
4660 hw->phy_type = e1000_phy_gg82563;
4662 /* Read the PHY ID Registers to identify which PHY is onboard. */
4663 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4667 hw->phy_id = (uint32_t) (phy_id_high << 16);
4669 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4673 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4674 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4676 switch (hw->mac_type) {
4678 if (hw->phy_id == M88E1000_E_PHY_ID)
4682 if (hw->phy_id == M88E1000_I_PHY_ID)
4687 case e1000_82545_rev_3:
4689 case e1000_82546_rev_3:
4690 if (hw->phy_id == M88E1011_I_PHY_ID)
4694 case e1000_82541_rev_2:
4696 case e1000_82547_rev_2:
4697 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4702 if (hw->phy_id == M88E1111_I_PHY_ID)
4706 if (hw->phy_id == BME1000_E_PHY_ID)
4709 case e1000_80003es2lan:
4710 if (hw->phy_id == GG82563_E_PHY_ID)
4714 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4716 if (hw->phy_id == IFE_E_PHY_ID)
4718 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4720 if (hw->phy_id == IFE_C_E_PHY_ID)
4724 if (hw->phy_id == I210_I_PHY_ID)
4728 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4729 return -E1000_ERR_CONFIG;
4732 phy_init_status = e1000_set_phy_type(hw);
4734 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4735 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4738 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4739 return -E1000_ERR_PHY;
4742 /*****************************************************************************
4743 * Set media type and TBI compatibility.
4745 * hw - Struct containing variables accessed by shared code
4746 * **************************************************************************/
4748 e1000_set_media_type(struct e1000_hw *hw)
4754 if (hw->mac_type != e1000_82543) {
4755 /* tbi_compatibility is only valid on 82543 */
4756 hw->tbi_compatibility_en = false;
4759 switch (hw->device_id) {
4760 case E1000_DEV_ID_82545GM_SERDES:
4761 case E1000_DEV_ID_82546GB_SERDES:
4762 case E1000_DEV_ID_82571EB_SERDES:
4763 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4764 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4765 case E1000_DEV_ID_82572EI_SERDES:
4766 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4767 hw->media_type = e1000_media_type_internal_serdes;
4770 switch (hw->mac_type) {
4771 case e1000_82542_rev2_0:
4772 case e1000_82542_rev2_1:
4773 hw->media_type = e1000_media_type_fiber;
4779 /* The STATUS_TBIMODE bit is reserved or reused
4780 * for the this device.
4782 hw->media_type = e1000_media_type_copper;
4785 status = E1000_READ_REG(hw, STATUS);
4786 if (status & E1000_STATUS_TBIMODE) {
4787 hw->media_type = e1000_media_type_fiber;
4788 /* tbi_compatibility not valid on fiber */
4789 hw->tbi_compatibility_en = false;
4791 hw->media_type = e1000_media_type_copper;
4799 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4801 * e1000_sw_init initializes the Adapter private data structure.
4802 * Fields are initialized based on PCI device information and
4803 * OS network device settings (MTU size).
4807 e1000_sw_init(struct e1000_hw *hw)
4811 /* PCI config space info */
4812 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4813 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4814 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4815 &hw->subsystem_vendor_id);
4816 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4818 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4819 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4821 /* identify the MAC */
4822 result = e1000_set_mac_type(hw);
4824 E1000_ERR(hw, "Unknown MAC Type\n");
4828 switch (hw->mac_type) {
4833 case e1000_82541_rev_2:
4834 case e1000_82547_rev_2:
4835 hw->phy_init_script = 1;
4839 /* flow control settings */
4840 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4841 hw->fc_low_water = E1000_FC_LOW_THRESH;
4842 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4843 hw->fc_send_xon = 1;
4845 /* Media type - copper or fiber */
4846 hw->tbi_compatibility_en = true;
4847 e1000_set_media_type(hw);
4849 if (hw->mac_type >= e1000_82543) {
4850 uint32_t status = E1000_READ_REG(hw, STATUS);
4852 if (status & E1000_STATUS_TBIMODE) {
4853 DEBUGOUT("fiber interface\n");
4854 hw->media_type = e1000_media_type_fiber;
4856 DEBUGOUT("copper interface\n");
4857 hw->media_type = e1000_media_type_copper;
4860 hw->media_type = e1000_media_type_fiber;
4863 hw->wait_autoneg_complete = true;
4864 if (hw->mac_type < e1000_82543)
4865 hw->report_tx_early = 0;
4867 hw->report_tx_early = 1;
4869 return E1000_SUCCESS;
4873 fill_rx(struct e1000_hw *hw)
4875 struct e1000_rx_desc *rd;
4876 unsigned long flush_start, flush_end;
4879 rd = rx_base + rx_tail;
4880 rx_tail = (rx_tail + 1) % 8;
4882 rd->buffer_addr = cpu_to_le64((unsigned long)packet);
4885 * Make sure there are no stale data in WB over this area, which
4886 * might get written into the memory while the e1000 also writes
4887 * into the same memory area.
4889 invalidate_dcache_range((unsigned long)packet,
4890 (unsigned long)packet + 4096);
4891 /* Dump the DMA descriptor into RAM. */
4892 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
4893 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4894 flush_dcache_range(flush_start, flush_end);
4896 E1000_WRITE_REG(hw, RDT, rx_tail);
4900 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4901 * @adapter: board private structure
4903 * Configure the Tx unit of the MAC after a reset.
4907 e1000_configure_tx(struct e1000_hw *hw)
4910 unsigned long tipg, tarc;
4911 uint32_t ipgr1, ipgr2;
4913 E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
4914 E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
4916 E1000_WRITE_REG(hw, TDLEN, 128);
4918 /* Setup the HW Tx Head and Tail descriptor pointers */
4919 E1000_WRITE_REG(hw, TDH, 0);
4920 E1000_WRITE_REG(hw, TDT, 0);
4923 /* Set the default values for the Tx Inter Packet Gap timer */
4924 if (hw->mac_type <= e1000_82547_rev_2 &&
4925 (hw->media_type == e1000_media_type_fiber ||
4926 hw->media_type == e1000_media_type_internal_serdes))
4927 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4929 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4931 /* Set the default values for the Tx Inter Packet Gap timer */
4932 switch (hw->mac_type) {
4933 case e1000_82542_rev2_0:
4934 case e1000_82542_rev2_1:
4935 tipg = DEFAULT_82542_TIPG_IPGT;
4936 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4937 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4939 case e1000_80003es2lan:
4940 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4941 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4944 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4945 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4948 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4949 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4950 E1000_WRITE_REG(hw, TIPG, tipg);
4951 /* Program the Transmit Control Register */
4952 tctl = E1000_READ_REG(hw, TCTL);
4953 tctl &= ~E1000_TCTL_CT;
4954 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4955 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4957 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4958 tarc = E1000_READ_REG(hw, TARC0);
4959 /* set the speed mode bit, we'll clear it if we're not at
4960 * gigabit link later */
4961 /* git bit can be set to 1*/
4962 } else if (hw->mac_type == e1000_80003es2lan) {
4963 tarc = E1000_READ_REG(hw, TARC0);
4965 E1000_WRITE_REG(hw, TARC0, tarc);
4966 tarc = E1000_READ_REG(hw, TARC1);
4968 E1000_WRITE_REG(hw, TARC1, tarc);
4972 e1000_config_collision_dist(hw);
4973 /* Setup Transmit Descriptor Settings for eop descriptor */
4974 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
4976 /* Need to set up RS bit */
4977 if (hw->mac_type < e1000_82543)
4978 hw->txd_cmd |= E1000_TXD_CMD_RPS;
4980 hw->txd_cmd |= E1000_TXD_CMD_RS;
4983 if (hw->mac_type == e1000_igb) {
4984 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
4986 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
4987 reg_txdctl |= 1 << 25;
4988 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
4994 E1000_WRITE_REG(hw, TCTL, tctl);
5000 * e1000_setup_rctl - configure the receive control register
5001 * @adapter: Board private structure
5004 e1000_setup_rctl(struct e1000_hw *hw)
5008 rctl = E1000_READ_REG(hw, RCTL);
5010 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5012 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5013 | E1000_RCTL_RDMTS_HALF; /* |
5014 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5016 if (hw->tbi_compatibility_on == 1)
5017 rctl |= E1000_RCTL_SBP;
5019 rctl &= ~E1000_RCTL_SBP;
5021 rctl &= ~(E1000_RCTL_SZ_4096);
5022 rctl |= E1000_RCTL_SZ_2048;
5023 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5024 E1000_WRITE_REG(hw, RCTL, rctl);
5028 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5029 * @adapter: board private structure
5031 * Configure the Rx unit of the MAC after a reset.
5034 e1000_configure_rx(struct e1000_hw *hw)
5036 unsigned long rctl, ctrl_ext;
5039 /* make sure receives are disabled while setting up the descriptors */
5040 rctl = E1000_READ_REG(hw, RCTL);
5041 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5042 if (hw->mac_type >= e1000_82540) {
5043 /* Set the interrupt throttling rate. Value is calculated
5044 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5045 #define MAX_INTS_PER_SEC 8000
5046 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
5047 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5050 if (hw->mac_type >= e1000_82571) {
5051 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5052 /* Reset delay timers after every interrupt */
5053 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5054 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5055 E1000_WRITE_FLUSH(hw);
5057 /* Setup the Base and Length of the Rx Descriptor Ring */
5058 E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
5059 E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
5061 E1000_WRITE_REG(hw, RDLEN, 128);
5063 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5064 E1000_WRITE_REG(hw, RDH, 0);
5065 E1000_WRITE_REG(hw, RDT, 0);
5066 /* Enable Receives */
5068 if (hw->mac_type == e1000_igb) {
5070 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5071 reg_rxdctl |= 1 << 25;
5072 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5076 E1000_WRITE_REG(hw, RCTL, rctl);
5081 /**************************************************************************
5082 POLL - Wait for a frame
5083 ***************************************************************************/
5085 _e1000_poll(struct e1000_hw *hw)
5087 struct e1000_rx_desc *rd;
5088 unsigned long inval_start, inval_end;
5091 /* return true if there's an ethernet packet ready to read */
5092 rd = rx_base + rx_last;
5094 /* Re-load the descriptor from RAM. */
5095 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5096 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5097 invalidate_dcache_range(inval_start, inval_end);
5099 if (!(rd->status & E1000_RXD_STAT_DD))
5101 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5102 /* Packet received, make sure the data are re-loaded from RAM. */
5103 len = le16_to_cpu(rd->length);
5104 invalidate_dcache_range((unsigned long)packet,
5105 (unsigned long)packet +
5106 roundup(len, ARCH_DMA_MINALIGN));
5110 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
5112 void *nv_packet = (void *)txpacket;
5113 struct e1000_tx_desc *txp;
5115 unsigned long flush_start, flush_end;
5117 txp = tx_base + tx_tail;
5118 tx_tail = (tx_tail + 1) % 8;
5120 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5121 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5122 txp->upper.data = 0;
5124 /* Dump the packet into RAM so e1000 can pick them. */
5125 flush_dcache_range((unsigned long)nv_packet,
5126 (unsigned long)nv_packet +
5127 roundup(length, ARCH_DMA_MINALIGN));
5128 /* Dump the descriptor into RAM as well. */
5129 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5130 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5131 flush_dcache_range(flush_start, flush_end);
5133 E1000_WRITE_REG(hw, TDT, tx_tail);
5135 E1000_WRITE_FLUSH(hw);
5137 invalidate_dcache_range(flush_start, flush_end);
5138 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5140 if (i++ > TOUT_LOOP) {
5141 DEBUGOUT("e1000: tx timeout\n");
5144 udelay(10); /* give the nic a chance to write to the register */
5150 _e1000_disable(struct e1000_hw *hw)
5152 /* Turn off the ethernet interface */
5153 E1000_WRITE_REG(hw, RCTL, 0);
5154 E1000_WRITE_REG(hw, TCTL, 0);
5156 /* Clear the transmit ring */
5157 E1000_WRITE_REG(hw, TDH, 0);
5158 E1000_WRITE_REG(hw, TDT, 0);
5160 /* Clear the receive ring */
5161 E1000_WRITE_REG(hw, RDH, 0);
5162 E1000_WRITE_REG(hw, RDT, 0);
5169 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5172 if (hw->mac_type >= e1000_82544)
5173 E1000_WRITE_REG(hw, WUC, 0);
5175 return e1000_init_hw(hw, enetaddr);
5179 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
5183 ret_val = e1000_reset(hw, enetaddr);
5185 if ((ret_val == -E1000_ERR_NOLINK) ||
5186 (ret_val == -E1000_ERR_TIMEOUT)) {
5187 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5189 E1000_ERR(hw, "Hardware Initialization Failed\n");
5193 e1000_configure_tx(hw);
5194 e1000_setup_rctl(hw);
5195 e1000_configure_rx(hw);
5199 /******************************************************************************
5200 * Gets the current PCI bus type of hardware
5202 * hw - Struct containing variables accessed by shared code
5203 *****************************************************************************/
5204 void e1000_get_bus_type(struct e1000_hw *hw)
5208 switch (hw->mac_type) {
5209 case e1000_82542_rev2_0:
5210 case e1000_82542_rev2_1:
5211 hw->bus_type = e1000_bus_type_pci;
5217 case e1000_80003es2lan:
5220 hw->bus_type = e1000_bus_type_pci_express;
5223 status = E1000_READ_REG(hw, STATUS);
5224 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5225 e1000_bus_type_pcix : e1000_bus_type_pci;
5230 #ifndef CONFIG_DM_ETH
5231 /* A list of all registered e1000 devices */
5232 static LIST_HEAD(e1000_hw_list);
5235 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5236 unsigned char enetaddr[6])
5240 /* Assign the passed-in values */
5242 hw->cardnum = cardnum;
5244 /* Print a debug message with the IO base address */
5245 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5246 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5248 /* Try to enable I/O accesses and bus-mastering */
5249 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5250 pci_write_config_dword(devno, PCI_COMMAND, val);
5252 /* Make sure it worked */
5253 pci_read_config_dword(devno, PCI_COMMAND, &val);
5254 if (!(val & PCI_COMMAND_MEMORY)) {
5255 E1000_ERR(hw, "Can't enable I/O memory\n");
5258 if (!(val & PCI_COMMAND_MASTER)) {
5259 E1000_ERR(hw, "Can't enable bus-mastering\n");
5263 /* Are these variables needed? */
5264 hw->fc = e1000_fc_default;
5265 hw->original_fc = e1000_fc_default;
5266 hw->autoneg_failed = 0;
5268 hw->get_link_status = true;
5269 #ifndef CONFIG_E1000_NO_NVM
5270 hw->eeprom_semaphore_present = true;
5272 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5274 hw->mac_type = e1000_undefined;
5276 /* MAC and Phy settings */
5277 if (e1000_sw_init(hw) < 0) {
5278 E1000_ERR(hw, "Software init failed\n");
5281 if (e1000_check_phy_reset_block(hw))
5282 E1000_ERR(hw, "PHY Reset is blocked!\n");
5284 /* Basic init was OK, reset the hardware and allow SPI access */
5287 #ifndef CONFIG_E1000_NO_NVM
5288 /* Validate the EEPROM and get chipset information */
5289 if (e1000_init_eeprom_params(hw)) {
5290 E1000_ERR(hw, "EEPROM is invalid!\n");
5293 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5294 e1000_validate_eeprom_checksum(hw))
5296 e1000_read_mac_addr(hw, enetaddr);
5298 e1000_get_bus_type(hw);
5300 #ifndef CONFIG_E1000_NO_NVM
5301 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5302 enetaddr[0], enetaddr[1], enetaddr[2],
5303 enetaddr[3], enetaddr[4], enetaddr[5]);
5305 memset(enetaddr, 0, 6);
5306 printf("e1000: no NVM\n");
5312 /* Put the name of a device in a string */
5313 static void e1000_name(char *str, int cardnum)
5315 sprintf(str, "e1000#%u", cardnum);
5318 #ifndef CONFIG_DM_ETH
5319 /**************************************************************************
5320 TRANSMIT - Transmit a frame
5321 ***************************************************************************/
5322 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5324 struct e1000_hw *hw = nic->priv;
5326 return _e1000_transmit(hw, txpacket, length);
5329 /**************************************************************************
5330 DISABLE - Turn off ethernet interface
5331 ***************************************************************************/
5333 e1000_disable(struct eth_device *nic)
5335 struct e1000_hw *hw = nic->priv;
5340 /**************************************************************************
5341 INIT - set up ethernet interface(s)
5342 ***************************************************************************/
5344 e1000_init(struct eth_device *nic, bd_t *bis)
5346 struct e1000_hw *hw = nic->priv;
5348 return _e1000_init(hw, nic->enetaddr);
5352 e1000_poll(struct eth_device *nic)
5354 struct e1000_hw *hw = nic->priv;
5357 len = _e1000_poll(hw);
5359 net_process_received_packet((uchar *)packet, len);
5366 /**************************************************************************
5367 PROBE - Look for an adapter, this routine's visible to the outside
5368 You should omit the last argument struct pci_device * for a non-PCI NIC
5369 ***************************************************************************/
5371 e1000_initialize(bd_t * bis)
5379 /* Find and probe all the matching PCI devices */
5380 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5382 * These will never get freed due to errors, this allows us to
5383 * perform SPI EEPROM programming from U-boot, for example.
5385 struct eth_device *nic = malloc(sizeof(*nic));
5386 struct e1000_hw *hw = malloc(sizeof(*hw));
5388 printf("e1000#%u: Out of Memory!\n", i);
5394 /* Make sure all of the fields are initially zeroed */
5395 memset(nic, 0, sizeof(*nic));
5396 memset(hw, 0, sizeof(*hw));
5399 /* Generate a card name */
5400 e1000_name(nic->name, i);
5401 hw->name = nic->name;
5403 ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5406 list_add_tail(&hw->list_node, &e1000_hw_list);
5410 /* Set up the function pointers and register the device */
5411 nic->init = e1000_init;
5412 nic->recv = e1000_poll;
5413 nic->send = e1000_transmit;
5414 nic->halt = e1000_disable;
5421 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5423 struct e1000_hw *hw;
5425 list_for_each_entry(hw, &e1000_hw_list, list_node)
5426 if (hw->cardnum == cardnum)
5431 #endif /* !CONFIG_DM_ETH */
5433 #ifdef CONFIG_CMD_E1000
5434 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5435 int argc, char * const argv[])
5437 unsigned char *mac = NULL;
5438 #ifdef CONFIG_DM_ETH
5439 struct eth_pdata *plat;
5440 struct udevice *dev;
5444 struct e1000_hw *hw;
5453 /* Make sure we can find the requested e1000 card */
5454 cardnum = simple_strtoul(argv[1], NULL, 10);
5455 #ifdef CONFIG_DM_ETH
5456 e1000_name(name, cardnum);
5457 ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5459 plat = dev_get_platdata(dev);
5460 mac = plat->enetaddr;
5463 hw = e1000_find_card(cardnum);
5465 mac = hw->nic->enetaddr;
5468 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5472 if (!strcmp(argv[2], "print-mac-address")) {
5473 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5474 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5478 #ifdef CONFIG_E1000_SPI
5479 /* Handle the "SPI" subcommand */
5480 if (!strcmp(argv[2], "spi"))
5481 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5489 e1000, 7, 0, do_e1000,
5490 "Intel e1000 controller management",
5491 /* */"<card#> print-mac-address\n"
5492 #ifdef CONFIG_E1000_SPI
5493 "e1000 <card#> spi show [<offset> [<length>]]\n"
5494 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5495 "e1000 <card#> spi program <addr> <offset> <length>\n"
5496 "e1000 <card#> spi checksum [update]\n"
5498 " - Manage the Intel E1000 PCI device"
5500 #endif /* not CONFIG_CMD_E1000 */
5502 #ifdef CONFIG_DM_ETH
5503 static int e1000_eth_start(struct udevice *dev)
5505 struct eth_pdata *plat = dev_get_platdata(dev);
5506 struct e1000_hw *hw = dev_get_priv(dev);
5508 return _e1000_init(hw, plat->enetaddr);
5511 static void e1000_eth_stop(struct udevice *dev)
5513 struct e1000_hw *hw = dev_get_priv(dev);
5518 static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5520 struct e1000_hw *hw = dev_get_priv(dev);
5523 ret = _e1000_transmit(hw, packet, length);
5525 return ret ? 0 : -ETIMEDOUT;
5528 static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5530 struct e1000_hw *hw = dev_get_priv(dev);
5533 len = _e1000_poll(hw);
5537 return len ? len : -EAGAIN;
5540 static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5542 struct e1000_hw *hw = dev_get_priv(dev);
5549 static int e1000_eth_probe(struct udevice *dev)
5551 struct eth_pdata *plat = dev_get_platdata(dev);
5552 struct e1000_hw *hw = dev_get_priv(dev);
5555 hw->name = dev->name;
5556 ret = e1000_init_one(hw, trailing_strtol(dev->name),
5557 dm_pci_get_bdf(dev), plat->enetaddr);
5559 printf(pr_fmt("failed to initialize card: %d\n"), ret);
5566 static int e1000_eth_bind(struct udevice *dev)
5571 * A simple way to number the devices. When device tree is used this
5572 * is unnecessary, but when the device is just discovered on the PCI
5573 * bus we need a name. We could instead have the uclass figure out
5574 * which devices are different and number them.
5576 e1000_name(name, num_cards++);
5578 return device_set_name(dev, name);
5581 static const struct eth_ops e1000_eth_ops = {
5582 .start = e1000_eth_start,
5583 .send = e1000_eth_send,
5584 .recv = e1000_eth_recv,
5585 .stop = e1000_eth_stop,
5586 .free_pkt = e1000_free_pkt,
5589 static const struct udevice_id e1000_eth_ids[] = {
5590 { .compatible = "intel,e1000" },
5594 U_BOOT_DRIVER(eth_e1000) = {
5595 .name = "eth_e1000",
5597 .of_match = e1000_eth_ids,
5598 .bind = e1000_eth_bind,
5599 .probe = e1000_eth_probe,
5600 .ops = &e1000_eth_ops,
5601 .priv_auto_alloc_size = sizeof(struct e1000_hw),
5602 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5605 U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);