3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
18 /* Ethernet chip registers.
20 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */
21 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
22 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */
23 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
24 #define SCBPointer 4 /* General purpose pointer. */
25 #define SCBPort 8 /* Misc. commands and operands. */
26 #define SCBflash 12 /* Flash memory control. */
27 #define SCBeeprom 14 /* EEPROM memory control. */
28 #define SCBCtrlMDI 16 /* MDI interface control. */
29 #define SCBEarlyRx 20 /* Early receive byte count. */
30 #define SCBGenControl 28 /* 82559 General Control Register */
31 #define SCBGenStatus 29 /* 82559 General Status register */
33 /* 82559 SCB status word defnitions
35 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
36 #define SCB_STATUS_FR 0x4000 /* frame received */
37 #define SCB_STATUS_CNA 0x2000 /* CU left active state */
38 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
39 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
40 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
41 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
43 #define SCB_INTACK_MASK 0xFD00 /* all the above */
45 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
46 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
48 /* System control block commands
52 #define CU_START 0x0010
53 #define CU_RESUME 0x0020
54 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
55 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
56 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
57 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
60 #define RUC_NOP 0x0000
61 #define RUC_START 0x0001
62 #define RUC_RESUME 0x0002
63 #define RUC_ABORT 0x0004
64 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
65 #define RUC_RESUMENR 0x0007
67 #define CU_CMD_MASK 0x00f0
68 #define RU_CMD_MASK 0x0007
70 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
71 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
73 #define CU_STATUS_MASK 0x00C0
74 #define RU_STATUS_MASK 0x003C
76 #define RU_STATUS_IDLE (0<<2)
77 #define RU_STATUS_SUS (1<<2)
78 #define RU_STATUS_NORES (2<<2)
79 #define RU_STATUS_READY (4<<2)
80 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
81 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
82 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
84 /* 82559 Port interface commands.
86 #define I82559_RESET 0x00000000 /* Software reset */
87 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
88 #define I82559_SELECTIVE_RESET 0x00000002
89 #define I82559_DUMP 0x00000003
90 #define I82559_DUMP_WAKEUP 0x00000007
92 /* 82559 Eeprom interface.
94 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
95 #define EE_CS 0x02 /* EEPROM chip select. */
96 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
97 #define EE_WRITE_0 0x01
98 #define EE_WRITE_1 0x05
99 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
100 #define EE_ENB (0x4800 | EE_CS)
101 #define EE_CMD_BITS 3
102 #define EE_DATA_BITS 16
104 /* The EEPROM commands include the alway-set leading bit.
106 #define EE_EWENB_CMD (4 << addr_len)
107 #define EE_WRITE_CMD (5 << addr_len)
108 #define EE_READ_CMD (6 << addr_len)
109 #define EE_ERASE_CMD (7 << addr_len)
111 /* Receive frame descriptors.
115 volatile u16 control;
116 volatile u32 link; /* struct RxFD * */
117 volatile u32 rx_buf_addr; /* void * */
120 volatile u8 data[PKTSIZE_ALIGN];
123 #define RFD_STATUS_C 0x8000 /* completion of received frame */
124 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
126 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
127 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
128 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
129 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
131 #define RFD_COUNT_MASK 0x3fff
132 #define RFD_COUNT_F 0x4000
133 #define RFD_COUNT_EOF 0x8000
135 #define RFD_RX_CRC 0x0800 /* crc error */
136 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
137 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
138 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
139 #define RFD_RX_SHORT 0x0080 /* short frame error */
140 #define RFD_RX_LENGTH 0x0020
141 #define RFD_RX_ERROR 0x0010 /* receive error */
142 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
143 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
144 #define RFD_RX_TCO 0x0001 /* TCO indication */
146 /* Transmit frame descriptors
148 struct TxFD { /* Transmit frame descriptor set. */
150 volatile u16 command;
151 volatile u32 link; /* void * */
152 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
155 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
156 volatile s32 tx_buf_size0; /* Length of Tx frame. */
157 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
158 volatile s32 tx_buf_size1; /* Length of Tx frame. */
161 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
162 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
163 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
164 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
165 #define TxCB_CMD_S 0x4000 /* suspend on completion */
166 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */
168 #define TxCB_COUNT_MASK 0x3fff
169 #define TxCB_COUNT_EOF 0x8000
171 /* The Speedo3 Rx and Tx frame/buffer descriptors.
173 struct descriptor { /* A generic descriptor. */
175 volatile u16 command;
176 volatile u32 link; /* struct descriptor * */
178 unsigned char params[0];
181 #define CONFIG_SYS_CMD_EL 0x8000
182 #define CONFIG_SYS_CMD_SUSPEND 0x4000
183 #define CONFIG_SYS_CMD_INT 0x2000
184 #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
185 #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
187 #define CONFIG_SYS_STATUS_C 0x8000
188 #define CONFIG_SYS_STATUS_OK 0x2000
192 #define NUM_RX_DESC PKTBUFSRX
193 #define NUM_TX_DESC 1 /* Number of TX descriptors */
195 #define TOUT_LOOP 1000000
199 static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
200 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
201 static int rx_next; /* RX descriptor ring pointer */
202 static int tx_next; /* TX descriptor ring pointer */
203 static int tx_threshold;
206 * The parameters for a CmdConfigure operation.
207 * There are so many options that it would be difficult to document
208 * each bit. We mostly use the default or recommended settings.
210 static const char i82558_config_cmd[] = {
211 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
212 0, 0x2E, 0, 0x60, 0x08, 0x88,
213 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
217 static void init_rx_ring (struct eth_device *dev);
218 static void purge_tx_ring (struct eth_device *dev);
220 static void read_hw_addr (struct eth_device *dev, bd_t * bis);
222 static int eepro100_init (struct eth_device *dev, bd_t * bis);
223 static int eepro100_send(struct eth_device *dev, void *packet, int length);
224 static int eepro100_recv (struct eth_device *dev);
225 static void eepro100_halt (struct eth_device *dev);
227 #if defined(CONFIG_E500)
228 #define bus_to_phys(a) (a)
229 #define phys_to_bus(a) (a)
231 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
232 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
235 static inline int INW (struct eth_device *dev, u_long addr)
237 return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase));
240 static inline void OUTW (struct eth_device *dev, int command, u_long addr)
242 *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command);
245 static inline void OUTL (struct eth_device *dev, int command, u_long addr)
247 *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command);
250 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
251 static inline int INL (struct eth_device *dev, u_long addr)
253 return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase));
256 static int get_phyreg (struct eth_device *dev, unsigned char addr,
257 unsigned char reg, unsigned short *value)
262 /* read requested data */
263 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
264 OUTL (dev, cmd, SCBCtrlMDI);
268 cmd = INL (dev, SCBCtrlMDI);
269 } while (!(cmd & (1 << 28)) && (--timeout));
274 *value = (unsigned short) (cmd & 0xffff);
279 static int set_phyreg (struct eth_device *dev, unsigned char addr,
280 unsigned char reg, unsigned short value)
285 /* write requested data */
286 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
287 OUTL (dev, cmd | value, SCBCtrlMDI);
289 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
298 /* Check if given phyaddr is valid, i.e. there is a PHY connected.
299 * Do this by checking model value field from ID2 register.
301 static struct eth_device* verify_phyaddr (const char *devname,
304 struct eth_device *dev;
305 unsigned short value;
308 dev = eth_get_dev_by_name(devname);
310 printf("%s: no such device\n", devname);
314 /* read id2 register */
315 if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
316 printf("%s: mii read timeout!\n", devname);
321 model = (unsigned char)((value >> 4) & 0x003f);
324 printf("%s: no PHY at address %d\n", devname, addr);
331 static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
334 unsigned short value = 0;
335 struct eth_device *dev;
337 dev = verify_phyaddr(bus->name, addr);
341 if (get_phyreg(dev, addr, reg, &value) != 0) {
342 printf("%s: mii read timeout!\n", bus->name);
349 static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
352 struct eth_device *dev;
354 dev = verify_phyaddr(bus->name, addr);
358 if (set_phyreg(dev, addr, reg, value) != 0) {
359 printf("%s: mii write timeout!\n", bus->name);
368 /* Wait for the chip get the command.
370 static int wait_for_eepro100 (struct eth_device *dev)
374 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
375 if (i >= TOUT_LOOP) {
383 static struct pci_device_id supported[] = {
384 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
385 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
386 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
390 int eepro100_initialize (bd_t * bis)
394 struct eth_device *dev;
401 if ((devno = pci_find_devices (supported, idx++)) < 0) {
405 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
409 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
413 pci_write_config_dword (devno,
415 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
417 /* Check if I/O accesses and Bus Mastering are enabled.
419 pci_read_config_dword (devno, PCI_COMMAND, &status);
420 if (!(status & PCI_COMMAND_MEMORY)) {
421 printf ("Error: Can not enable MEM access.\n");
425 if (!(status & PCI_COMMAND_MASTER)) {
426 printf ("Error: Can not enable Bus Mastering.\n");
430 dev = (struct eth_device *) malloc (sizeof *dev);
432 printf("eepro100: Can not allocate memory\n");
435 memset(dev, 0, sizeof(*dev));
437 sprintf (dev->name, "i82559#%d", card_number);
438 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
439 dev->iobase = bus_to_phys (iobase);
440 dev->init = eepro100_init;
441 dev->halt = eepro100_halt;
442 dev->send = eepro100_send;
443 dev->recv = eepro100_recv;
447 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
448 /* register mii command access routines */
450 struct mii_dev *mdiodev = mdio_alloc();
453 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
454 mdiodev->read = eepro100_miiphy_read;
455 mdiodev->write = eepro100_miiphy_write;
457 retval = mdio_register(mdiodev);
464 /* Set the latency timer for value.
466 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
470 read_hw_addr (dev, bis);
477 static int eepro100_init (struct eth_device *dev, bd_t * bis)
481 struct descriptor *ias_cmd, *cfg_cmd;
483 /* Reset the ethernet controller
485 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
488 OUTL (dev, I82559_RESET, SCBPort);
491 if (!wait_for_eepro100 (dev)) {
492 printf ("Error: Can not reset ethernet controller.\n");
495 OUTL (dev, 0, SCBPointer);
496 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
498 if (!wait_for_eepro100 (dev)) {
499 printf ("Error: Can not reset ethernet controller.\n");
502 OUTL (dev, 0, SCBPointer);
503 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
505 /* Initialize Rx and Tx rings.
510 /* Tell the adapter where the RX ring is located.
512 if (!wait_for_eepro100 (dev)) {
513 printf ("Error: Can not reset ethernet controller.\n");
517 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
518 OUTW (dev, SCB_M | RUC_START, SCBCmd);
520 /* Send the Configure frame */
522 tx_next = ((tx_next + 1) % NUM_TX_DESC);
524 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
525 cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
527 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
529 memcpy (cfg_cmd->params, i82558_config_cmd,
530 sizeof (i82558_config_cmd));
532 if (!wait_for_eepro100 (dev)) {
533 printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
537 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
538 OUTW (dev, SCB_M | CU_START, SCBCmd);
541 !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
543 if (i >= TOUT_LOOP) {
544 printf ("%s: Tx error buffer not ready\n", dev->name);
549 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
550 printf ("TX error status = 0x%08X\n",
551 le16_to_cpu (tx_ring[tx_cur].status));
555 /* Send the Individual Address Setup frame
558 tx_next = ((tx_next + 1) % NUM_TX_DESC);
560 ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
561 ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
563 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
565 memcpy (ias_cmd->params, dev->enetaddr, 6);
567 /* Tell the adapter where the TX ring is located.
569 if (!wait_for_eepro100 (dev)) {
570 printf ("Error: Can not reset ethernet controller.\n");
574 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
575 OUTW (dev, SCB_M | CU_START, SCBCmd);
577 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
579 if (i >= TOUT_LOOP) {
580 printf ("%s: Tx error buffer not ready\n",
586 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
587 printf ("TX error status = 0x%08X\n",
588 le16_to_cpu (tx_ring[tx_cur].status));
598 static int eepro100_send(struct eth_device *dev, void *packet, int length)
604 printf ("%s: bad packet size: %d\n", dev->name, length);
609 tx_next = (tx_next + 1) % NUM_TX_DESC;
611 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
615 tx_ring[tx_cur].status = 0;
616 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
617 tx_ring[tx_cur].link =
618 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
619 tx_ring[tx_cur].tx_desc_addr =
620 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
621 tx_ring[tx_cur].tx_buf_addr0 =
622 cpu_to_le32 (phys_to_bus ((u_long) packet));
623 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
625 if (!wait_for_eepro100 (dev)) {
626 printf ("%s: Tx error ethernet controller not ready.\n",
633 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
634 OUTW (dev, SCB_M | CU_START, SCBCmd);
636 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
638 if (i >= TOUT_LOOP) {
639 printf ("%s: Tx error buffer not ready\n", dev->name);
644 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
645 printf ("TX error status = 0x%08X\n",
646 le16_to_cpu (tx_ring[tx_cur].status));
656 static int eepro100_recv (struct eth_device *dev)
659 int rx_prev, length = 0;
661 stat = INW (dev, SCBStatus);
662 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
665 status = le16_to_cpu (rx_ring[rx_next].status);
667 if (!(status & RFD_STATUS_C)) {
671 /* Valid frame status.
673 if ((status & RFD_STATUS_OK)) {
674 /* A valid frame received.
676 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
678 /* Pass the packet up to the protocol
681 net_process_received_packet((u8 *)rx_ring[rx_next].data,
684 /* There was an error.
686 printf ("RX error status = 0x%08X\n", status);
689 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
690 rx_ring[rx_next].status = 0;
691 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
693 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
694 rx_ring[rx_prev].control = 0;
696 /* Update entry information.
698 rx_next = (rx_next + 1) % NUM_RX_DESC;
701 if (stat & SCB_STATUS_RNR) {
703 printf ("%s: Receiver is not ready, restart it !\n", dev->name);
705 /* Reinitialize Rx ring.
709 if (!wait_for_eepro100 (dev)) {
710 printf ("Error: Can not restart ethernet controller.\n");
714 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
715 OUTW (dev, SCB_M | RUC_START, SCBCmd);
722 static void eepro100_halt (struct eth_device *dev)
724 /* Reset the ethernet controller
726 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
729 OUTL (dev, I82559_RESET, SCBPort);
732 if (!wait_for_eepro100 (dev)) {
733 printf ("Error: Can not reset ethernet controller.\n");
736 OUTL (dev, 0, SCBPointer);
737 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
739 if (!wait_for_eepro100 (dev)) {
740 printf ("Error: Can not reset ethernet controller.\n");
743 OUTL (dev, 0, SCBPointer);
744 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
752 static int read_eeprom (struct eth_device *dev, int location, int addr_len)
754 unsigned short retval = 0;
755 int read_cmd = location | EE_READ_CMD;
758 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
759 OUTW (dev, EE_ENB, SCBeeprom);
761 /* Shift the read command bits out. */
762 for (i = 12; i >= 0; i--) {
763 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
765 OUTW (dev, EE_ENB | dataval, SCBeeprom);
767 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
770 OUTW (dev, EE_ENB, SCBeeprom);
772 for (i = 15; i >= 0; i--) {
773 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
775 retval = (retval << 1) |
776 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
777 OUTW (dev, EE_ENB, SCBeeprom);
781 /* Terminate the EEPROM access. */
782 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
786 #ifdef CONFIG_EEPRO100_SROM_WRITE
787 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
789 unsigned short dataval;
790 int enable_cmd = 0x3f | EE_EWENB_CMD;
791 int write_cmd = location | EE_WRITE_CMD;
793 unsigned long datalong, tmplong;
795 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
797 OUTW(dev, EE_ENB, SCBeeprom);
799 /* Shift the enable command bits out. */
800 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
802 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
803 OUTW(dev, EE_ENB | dataval, SCBeeprom);
805 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
809 OUTW(dev, EE_ENB, SCBeeprom);
811 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
813 OUTW(dev, EE_ENB, SCBeeprom);
816 /* Shift the write command bits out. */
817 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
819 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
820 OUTW(dev, EE_ENB | dataval, SCBeeprom);
822 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
827 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
829 for (i = 0; i< EE_DATA_BITS; i++)
831 /* Extract and move data bit to bit DI */
832 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
834 OUTW(dev, EE_ENB | dataval, SCBeeprom);
836 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
838 OUTW(dev, EE_ENB | dataval, SCBeeprom);
841 datalong = datalong << 1; /* Adjust significant data bit*/
844 /* Finish up command (toggle CS) */
845 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
846 udelay(1); /* delay for more than 250 ns */
847 OUTW(dev, EE_ENB, SCBeeprom);
849 /* Wait for programming ready (D0 = 1) */
853 dataval = INW(dev, SCBeeprom);
854 if (dataval & EE_DATA_READ)
862 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
866 /* Terminate the EEPROM access. */
867 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
873 static void init_rx_ring (struct eth_device *dev)
877 for (i = 0; i < NUM_RX_DESC; i++) {
878 rx_ring[i].status = 0;
880 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
882 cpu_to_le32 (phys_to_bus
883 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
884 rx_ring[i].rx_buf_addr = 0xffffffff;
885 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
891 static void purge_tx_ring (struct eth_device *dev)
896 tx_threshold = 0x01208000;
898 for (i = 0; i < NUM_TX_DESC; i++) {
899 tx_ring[i].status = 0;
900 tx_ring[i].command = 0;
902 tx_ring[i].tx_desc_addr = 0;
903 tx_ring[i].count = 0;
905 tx_ring[i].tx_buf_addr0 = 0;
906 tx_ring[i].tx_buf_size0 = 0;
907 tx_ring[i].tx_buf_addr1 = 0;
908 tx_ring[i].tx_buf_size1 = 0;
912 static void read_hw_addr (struct eth_device *dev, bd_t * bis)
916 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
918 for (j = 0, i = 0; i < 0x40; i++) {
919 u16 value = read_eeprom (dev, i, addr_len);
923 dev->enetaddr[j++] = value;
924 dev->enetaddr[j++] = value >> 8;
929 memset (dev->enetaddr, 0, ETH_ALEN);
931 printf ("%s: Invalid EEPROM checksum %#4.4x, "
932 "check settings before activating this device!\n",