2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
20 #include <asm/errno.h>
21 #include <linux/compiler.h>
23 DECLARE_GLOBAL_DATA_PTR;
26 * Timeout the transfer after 5 mS. This is usually a bit more, since
27 * the code in the tightloops this timeout is used in adds some overhead.
29 #define FEC_XFER_TIMEOUT 5000
32 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
33 * 64-byte alignment in the DMA RX FEC buffer.
34 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
35 * satisfies the alignment on other SoCs (32-bytes)
37 #define FEC_DMA_RX_MINALIGN 64
40 #error "CONFIG_MII has to be defined!"
43 #ifndef CONFIG_FEC_XCV_TYPE
44 #define CONFIG_FEC_XCV_TYPE MII100
48 * The i.MX28 operates with packets in big endian. We need to swap them before
49 * sending and after receiving.
52 #define CONFIG_FEC_MXC_SWAP_PACKET
55 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
57 /* Check various alignment issues at compile time */
58 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
59 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
62 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
63 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
64 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
70 uint8_t data[1500]; /**< actual data */
71 int length; /**< actual length */
72 int used; /**< buffer in use or not */
73 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
76 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
77 static void swap_packet(uint32_t *packet, int length)
81 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
82 packet[i] = __swab32(packet[i]);
87 * MII-interface related functions
89 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
92 uint32_t reg; /* convenient holder for the PHY register */
93 uint32_t phy; /* convenient holder for the PHY */
98 * reading from any PHY's register is done by properly
99 * programming the FEC's MII data register.
101 writel(FEC_IEVENT_MII, ð->ievent);
102 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
103 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
105 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
106 phy | reg, ð->mii_data);
109 * wait for the related interrupt
111 start = get_timer(0);
112 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
113 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
114 printf("Read MDIO failed...\n");
120 * clear mii interrupt bit
122 writel(FEC_IEVENT_MII, ð->ievent);
125 * it's now safe to read the PHY's register
127 val = (unsigned short)readl(ð->mii_data);
128 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
133 static void fec_mii_setspeed(struct ethernet_regs *eth)
136 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
137 * and do not drop the Preamble.
139 register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
140 #ifdef FEC_QUIRK_ENET_MAC
144 writel(speed, ð->mii_speed);
145 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
148 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
149 uint8_t regAddr, uint16_t data)
151 uint32_t reg; /* convenient holder for the PHY register */
152 uint32_t phy; /* convenient holder for the PHY */
155 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
156 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
158 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
159 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
162 * wait for the MII interrupt
164 start = get_timer(0);
165 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
166 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
167 printf("Write MDIO failed...\n");
173 * clear MII interrupt bit
175 writel(FEC_IEVENT_MII, ð->ievent);
176 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
182 int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
184 return fec_mdio_read(bus->priv, phyAddr, regAddr);
187 int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
190 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
193 #ifndef CONFIG_PHYLIB
194 static int miiphy_restart_aneg(struct eth_device *dev)
197 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
198 struct fec_priv *fec = (struct fec_priv *)dev->priv;
199 struct ethernet_regs *eth = fec->bus->priv;
202 * Wake up from sleep if necessary
203 * Reset PHY, then delay 300ns
206 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
208 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
212 * Set the auto-negotiation advertisement register bits
214 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
215 LPA_100FULL | LPA_100HALF | LPA_10FULL |
216 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
217 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
218 BMCR_ANENABLE | BMCR_ANRESTART);
220 if (fec->mii_postcall)
221 ret = fec->mii_postcall(fec->phy_id);
227 static int miiphy_wait_aneg(struct eth_device *dev)
231 struct fec_priv *fec = (struct fec_priv *)dev->priv;
232 struct ethernet_regs *eth = fec->bus->priv;
235 * Wait for AN completion
237 start = get_timer(0);
239 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
240 printf("%s: Autonegotiation timeout\n", dev->name);
244 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
246 printf("%s: Autonegotiation failed. status: %d\n",
250 } while (!(status & BMSR_LSTATUS));
256 static int fec_rx_task_enable(struct fec_priv *fec)
258 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
262 static int fec_rx_task_disable(struct fec_priv *fec)
267 static int fec_tx_task_enable(struct fec_priv *fec)
269 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
273 static int fec_tx_task_disable(struct fec_priv *fec)
279 * Initialize receive task's buffer descriptors
280 * @param[in] fec all we know about the device yet
281 * @param[in] count receive buffer count to be allocated
282 * @param[in] dsize desired size of each receive buffer
283 * @return 0 on success
285 * Init all RX descriptors to default values.
287 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
294 * Reload the RX descriptors with default values and wipe
297 size = roundup(dsize, ARCH_DMA_MINALIGN);
298 for (i = 0; i < count; i++) {
299 data = (uint8_t *)fec->rbd_base[i].data_pointer;
300 memset(data, 0, dsize);
301 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
303 fec->rbd_base[i].status = FEC_RBD_EMPTY;
304 fec->rbd_base[i].data_length = 0;
307 /* Mark the last RBD to close the ring. */
308 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
311 flush_dcache_range((unsigned)fec->rbd_base,
312 (unsigned)fec->rbd_base + size);
316 * Initialize transmit task's buffer descriptors
317 * @param[in] fec all we know about the device yet
319 * Transmit buffers are created externally. We only have to init the BDs here.\n
320 * Note: There is a race condition in the hardware. When only one BD is in
321 * use it must be marked with the WRAP bit to use it for every transmitt.
322 * This bit in combination with the READY bit results into double transmit
323 * of each data buffer. It seems the state machine checks READY earlier then
324 * resetting it after the first transfer.
325 * Using two BDs solves this issue.
327 static void fec_tbd_init(struct fec_priv *fec)
329 unsigned addr = (unsigned)fec->tbd_base;
330 unsigned size = roundup(2 * sizeof(struct fec_bd),
333 memset(fec->tbd_base, 0, size);
334 fec->tbd_base[0].status = 0;
335 fec->tbd_base[1].status = FEC_TBD_WRAP;
337 flush_dcache_range(addr, addr + size);
341 * Mark the given read buffer descriptor as free
342 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
343 * @param[in] pRbd buffer descriptor to mark free again
345 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
347 unsigned short flags = FEC_RBD_EMPTY;
349 flags |= FEC_RBD_WRAP;
350 writew(flags, &pRbd->status);
351 writew(0, &pRbd->data_length);
354 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
357 imx_get_mac_from_fuse(dev_id, mac);
358 return !is_valid_ether_addr(mac);
361 static int fec_set_hwaddr(struct eth_device *dev)
363 uchar *mac = dev->enetaddr;
364 struct fec_priv *fec = (struct fec_priv *)dev->priv;
366 writel(0, &fec->eth->iaddr1);
367 writel(0, &fec->eth->iaddr2);
368 writel(0, &fec->eth->gaddr1);
369 writel(0, &fec->eth->gaddr2);
372 * Set physical address
374 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
376 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
382 * Do initial configuration of the FEC registers
384 static void fec_reg_setup(struct fec_priv *fec)
389 * Set interrupt mask register
391 writel(0x00000000, &fec->eth->imask);
394 * Clear FEC-Lite interrupt event register(IEVENT)
396 writel(0xffffffff, &fec->eth->ievent);
400 * Set FEC-Lite receive control register(R_CNTRL):
403 /* Start with frame length = 1518, common for all modes. */
404 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
405 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
406 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
407 if (fec->xcv_type == RGMII)
408 rcntrl |= FEC_RCNTRL_RGMII;
409 else if (fec->xcv_type == RMII)
410 rcntrl |= FEC_RCNTRL_RMII;
412 writel(rcntrl, &fec->eth->r_cntrl);
416 * Start the FEC engine
417 * @param[in] dev Our device to handle
419 static int fec_open(struct eth_device *edev)
421 struct fec_priv *fec = (struct fec_priv *)edev->priv;
426 debug("fec_open: fec_open(dev)\n");
427 /* full-duplex, heartbeat disabled */
428 writel(1 << 2, &fec->eth->x_cntrl);
431 /* Invalidate all descriptors */
432 for (i = 0; i < FEC_RBD_NUM - 1; i++)
433 fec_rbd_clean(0, &fec->rbd_base[i]);
434 fec_rbd_clean(1, &fec->rbd_base[i]);
436 /* Flush the descriptors into RAM */
437 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
439 addr = (uint32_t)fec->rbd_base;
440 flush_dcache_range(addr, addr + size);
442 #ifdef FEC_QUIRK_ENET_MAC
443 /* Enable ENET HW endian SWAP */
444 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
446 /* Enable ENET store and forward mode */
447 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
451 * Enable FEC-Lite controller
453 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
455 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
458 * setup the MII gasket for RMII mode
461 /* disable the gasket */
462 writew(0, &fec->eth->miigsk_enr);
464 /* wait for the gasket to be disabled */
465 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
468 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
469 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
471 /* re-enable the gasket */
472 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
474 /* wait until MII gasket is ready */
476 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
477 if (--max_loops <= 0) {
478 printf("WAIT for MII Gasket ready timed out\n");
486 /* Start up the PHY */
487 int ret = phy_startup(fec->phydev);
490 printf("Could not initialize PHY %s\n",
491 fec->phydev->dev->name);
494 speed = fec->phydev->speed;
497 miiphy_wait_aneg(edev);
498 speed = miiphy_speed(edev->name, fec->phy_id);
499 miiphy_duplex(edev->name, fec->phy_id);
502 #ifdef FEC_QUIRK_ENET_MAC
504 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
505 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
506 if (speed == _1000BASET)
507 ecr |= FEC_ECNTRL_SPEED;
508 else if (speed != _100BASET)
509 rcr |= FEC_RCNTRL_RMII_10T;
510 writel(ecr, &fec->eth->ecntrl);
511 writel(rcr, &fec->eth->r_cntrl);
514 debug("%s:Speed=%i\n", __func__, speed);
517 * Enable SmartDMA receive task
519 fec_rx_task_enable(fec);
525 static int fec_init(struct eth_device *dev, bd_t* bd)
527 struct fec_priv *fec = (struct fec_priv *)dev->priv;
528 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
531 /* Initialize MAC address */
535 * Setup transmit descriptors, there are two in total.
539 /* Setup receive descriptors. */
540 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
544 if (fec->xcv_type != SEVENWIRE)
545 fec_mii_setspeed(fec->bus->priv);
548 * Set Opcode/Pause Duration Register
550 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
551 writel(0x2, &fec->eth->x_wmrk);
553 * Set multicast address filter
555 writel(0x00000000, &fec->eth->gaddr1);
556 writel(0x00000000, &fec->eth->gaddr2);
560 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
563 /* FIFO receive start register */
564 writel(0x520, &fec->eth->r_fstart);
566 /* size and address of each buffer */
567 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
568 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
569 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
571 #ifndef CONFIG_PHYLIB
572 if (fec->xcv_type != SEVENWIRE)
573 miiphy_restart_aneg(dev);
580 * Halt the FEC engine
581 * @param[in] dev Our device to handle
583 static void fec_halt(struct eth_device *dev)
585 struct fec_priv *fec = (struct fec_priv *)dev->priv;
586 int counter = 0xffff;
589 * issue graceful stop command to the FEC transmitter if necessary
591 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
594 debug("eth_halt: wait for stop regs\n");
596 * wait for graceful stop to register
598 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
602 * Disable SmartDMA tasks
604 fec_tx_task_disable(fec);
605 fec_rx_task_disable(fec);
608 * Disable the Ethernet Controller
609 * Note: this will also reset the BD index counter!
611 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
615 debug("eth_halt: done\n");
620 * @param[in] dev Our ethernet device to handle
621 * @param[in] packet Pointer to the data to be transmitted
622 * @param[in] length Data count in bytes
623 * @return 0 on success
625 static int fec_send(struct eth_device *dev, void *packet, int length)
630 int timeout = FEC_XFER_TIMEOUT;
634 * This routine transmits one frame. This routine only accepts
635 * 6-byte Ethernet addresses.
637 struct fec_priv *fec = (struct fec_priv *)dev->priv;
640 * Check for valid length of data.
642 if ((length > 1500) || (length <= 0)) {
643 printf("Payload (%d) too large\n", length);
648 * Setup the transmit buffer. We are always using the first buffer for
649 * transmission, the second will be empty and only used to stop the DMA
650 * engine. We also flush the packet to RAM here to avoid cache trouble.
652 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
653 swap_packet((uint32_t *)packet, length);
656 addr = (uint32_t)packet;
657 end = roundup(addr + length, ARCH_DMA_MINALIGN);
658 addr &= ~(ARCH_DMA_MINALIGN - 1);
659 flush_dcache_range(addr, end);
661 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
662 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
665 * update BD's status now
667 * - is always the last in a chain (means no chain)
668 * - should transmitt the CRC
669 * - might be the last BD in the list, so the address counter should
670 * wrap (-> keep the WRAP flag)
672 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
673 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
674 writew(status, &fec->tbd_base[fec->tbd_index].status);
677 * Flush data cache. This code flushes both TX descriptors to RAM.
678 * After this code, the descriptors will be safely in RAM and we
681 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
682 addr = (uint32_t)fec->tbd_base;
683 flush_dcache_range(addr, addr + size);
686 * Below we read the DMA descriptor's last four bytes back from the
687 * DRAM. This is important in order to make sure that all WRITE
688 * operations on the bus that were triggered by previous cache FLUSH
691 * Otherwise, on MX28, it is possible to observe a corruption of the
692 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
693 * for the bus structure of MX28. The scenario is as follows:
695 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
696 * to DRAM due to flush_dcache_range()
697 * 2) ARM core writes the FEC registers via AHB_ARB2
698 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
700 * Note that 2) does sometimes finish before 1) due to reordering of
701 * WRITE accesses on the AHB bus, therefore triggering 3) before the
702 * DMA descriptor is fully written into DRAM. This results in occasional
703 * corruption of the DMA descriptor.
705 readl(addr + size - 4);
708 * Enable SmartDMA transmit task
710 fec_tx_task_enable(fec);
713 * Wait until frame is sent. On each turn of the wait cycle, we must
714 * invalidate data cache to see what's really in RAM. Also, we need
718 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
728 * The TDAR bit is cleared when the descriptors are all out from TX
729 * but on mx6solox we noticed that the READY bit is still not cleared
731 * These are two distinct signals, and in IC simulation, we found that
732 * TDAR always gets cleared prior than the READY bit of last BD becomes
734 * In mx6solox, we use a later version of FEC IP. It looks like that
735 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
738 * Fix this by polling the READY bit of BD after the TDAR polling,
739 * which covers the mx6solox case and does not harm the other SoCs.
741 timeout = FEC_XFER_TIMEOUT;
743 invalidate_dcache_range(addr, addr + size);
744 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
753 debug("fec_send: status 0x%x index %d ret %i\n",
754 readw(&fec->tbd_base[fec->tbd_index].status),
755 fec->tbd_index, ret);
756 /* for next transmission use the other buffer */
766 * Pull one frame from the card
767 * @param[in] dev Our ethernet device to handle
768 * @return Length of packet read
770 static int fec_recv(struct eth_device *dev)
772 struct fec_priv *fec = (struct fec_priv *)dev->priv;
773 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
774 unsigned long ievent;
775 int frame_length, len = 0;
778 uint32_t addr, size, end;
780 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
783 * Check if any critical events have happened
785 ievent = readl(&fec->eth->ievent);
786 writel(ievent, &fec->eth->ievent);
787 debug("fec_recv: ievent 0x%lx\n", ievent);
788 if (ievent & FEC_IEVENT_BABR) {
790 fec_init(dev, fec->bd);
791 printf("some error: 0x%08lx\n", ievent);
794 if (ievent & FEC_IEVENT_HBERR) {
795 /* Heartbeat error */
796 writel(0x00000001 | readl(&fec->eth->x_cntrl),
799 if (ievent & FEC_IEVENT_GRA) {
800 /* Graceful stop complete */
801 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
803 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
805 fec_init(dev, fec->bd);
810 * Read the buffer status. Before the status can be read, the data cache
811 * must be invalidated, because the data in RAM might have been changed
812 * by DMA. The descriptors are properly aligned to cachelines so there's
813 * no need to worry they'd overlap.
815 * WARNING: By invalidating the descriptor here, we also invalidate
816 * the descriptors surrounding this one. Therefore we can NOT change the
817 * contents of this descriptor nor the surrounding ones. The problem is
818 * that in order to mark the descriptor as processed, we need to change
819 * the descriptor. The solution is to mark the whole cache line when all
820 * descriptors in the cache line are processed.
822 addr = (uint32_t)rbd;
823 addr &= ~(ARCH_DMA_MINALIGN - 1);
824 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
825 invalidate_dcache_range(addr, addr + size);
827 bd_status = readw(&rbd->status);
828 debug("fec_recv: status 0x%x\n", bd_status);
830 if (!(bd_status & FEC_RBD_EMPTY)) {
831 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
832 ((readw(&rbd->data_length) - 4) > 14)) {
834 * Get buffer address and size
836 frame = (struct nbuf *)readl(&rbd->data_pointer);
837 frame_length = readw(&rbd->data_length) - 4;
839 * Invalidate data cache over the buffer
841 addr = (uint32_t)frame;
842 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
843 addr &= ~(ARCH_DMA_MINALIGN - 1);
844 invalidate_dcache_range(addr, end);
847 * Fill the buffer and pass it to upper layers
849 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
850 swap_packet((uint32_t *)frame->data, frame_length);
852 memcpy(buff, frame->data, frame_length);
853 NetReceive(buff, frame_length);
856 if (bd_status & FEC_RBD_ERR)
857 printf("error frame: 0x%08lx 0x%08x\n",
858 (ulong)rbd->data_pointer,
863 * Free the current buffer, restart the engine and move forward
864 * to the next buffer. Here we check if the whole cacheline of
865 * descriptors was already processed and if so, we mark it free
868 size = RXDESC_PER_CACHELINE - 1;
869 if ((fec->rbd_index & size) == size) {
870 i = fec->rbd_index - size;
871 addr = (uint32_t)&fec->rbd_base[i];
872 for (; i <= fec->rbd_index ; i++) {
873 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
876 flush_dcache_range(addr,
877 addr + ARCH_DMA_MINALIGN);
880 fec_rx_task_enable(fec);
881 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
883 debug("fec_recv: stop\n");
888 static void fec_set_dev_name(char *dest, int dev_id)
890 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
893 static int fec_alloc_descs(struct fec_priv *fec)
899 /* Allocate TX descriptors. */
900 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
901 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
905 /* Allocate RX descriptors. */
906 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
907 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
911 memset(fec->rbd_base, 0, size);
913 /* Allocate RX buffers. */
915 /* Maximum RX buffer size. */
916 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
917 for (i = 0; i < FEC_RBD_NUM; i++) {
918 data = memalign(FEC_DMA_RX_MINALIGN, size);
920 printf("%s: error allocating rxbuf %d\n", __func__, i);
924 memset(data, 0, size);
926 fec->rbd_base[i].data_pointer = (uint32_t)data;
927 fec->rbd_base[i].status = FEC_RBD_EMPTY;
928 fec->rbd_base[i].data_length = 0;
929 /* Flush the buffer to memory. */
930 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
933 /* Mark the last RBD to close the ring. */
934 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
943 free((void *)fec->rbd_base[i].data_pointer);
951 static void fec_free_descs(struct fec_priv *fec)
955 for (i = 0; i < FEC_RBD_NUM; i++)
956 free((void *)fec->rbd_base[i].data_pointer);
962 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
963 struct mii_dev *bus, struct phy_device *phydev)
965 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
966 struct mii_dev *bus, int phy_id)
969 struct eth_device *edev;
970 struct fec_priv *fec;
971 unsigned char ethaddr[6];
975 /* create and fill edev struct */
976 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
978 puts("fec_mxc: not enough malloc memory for eth_device\n");
983 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
985 puts("fec_mxc: not enough malloc memory for fec_priv\n");
990 memset(edev, 0, sizeof(*edev));
991 memset(fec, 0, sizeof(*fec));
993 ret = fec_alloc_descs(fec);
998 edev->init = fec_init;
999 edev->send = fec_send;
1000 edev->recv = fec_recv;
1001 edev->halt = fec_halt;
1002 edev->write_hwaddr = fec_set_hwaddr;
1004 fec->eth = (struct ethernet_regs *)base_addr;
1007 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1010 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1011 start = get_timer(0);
1012 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1013 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1014 printf("FEC MXC: Timeout reseting chip\n");
1021 fec_set_dev_name(edev->name, dev_id);
1022 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1024 fec_mii_setspeed(bus->priv);
1025 #ifdef CONFIG_PHYLIB
1026 fec->phydev = phydev;
1027 phy_connect_dev(phydev, edev);
1031 fec->phy_id = phy_id;
1035 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
1036 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
1037 memcpy(edev->enetaddr, ethaddr, 6);
1038 if (!getenv("ethaddr"))
1039 eth_setenv_enetaddr("ethaddr", ethaddr);
1043 fec_free_descs(fec);
1052 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
1054 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1055 struct mii_dev *bus;
1060 printf("mdio_alloc failed\n");
1063 bus->read = fec_phy_read;
1064 bus->write = fec_phy_write;
1066 fec_set_dev_name(bus->name, dev_id);
1068 ret = mdio_register(bus);
1070 printf("mdio_register failed\n");
1074 fec_mii_setspeed(eth);
1078 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1081 struct mii_dev *bus = NULL;
1082 #ifdef CONFIG_PHYLIB
1083 struct phy_device *phydev = NULL;
1089 * The i.MX28 has two ethernet interfaces, but they are not equal.
1090 * Only the first one can access the MDIO bus.
1092 base_mii = MXS_ENET0_BASE;
1096 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1097 bus = fec_get_miibus(base_mii, dev_id);
1100 #ifdef CONFIG_PHYLIB
1101 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1106 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1108 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1111 #ifdef CONFIG_PHYLIB
1119 #ifdef CONFIG_FEC_MXC_PHYADDR
1120 int fecmxc_initialize(bd_t *bd)
1122 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1127 #ifndef CONFIG_PHYLIB
1128 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1130 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1131 fec->mii_postcall = cb;