2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
21 #include <asm/errno.h>
22 #include <linux/compiler.h>
24 DECLARE_GLOBAL_DATA_PTR;
27 * Timeout the transfer after 5 mS. This is usually a bit more, since
28 * the code in the tightloops this timeout is used in adds some overhead.
30 #define FEC_XFER_TIMEOUT 5000
33 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
34 * 64-byte alignment in the DMA RX FEC buffer.
35 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
36 * satisfies the alignment on other SoCs (32-bytes)
38 #define FEC_DMA_RX_MINALIGN 64
41 #error "CONFIG_MII has to be defined!"
44 #ifndef CONFIG_FEC_XCV_TYPE
45 #define CONFIG_FEC_XCV_TYPE MII100
49 * The i.MX28 operates with packets in big endian. We need to swap them before
50 * sending and after receiving.
53 #define CONFIG_FEC_MXC_SWAP_PACKET
56 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
58 /* Check various alignment issues at compile time */
59 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
60 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
63 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
64 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
65 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
70 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
71 static void swap_packet(uint32_t *packet, int length)
75 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
76 packet[i] = __swab32(packet[i]);
81 * MII-interface related functions
83 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
86 uint32_t reg; /* convenient holder for the PHY register */
87 uint32_t phy; /* convenient holder for the PHY */
92 * reading from any PHY's register is done by properly
93 * programming the FEC's MII data register.
95 writel(FEC_IEVENT_MII, ð->ievent);
96 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
97 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
99 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
100 phy | reg, ð->mii_data);
103 * wait for the related interrupt
105 start = get_timer(0);
106 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
107 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
108 printf("Read MDIO failed...\n");
114 * clear mii interrupt bit
116 writel(FEC_IEVENT_MII, ð->ievent);
119 * it's now safe to read the PHY's register
121 val = (unsigned short)readl(ð->mii_data);
122 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
127 static void fec_mii_setspeed(struct ethernet_regs *eth)
130 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
131 * and do not drop the Preamble.
133 register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
134 #ifdef FEC_QUIRK_ENET_MAC
138 writel(speed, ð->mii_speed);
139 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
142 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
143 uint8_t regAddr, uint16_t data)
145 uint32_t reg; /* convenient holder for the PHY register */
146 uint32_t phy; /* convenient holder for the PHY */
149 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
150 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
152 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
153 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
156 * wait for the MII interrupt
158 start = get_timer(0);
159 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
160 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
161 printf("Write MDIO failed...\n");
167 * clear MII interrupt bit
169 writel(FEC_IEVENT_MII, ð->ievent);
170 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
176 static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
179 return fec_mdio_read(bus->priv, phyAddr, regAddr);
182 static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
183 int regAddr, u16 data)
185 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
188 #ifndef CONFIG_PHYLIB
189 static int miiphy_restart_aneg(struct eth_device *dev)
192 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
193 struct fec_priv *fec = (struct fec_priv *)dev->priv;
194 struct ethernet_regs *eth = fec->bus->priv;
197 * Wake up from sleep if necessary
198 * Reset PHY, then delay 300ns
201 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
203 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
207 * Set the auto-negotiation advertisement register bits
209 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
210 LPA_100FULL | LPA_100HALF | LPA_10FULL |
211 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
212 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
213 BMCR_ANENABLE | BMCR_ANRESTART);
215 if (fec->mii_postcall)
216 ret = fec->mii_postcall(fec->phy_id);
222 static int miiphy_wait_aneg(struct eth_device *dev)
226 struct fec_priv *fec = (struct fec_priv *)dev->priv;
227 struct ethernet_regs *eth = fec->bus->priv;
230 * Wait for AN completion
232 start = get_timer(0);
234 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
235 printf("%s: Autonegotiation timeout\n", dev->name);
239 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
241 printf("%s: Autonegotiation failed. status: %d\n",
245 } while (!(status & BMSR_LSTATUS));
251 static int fec_rx_task_enable(struct fec_priv *fec)
253 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
257 static int fec_rx_task_disable(struct fec_priv *fec)
262 static int fec_tx_task_enable(struct fec_priv *fec)
264 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
268 static int fec_tx_task_disable(struct fec_priv *fec)
274 * Initialize receive task's buffer descriptors
275 * @param[in] fec all we know about the device yet
276 * @param[in] count receive buffer count to be allocated
277 * @param[in] dsize desired size of each receive buffer
278 * @return 0 on success
280 * Init all RX descriptors to default values.
282 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
289 * Reload the RX descriptors with default values and wipe
292 size = roundup(dsize, ARCH_DMA_MINALIGN);
293 for (i = 0; i < count; i++) {
294 data = (uint8_t *)fec->rbd_base[i].data_pointer;
295 memset(data, 0, dsize);
296 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
298 fec->rbd_base[i].status = FEC_RBD_EMPTY;
299 fec->rbd_base[i].data_length = 0;
302 /* Mark the last RBD to close the ring. */
303 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
306 flush_dcache_range((unsigned)fec->rbd_base,
307 (unsigned)fec->rbd_base + size);
311 * Initialize transmit task's buffer descriptors
312 * @param[in] fec all we know about the device yet
314 * Transmit buffers are created externally. We only have to init the BDs here.\n
315 * Note: There is a race condition in the hardware. When only one BD is in
316 * use it must be marked with the WRAP bit to use it for every transmitt.
317 * This bit in combination with the READY bit results into double transmit
318 * of each data buffer. It seems the state machine checks READY earlier then
319 * resetting it after the first transfer.
320 * Using two BDs solves this issue.
322 static void fec_tbd_init(struct fec_priv *fec)
324 unsigned addr = (unsigned)fec->tbd_base;
325 unsigned size = roundup(2 * sizeof(struct fec_bd),
328 memset(fec->tbd_base, 0, size);
329 fec->tbd_base[0].status = 0;
330 fec->tbd_base[1].status = FEC_TBD_WRAP;
332 flush_dcache_range(addr, addr + size);
336 * Mark the given read buffer descriptor as free
337 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
338 * @param[in] pRbd buffer descriptor to mark free again
340 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
342 unsigned short flags = FEC_RBD_EMPTY;
344 flags |= FEC_RBD_WRAP;
345 writew(flags, &pRbd->status);
346 writew(0, &pRbd->data_length);
349 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
352 imx_get_mac_from_fuse(dev_id, mac);
353 return !is_valid_ethaddr(mac);
356 static int fec_set_hwaddr(struct eth_device *dev)
358 uchar *mac = dev->enetaddr;
359 struct fec_priv *fec = (struct fec_priv *)dev->priv;
361 writel(0, &fec->eth->iaddr1);
362 writel(0, &fec->eth->iaddr2);
363 writel(0, &fec->eth->gaddr1);
364 writel(0, &fec->eth->gaddr2);
367 * Set physical address
369 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
371 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
377 * Do initial configuration of the FEC registers
379 static void fec_reg_setup(struct fec_priv *fec)
384 * Set interrupt mask register
386 writel(0x00000000, &fec->eth->imask);
389 * Clear FEC-Lite interrupt event register(IEVENT)
391 writel(0xffffffff, &fec->eth->ievent);
395 * Set FEC-Lite receive control register(R_CNTRL):
398 /* Start with frame length = 1518, common for all modes. */
399 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
400 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
401 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
402 if (fec->xcv_type == RGMII)
403 rcntrl |= FEC_RCNTRL_RGMII;
404 else if (fec->xcv_type == RMII)
405 rcntrl |= FEC_RCNTRL_RMII;
407 writel(rcntrl, &fec->eth->r_cntrl);
411 * Start the FEC engine
412 * @param[in] dev Our device to handle
414 static int fec_open(struct eth_device *edev)
416 struct fec_priv *fec = (struct fec_priv *)edev->priv;
421 debug("fec_open: fec_open(dev)\n");
422 /* full-duplex, heartbeat disabled */
423 writel(1 << 2, &fec->eth->x_cntrl);
426 /* Invalidate all descriptors */
427 for (i = 0; i < FEC_RBD_NUM - 1; i++)
428 fec_rbd_clean(0, &fec->rbd_base[i]);
429 fec_rbd_clean(1, &fec->rbd_base[i]);
431 /* Flush the descriptors into RAM */
432 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
434 addr = (uint32_t)fec->rbd_base;
435 flush_dcache_range(addr, addr + size);
437 #ifdef FEC_QUIRK_ENET_MAC
438 /* Enable ENET HW endian SWAP */
439 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
441 /* Enable ENET store and forward mode */
442 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
446 * Enable FEC-Lite controller
448 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
450 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
453 * setup the MII gasket for RMII mode
456 /* disable the gasket */
457 writew(0, &fec->eth->miigsk_enr);
459 /* wait for the gasket to be disabled */
460 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
463 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
464 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
466 /* re-enable the gasket */
467 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
469 /* wait until MII gasket is ready */
471 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
472 if (--max_loops <= 0) {
473 printf("WAIT for MII Gasket ready timed out\n");
481 /* Start up the PHY */
482 int ret = phy_startup(fec->phydev);
485 printf("Could not initialize PHY %s\n",
486 fec->phydev->dev->name);
489 speed = fec->phydev->speed;
492 miiphy_wait_aneg(edev);
493 speed = miiphy_speed(edev->name, fec->phy_id);
494 miiphy_duplex(edev->name, fec->phy_id);
497 #ifdef FEC_QUIRK_ENET_MAC
499 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
500 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
501 if (speed == _1000BASET)
502 ecr |= FEC_ECNTRL_SPEED;
503 else if (speed != _100BASET)
504 rcr |= FEC_RCNTRL_RMII_10T;
505 writel(ecr, &fec->eth->ecntrl);
506 writel(rcr, &fec->eth->r_cntrl);
509 debug("%s:Speed=%i\n", __func__, speed);
512 * Enable SmartDMA receive task
514 fec_rx_task_enable(fec);
520 static int fec_init(struct eth_device *dev, bd_t* bd)
522 struct fec_priv *fec = (struct fec_priv *)dev->priv;
523 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
526 /* Initialize MAC address */
530 * Setup transmit descriptors, there are two in total.
534 /* Setup receive descriptors. */
535 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
539 if (fec->xcv_type != SEVENWIRE)
540 fec_mii_setspeed(fec->bus->priv);
543 * Set Opcode/Pause Duration Register
545 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
546 writel(0x2, &fec->eth->x_wmrk);
548 * Set multicast address filter
550 writel(0x00000000, &fec->eth->gaddr1);
551 writel(0x00000000, &fec->eth->gaddr2);
555 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
558 /* FIFO receive start register */
559 writel(0x520, &fec->eth->r_fstart);
561 /* size and address of each buffer */
562 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
563 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
564 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
566 #ifndef CONFIG_PHYLIB
567 if (fec->xcv_type != SEVENWIRE)
568 miiphy_restart_aneg(dev);
575 * Halt the FEC engine
576 * @param[in] dev Our device to handle
578 static void fec_halt(struct eth_device *dev)
580 struct fec_priv *fec = (struct fec_priv *)dev->priv;
581 int counter = 0xffff;
584 * issue graceful stop command to the FEC transmitter if necessary
586 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
589 debug("eth_halt: wait for stop regs\n");
591 * wait for graceful stop to register
593 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
597 * Disable SmartDMA tasks
599 fec_tx_task_disable(fec);
600 fec_rx_task_disable(fec);
603 * Disable the Ethernet Controller
604 * Note: this will also reset the BD index counter!
606 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
610 debug("eth_halt: done\n");
615 * @param[in] dev Our ethernet device to handle
616 * @param[in] packet Pointer to the data to be transmitted
617 * @param[in] length Data count in bytes
618 * @return 0 on success
620 static int fec_send(struct eth_device *dev, void *packet, int length)
625 int timeout = FEC_XFER_TIMEOUT;
629 * This routine transmits one frame. This routine only accepts
630 * 6-byte Ethernet addresses.
632 struct fec_priv *fec = (struct fec_priv *)dev->priv;
635 * Check for valid length of data.
637 if ((length > 1500) || (length <= 0)) {
638 printf("Payload (%d) too large\n", length);
643 * Setup the transmit buffer. We are always using the first buffer for
644 * transmission, the second will be empty and only used to stop the DMA
645 * engine. We also flush the packet to RAM here to avoid cache trouble.
647 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
648 swap_packet((uint32_t *)packet, length);
651 addr = (uint32_t)packet;
652 end = roundup(addr + length, ARCH_DMA_MINALIGN);
653 addr &= ~(ARCH_DMA_MINALIGN - 1);
654 flush_dcache_range(addr, end);
656 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
657 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
660 * update BD's status now
662 * - is always the last in a chain (means no chain)
663 * - should transmitt the CRC
664 * - might be the last BD in the list, so the address counter should
665 * wrap (-> keep the WRAP flag)
667 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
668 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
669 writew(status, &fec->tbd_base[fec->tbd_index].status);
672 * Flush data cache. This code flushes both TX descriptors to RAM.
673 * After this code, the descriptors will be safely in RAM and we
676 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
677 addr = (uint32_t)fec->tbd_base;
678 flush_dcache_range(addr, addr + size);
681 * Below we read the DMA descriptor's last four bytes back from the
682 * DRAM. This is important in order to make sure that all WRITE
683 * operations on the bus that were triggered by previous cache FLUSH
686 * Otherwise, on MX28, it is possible to observe a corruption of the
687 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
688 * for the bus structure of MX28. The scenario is as follows:
690 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
691 * to DRAM due to flush_dcache_range()
692 * 2) ARM core writes the FEC registers via AHB_ARB2
693 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
695 * Note that 2) does sometimes finish before 1) due to reordering of
696 * WRITE accesses on the AHB bus, therefore triggering 3) before the
697 * DMA descriptor is fully written into DRAM. This results in occasional
698 * corruption of the DMA descriptor.
700 readl(addr + size - 4);
703 * Enable SmartDMA transmit task
705 fec_tx_task_enable(fec);
708 * Wait until frame is sent. On each turn of the wait cycle, we must
709 * invalidate data cache to see what's really in RAM. Also, we need
713 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
723 * The TDAR bit is cleared when the descriptors are all out from TX
724 * but on mx6solox we noticed that the READY bit is still not cleared
726 * These are two distinct signals, and in IC simulation, we found that
727 * TDAR always gets cleared prior than the READY bit of last BD becomes
729 * In mx6solox, we use a later version of FEC IP. It looks like that
730 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
733 * Fix this by polling the READY bit of BD after the TDAR polling,
734 * which covers the mx6solox case and does not harm the other SoCs.
736 timeout = FEC_XFER_TIMEOUT;
738 invalidate_dcache_range(addr, addr + size);
739 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
748 debug("fec_send: status 0x%x index %d ret %i\n",
749 readw(&fec->tbd_base[fec->tbd_index].status),
750 fec->tbd_index, ret);
751 /* for next transmission use the other buffer */
761 * Pull one frame from the card
762 * @param[in] dev Our ethernet device to handle
763 * @return Length of packet read
765 static int fec_recv(struct eth_device *dev)
767 struct fec_priv *fec = (struct fec_priv *)dev->priv;
768 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
769 unsigned long ievent;
770 int frame_length, len = 0;
772 uint32_t addr, size, end;
774 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
777 * Check if any critical events have happened
779 ievent = readl(&fec->eth->ievent);
780 writel(ievent, &fec->eth->ievent);
781 debug("fec_recv: ievent 0x%lx\n", ievent);
782 if (ievent & FEC_IEVENT_BABR) {
784 fec_init(dev, fec->bd);
785 printf("some error: 0x%08lx\n", ievent);
788 if (ievent & FEC_IEVENT_HBERR) {
789 /* Heartbeat error */
790 writel(0x00000001 | readl(&fec->eth->x_cntrl),
793 if (ievent & FEC_IEVENT_GRA) {
794 /* Graceful stop complete */
795 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
797 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
799 fec_init(dev, fec->bd);
804 * Read the buffer status. Before the status can be read, the data cache
805 * must be invalidated, because the data in RAM might have been changed
806 * by DMA. The descriptors are properly aligned to cachelines so there's
807 * no need to worry they'd overlap.
809 * WARNING: By invalidating the descriptor here, we also invalidate
810 * the descriptors surrounding this one. Therefore we can NOT change the
811 * contents of this descriptor nor the surrounding ones. The problem is
812 * that in order to mark the descriptor as processed, we need to change
813 * the descriptor. The solution is to mark the whole cache line when all
814 * descriptors in the cache line are processed.
816 addr = (uint32_t)rbd;
817 addr &= ~(ARCH_DMA_MINALIGN - 1);
818 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
819 invalidate_dcache_range(addr, addr + size);
821 bd_status = readw(&rbd->status);
822 debug("fec_recv: status 0x%x\n", bd_status);
824 if (!(bd_status & FEC_RBD_EMPTY)) {
825 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
826 ((readw(&rbd->data_length) - 4) > 14)) {
828 * Get buffer address and size
830 addr = readl(&rbd->data_pointer);
831 frame_length = readw(&rbd->data_length) - 4;
833 * Invalidate data cache over the buffer
835 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
836 addr &= ~(ARCH_DMA_MINALIGN - 1);
837 invalidate_dcache_range(addr, end);
840 * Fill the buffer and pass it to upper layers
842 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
843 swap_packet((uint32_t *)addr, frame_length);
845 memcpy(buff, (char *)addr, frame_length);
846 net_process_received_packet(buff, frame_length);
849 if (bd_status & FEC_RBD_ERR)
850 printf("error frame: 0x%08x 0x%08x\n",
855 * Free the current buffer, restart the engine and move forward
856 * to the next buffer. Here we check if the whole cacheline of
857 * descriptors was already processed and if so, we mark it free
860 size = RXDESC_PER_CACHELINE - 1;
861 if ((fec->rbd_index & size) == size) {
862 i = fec->rbd_index - size;
863 addr = (uint32_t)&fec->rbd_base[i];
864 for (; i <= fec->rbd_index ; i++) {
865 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
868 flush_dcache_range(addr,
869 addr + ARCH_DMA_MINALIGN);
872 fec_rx_task_enable(fec);
873 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
875 debug("fec_recv: stop\n");
880 static void fec_set_dev_name(char *dest, int dev_id)
882 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
885 static int fec_alloc_descs(struct fec_priv *fec)
891 /* Allocate TX descriptors. */
892 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
893 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
897 /* Allocate RX descriptors. */
898 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
899 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
903 memset(fec->rbd_base, 0, size);
905 /* Allocate RX buffers. */
907 /* Maximum RX buffer size. */
908 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
909 for (i = 0; i < FEC_RBD_NUM; i++) {
910 data = memalign(FEC_DMA_RX_MINALIGN, size);
912 printf("%s: error allocating rxbuf %d\n", __func__, i);
916 memset(data, 0, size);
918 fec->rbd_base[i].data_pointer = (uint32_t)data;
919 fec->rbd_base[i].status = FEC_RBD_EMPTY;
920 fec->rbd_base[i].data_length = 0;
921 /* Flush the buffer to memory. */
922 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
925 /* Mark the last RBD to close the ring. */
926 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
935 free((void *)fec->rbd_base[i].data_pointer);
943 static void fec_free_descs(struct fec_priv *fec)
947 for (i = 0; i < FEC_RBD_NUM; i++)
948 free((void *)fec->rbd_base[i].data_pointer);
954 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
955 struct mii_dev *bus, struct phy_device *phydev)
957 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
958 struct mii_dev *bus, int phy_id)
961 struct eth_device *edev;
962 struct fec_priv *fec;
963 unsigned char ethaddr[6];
967 /* create and fill edev struct */
968 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
970 puts("fec_mxc: not enough malloc memory for eth_device\n");
975 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
977 puts("fec_mxc: not enough malloc memory for fec_priv\n");
982 memset(edev, 0, sizeof(*edev));
983 memset(fec, 0, sizeof(*fec));
985 ret = fec_alloc_descs(fec);
990 edev->init = fec_init;
991 edev->send = fec_send;
992 edev->recv = fec_recv;
993 edev->halt = fec_halt;
994 edev->write_hwaddr = fec_set_hwaddr;
996 fec->eth = (struct ethernet_regs *)base_addr;
999 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1002 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1003 start = get_timer(0);
1004 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1005 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1006 printf("FEC MXC: Timeout reseting chip\n");
1013 fec_set_dev_name(edev->name, dev_id);
1014 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1016 fec_mii_setspeed(bus->priv);
1017 #ifdef CONFIG_PHYLIB
1018 fec->phydev = phydev;
1019 phy_connect_dev(phydev, edev);
1023 fec->phy_id = phy_id;
1027 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
1028 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
1029 memcpy(edev->enetaddr, ethaddr, 6);
1030 if (!getenv("ethaddr"))
1031 eth_setenv_enetaddr("ethaddr", ethaddr);
1035 fec_free_descs(fec);
1044 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
1046 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1047 struct mii_dev *bus;
1052 printf("mdio_alloc failed\n");
1055 bus->read = fec_phy_read;
1056 bus->write = fec_phy_write;
1058 fec_set_dev_name(bus->name, dev_id);
1060 ret = mdio_register(bus);
1062 printf("mdio_register failed\n");
1066 fec_mii_setspeed(eth);
1070 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1073 struct mii_dev *bus = NULL;
1074 #ifdef CONFIG_PHYLIB
1075 struct phy_device *phydev = NULL;
1081 * The i.MX28 has two ethernet interfaces, but they are not equal.
1082 * Only the first one can access the MDIO bus.
1084 base_mii = MXS_ENET0_BASE;
1088 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1089 bus = fec_get_miibus(base_mii, dev_id);
1092 #ifdef CONFIG_PHYLIB
1093 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1098 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1100 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1103 #ifdef CONFIG_PHYLIB
1111 #ifdef CONFIG_FEC_MXC_PHYADDR
1112 int fecmxc_initialize(bd_t *bd)
1114 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1119 #ifndef CONFIG_PHYLIB
1120 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1122 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1123 fec->mii_postcall = cb;