2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
33 #include <asm/errno.h>
34 #include <linux/compiler.h>
36 DECLARE_GLOBAL_DATA_PTR;
39 #error "CONFIG_MII has to be defined!"
42 #ifndef CONFIG_FEC_XCV_TYPE
43 #define CONFIG_FEC_XCV_TYPE MII100
47 * The i.MX28 operates with packets in big endian. We need to swap them before
48 * sending and after receiving.
51 #define CONFIG_FEC_MXC_SWAP_PACKET
54 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
56 /* Check various alignment issues at compile time */
57 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
58 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
61 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
62 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
63 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
69 uint8_t data[1500]; /**< actual data */
70 int length; /**< actual length */
71 int used; /**< buffer in use or not */
72 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
75 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
76 static void swap_packet(uint32_t *packet, int length)
80 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
81 packet[i] = __swab32(packet[i]);
86 * MII-interface related functions
88 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
91 uint32_t reg; /* convenient holder for the PHY register */
92 uint32_t phy; /* convenient holder for the PHY */
97 * reading from any PHY's register is done by properly
98 * programming the FEC's MII data register.
100 writel(FEC_IEVENT_MII, ð->ievent);
101 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
102 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
104 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
105 phy | reg, ð->mii_data);
108 * wait for the related interrupt
110 start = get_timer(0);
111 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
112 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
113 printf("Read MDIO failed...\n");
119 * clear mii interrupt bit
121 writel(FEC_IEVENT_MII, ð->ievent);
124 * it's now safe to read the PHY's register
126 val = (unsigned short)readl(ð->mii_data);
127 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
132 static void fec_mii_setspeed(struct fec_priv *fec)
135 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
136 * and do not drop the Preamble.
138 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
139 &fec->eth->mii_speed);
140 debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed));
143 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
144 uint8_t regAddr, uint16_t data)
146 uint32_t reg; /* convenient holder for the PHY register */
147 uint32_t phy; /* convenient holder for the PHY */
150 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
151 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
153 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
154 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
157 * wait for the MII interrupt
159 start = get_timer(0);
160 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
161 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
162 printf("Write MDIO failed...\n");
168 * clear MII interrupt bit
170 writel(FEC_IEVENT_MII, ð->ievent);
171 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
177 int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
179 return fec_mdio_read(bus->priv, phyAddr, regAddr);
182 int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
185 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
188 #ifndef CONFIG_PHYLIB
189 static int miiphy_restart_aneg(struct eth_device *dev)
192 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
193 struct fec_priv *fec = (struct fec_priv *)dev->priv;
194 struct ethernet_regs *eth = fec->bus->priv;
197 * Wake up from sleep if necessary
198 * Reset PHY, then delay 300ns
201 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
203 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
207 * Set the auto-negotiation advertisement register bits
209 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
210 LPA_100FULL | LPA_100HALF | LPA_10FULL |
211 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
212 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
213 BMCR_ANENABLE | BMCR_ANRESTART);
215 if (fec->mii_postcall)
216 ret = fec->mii_postcall(fec->phy_id);
222 static int miiphy_wait_aneg(struct eth_device *dev)
226 struct fec_priv *fec = (struct fec_priv *)dev->priv;
227 struct ethernet_regs *eth = fec->bus->priv;
230 * Wait for AN completion
232 start = get_timer(0);
234 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
235 printf("%s: Autonegotiation timeout\n", dev->name);
239 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
241 printf("%s: Autonegotiation failed. status: %d\n",
245 } while (!(status & BMSR_LSTATUS));
251 static int fec_rx_task_enable(struct fec_priv *fec)
253 writel(1 << 24, &fec->eth->r_des_active);
257 static int fec_rx_task_disable(struct fec_priv *fec)
262 static int fec_tx_task_enable(struct fec_priv *fec)
264 writel(1 << 24, &fec->eth->x_des_active);
268 static int fec_tx_task_disable(struct fec_priv *fec)
274 * Initialize receive task's buffer descriptors
275 * @param[in] fec all we know about the device yet
276 * @param[in] count receive buffer count to be allocated
277 * @param[in] dsize desired size of each receive buffer
278 * @return 0 on success
280 * For this task we need additional memory for the data buffers. And each
281 * data buffer requires some alignment. Thy must be aligned to a specific
284 static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
290 * Allocate memory for the buffers. This allocation respects the
293 size = roundup(dsize, ARCH_DMA_MINALIGN);
294 for (i = 0; i < count; i++) {
295 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
297 uint8_t *data = memalign(ARCH_DMA_MINALIGN,
300 printf("%s: error allocating rxbuf %d\n",
304 writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
305 } /* needs allocation */
306 writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
307 writew(0, &fec->rbd_base[i].data_length);
310 /* Mark the last RBD to close the ring. */
311 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
317 for (; i >= 0; i--) {
318 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
319 free((void *)data_ptr);
326 * Initialize transmit task's buffer descriptors
327 * @param[in] fec all we know about the device yet
329 * Transmit buffers are created externally. We only have to init the BDs here.\n
330 * Note: There is a race condition in the hardware. When only one BD is in
331 * use it must be marked with the WRAP bit to use it for every transmitt.
332 * This bit in combination with the READY bit results into double transmit
333 * of each data buffer. It seems the state machine checks READY earlier then
334 * resetting it after the first transfer.
335 * Using two BDs solves this issue.
337 static void fec_tbd_init(struct fec_priv *fec)
339 unsigned addr = (unsigned)fec->tbd_base;
340 unsigned size = roundup(2 * sizeof(struct fec_bd),
342 writew(0x0000, &fec->tbd_base[0].status);
343 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
345 flush_dcache_range(addr, addr+size);
349 * Mark the given read buffer descriptor as free
350 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
351 * @param[in] pRbd buffer descriptor to mark free again
353 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
355 unsigned short flags = FEC_RBD_EMPTY;
357 flags |= FEC_RBD_WRAP;
358 writew(flags, &pRbd->status);
359 writew(0, &pRbd->data_length);
362 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
365 imx_get_mac_from_fuse(dev_id, mac);
366 return !is_valid_ether_addr(mac);
369 static int fec_set_hwaddr(struct eth_device *dev)
371 uchar *mac = dev->enetaddr;
372 struct fec_priv *fec = (struct fec_priv *)dev->priv;
374 writel(0, &fec->eth->iaddr1);
375 writel(0, &fec->eth->iaddr2);
376 writel(0, &fec->eth->gaddr1);
377 writel(0, &fec->eth->gaddr2);
380 * Set physical address
382 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
384 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
389 static void fec_eth_phy_config(struct eth_device *dev)
392 struct fec_priv *fec = (struct fec_priv *)dev->priv;
393 struct phy_device *phydev;
395 phydev = phy_connect(fec->bus, fec->phy_id, dev,
396 PHY_INTERFACE_MODE_RGMII);
398 fec->phydev = phydev;
405 * Do initial configuration of the FEC registers
407 static void fec_reg_setup(struct fec_priv *fec)
412 * Set interrupt mask register
414 writel(0x00000000, &fec->eth->imask);
417 * Clear FEC-Lite interrupt event register(IEVENT)
419 writel(0xffffffff, &fec->eth->ievent);
423 * Set FEC-Lite receive control register(R_CNTRL):
426 /* Start with frame length = 1518, common for all modes. */
427 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
428 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
429 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
430 if (fec->xcv_type == RGMII)
431 rcntrl |= FEC_RCNTRL_RGMII;
432 else if (fec->xcv_type == RMII)
433 rcntrl |= FEC_RCNTRL_RMII;
435 writel(rcntrl, &fec->eth->r_cntrl);
439 * Start the FEC engine
440 * @param[in] dev Our device to handle
442 static int fec_open(struct eth_device *edev)
444 struct fec_priv *fec = (struct fec_priv *)edev->priv;
449 debug("fec_open: fec_open(dev)\n");
450 /* full-duplex, heartbeat disabled */
451 writel(1 << 2, &fec->eth->x_cntrl);
454 /* Invalidate all descriptors */
455 for (i = 0; i < FEC_RBD_NUM - 1; i++)
456 fec_rbd_clean(0, &fec->rbd_base[i]);
457 fec_rbd_clean(1, &fec->rbd_base[i]);
459 /* Flush the descriptors into RAM */
460 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
462 addr = (uint32_t)fec->rbd_base;
463 flush_dcache_range(addr, addr + size);
465 #ifdef FEC_QUIRK_ENET_MAC
466 /* Enable ENET HW endian SWAP */
467 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
469 /* Enable ENET store and forward mode */
470 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
474 * Enable FEC-Lite controller
476 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
478 #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
481 * setup the MII gasket for RMII mode
484 /* disable the gasket */
485 writew(0, &fec->eth->miigsk_enr);
487 /* wait for the gasket to be disabled */
488 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
491 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
492 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
494 /* re-enable the gasket */
495 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
497 /* wait until MII gasket is ready */
499 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
500 if (--max_loops <= 0) {
501 printf("WAIT for MII Gasket ready timed out\n");
509 fec_eth_phy_config(edev);
511 /* Start up the PHY */
512 int ret = phy_startup(fec->phydev);
515 printf("Could not initialize PHY %s\n",
516 fec->phydev->dev->name);
519 speed = fec->phydev->speed;
524 miiphy_wait_aneg(edev);
525 speed = miiphy_speed(edev->name, fec->phy_id);
526 miiphy_duplex(edev->name, fec->phy_id);
529 #ifdef FEC_QUIRK_ENET_MAC
531 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
532 u32 rcr = (readl(&fec->eth->r_cntrl) &
533 ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
534 FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
535 if (speed == _1000BASET)
536 ecr |= FEC_ECNTRL_SPEED;
537 else if (speed != _100BASET)
538 rcr |= FEC_RCNTRL_RMII_10T;
539 writel(ecr, &fec->eth->ecntrl);
540 writel(rcr, &fec->eth->r_cntrl);
543 debug("%s:Speed=%i\n", __func__, speed);
546 * Enable SmartDMA receive task
548 fec_rx_task_enable(fec);
554 static int fec_init(struct eth_device *dev, bd_t* bd)
556 struct fec_priv *fec = (struct fec_priv *)dev->priv;
557 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
561 /* Initialize MAC address */
565 * Allocate transmit descriptors, there are two in total. This
566 * allocation respects cache alignment.
568 if (!fec->tbd_base) {
569 size = roundup(2 * sizeof(struct fec_bd),
571 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
572 if (!fec->tbd_base) {
576 memset(fec->tbd_base, 0, size);
578 flush_dcache_range((unsigned)fec->tbd_base, size);
582 * Allocate receive descriptors. This allocation respects cache
585 if (!fec->rbd_base) {
586 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
588 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
589 if (!fec->rbd_base) {
593 memset(fec->rbd_base, 0, size);
595 * Initialize RxBD ring
597 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
601 flush_dcache_range((unsigned)fec->rbd_base,
602 (unsigned)fec->rbd_base + size);
607 if (fec->xcv_type != SEVENWIRE)
608 fec_mii_setspeed(fec);
611 * Set Opcode/Pause Duration Register
613 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
614 writel(0x2, &fec->eth->x_wmrk);
616 * Set multicast address filter
618 writel(0x00000000, &fec->eth->gaddr1);
619 writel(0x00000000, &fec->eth->gaddr2);
623 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
626 /* FIFO receive start register */
627 writel(0x520, &fec->eth->r_fstart);
629 /* size and address of each buffer */
630 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
631 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
632 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
634 #ifndef CONFIG_PHYLIB
635 if (fec->xcv_type != SEVENWIRE)
636 miiphy_restart_aneg(dev);
650 * Halt the FEC engine
651 * @param[in] dev Our device to handle
653 static void fec_halt(struct eth_device *dev)
655 struct fec_priv *fec = (struct fec_priv *)dev->priv;
656 int counter = 0xffff;
659 * issue graceful stop command to the FEC transmitter if necessary
661 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
664 debug("eth_halt: wait for stop regs\n");
666 * wait for graceful stop to register
668 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
672 * Disable SmartDMA tasks
674 fec_tx_task_disable(fec);
675 fec_rx_task_disable(fec);
678 * Disable the Ethernet Controller
679 * Note: this will also reset the BD index counter!
681 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
685 debug("eth_halt: done\n");
690 * @param[in] dev Our ethernet device to handle
691 * @param[in] packet Pointer to the data to be transmitted
692 * @param[in] length Data count in bytes
693 * @return 0 on success
695 static int fec_send(struct eth_device *dev, void *packet, int length)
702 * This routine transmits one frame. This routine only accepts
703 * 6-byte Ethernet addresses.
705 struct fec_priv *fec = (struct fec_priv *)dev->priv;
708 * Check for valid length of data.
710 if ((length > 1500) || (length <= 0)) {
711 printf("Payload (%d) too large\n", length);
716 * Setup the transmit buffer. We are always using the first buffer for
717 * transmission, the second will be empty and only used to stop the DMA
718 * engine. We also flush the packet to RAM here to avoid cache trouble.
720 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
721 swap_packet((uint32_t *)packet, length);
724 addr = (uint32_t)packet;
725 end = roundup(addr + length, ARCH_DMA_MINALIGN);
726 addr &= ~(ARCH_DMA_MINALIGN - 1);
727 flush_dcache_range(addr, end);
729 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
730 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
733 * update BD's status now
735 * - is always the last in a chain (means no chain)
736 * - should transmitt the CRC
737 * - might be the last BD in the list, so the address counter should
738 * wrap (-> keep the WRAP flag)
740 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
741 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
742 writew(status, &fec->tbd_base[fec->tbd_index].status);
745 * Flush data cache. This code flushes both TX descriptors to RAM.
746 * After this code, the descriptors will be safely in RAM and we
749 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
750 addr = (uint32_t)fec->tbd_base;
751 flush_dcache_range(addr, addr + size);
754 * Enable SmartDMA transmit task
756 fec_tx_task_enable(fec);
759 * Wait until frame is sent. On each turn of the wait cycle, we must
760 * invalidate data cache to see what's really in RAM. Also, we need
763 invalidate_dcache_range(addr, addr + size);
764 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
766 invalidate_dcache_range(addr, addr + size);
769 debug("fec_send: status 0x%x index %d\n",
770 readw(&fec->tbd_base[fec->tbd_index].status),
772 /* for next transmission use the other buffer */
782 * Pull one frame from the card
783 * @param[in] dev Our ethernet device to handle
784 * @return Length of packet read
786 static int fec_recv(struct eth_device *dev)
788 struct fec_priv *fec = (struct fec_priv *)dev->priv;
789 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
790 unsigned long ievent;
791 int frame_length, len = 0;
794 uint32_t addr, size, end;
796 uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN);
799 * Check if any critical events have happened
801 ievent = readl(&fec->eth->ievent);
802 writel(ievent, &fec->eth->ievent);
803 debug("fec_recv: ievent 0x%lx\n", ievent);
804 if (ievent & FEC_IEVENT_BABR) {
806 fec_init(dev, fec->bd);
807 printf("some error: 0x%08lx\n", ievent);
810 if (ievent & FEC_IEVENT_HBERR) {
811 /* Heartbeat error */
812 writel(0x00000001 | readl(&fec->eth->x_cntrl),
815 if (ievent & FEC_IEVENT_GRA) {
816 /* Graceful stop complete */
817 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
819 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
821 fec_init(dev, fec->bd);
826 * Read the buffer status. Before the status can be read, the data cache
827 * must be invalidated, because the data in RAM might have been changed
828 * by DMA. The descriptors are properly aligned to cachelines so there's
829 * no need to worry they'd overlap.
831 * WARNING: By invalidating the descriptor here, we also invalidate
832 * the descriptors surrounding this one. Therefore we can NOT change the
833 * contents of this descriptor nor the surrounding ones. The problem is
834 * that in order to mark the descriptor as processed, we need to change
835 * the descriptor. The solution is to mark the whole cache line when all
836 * descriptors in the cache line are processed.
838 addr = (uint32_t)rbd;
839 addr &= ~(ARCH_DMA_MINALIGN - 1);
840 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
841 invalidate_dcache_range(addr, addr + size);
843 bd_status = readw(&rbd->status);
844 debug("fec_recv: status 0x%x\n", bd_status);
846 if (!(bd_status & FEC_RBD_EMPTY)) {
847 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
848 ((readw(&rbd->data_length) - 4) > 14)) {
850 * Get buffer address and size
852 frame = (struct nbuf *)readl(&rbd->data_pointer);
853 frame_length = readw(&rbd->data_length) - 4;
855 * Invalidate data cache over the buffer
857 addr = (uint32_t)frame;
858 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
859 addr &= ~(ARCH_DMA_MINALIGN - 1);
860 invalidate_dcache_range(addr, end);
863 * Fill the buffer and pass it to upper layers
865 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
866 swap_packet((uint32_t *)frame->data, frame_length);
868 memcpy(buff, frame->data, frame_length);
869 NetReceive(buff, frame_length);
872 if (bd_status & FEC_RBD_ERR)
873 printf("error frame: 0x%08lx 0x%08x\n",
874 (ulong)rbd->data_pointer,
879 * Free the current buffer, restart the engine and move forward
880 * to the next buffer. Here we check if the whole cacheline of
881 * descriptors was already processed and if so, we mark it free
884 size = RXDESC_PER_CACHELINE - 1;
885 if ((fec->rbd_index & size) == size) {
886 i = fec->rbd_index - size;
887 addr = (uint32_t)&fec->rbd_base[i];
888 for (; i <= fec->rbd_index ; i++) {
889 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
892 flush_dcache_range(addr,
893 addr + ARCH_DMA_MINALIGN);
896 fec_rx_task_enable(fec);
897 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
899 debug("fec_recv: stop\n");
904 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
906 struct eth_device *edev;
907 struct fec_priv *fec;
909 unsigned char ethaddr[6];
913 /* create and fill edev struct */
914 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
916 puts("fec_mxc: not enough malloc memory for eth_device\n");
921 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
923 puts("fec_mxc: not enough malloc memory for fec_priv\n");
928 memset(edev, 0, sizeof(*edev));
929 memset(fec, 0, sizeof(*fec));
932 edev->init = fec_init;
933 edev->send = fec_send;
934 edev->recv = fec_recv;
935 edev->halt = fec_halt;
936 edev->write_hwaddr = fec_set_hwaddr;
938 fec->eth = (struct ethernet_regs *)base_addr;
941 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
944 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
945 start = get_timer(0);
946 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
947 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
948 printf("FEC MXC: Timeout reseting chip\n");
955 fec_mii_setspeed(fec);
958 sprintf(edev->name, "FEC");
961 sprintf(edev->name, "FEC%i", dev_id);
962 fec->dev_id = dev_id;
964 fec->phy_id = phy_id;
968 printf("mdio_alloc failed\n");
972 bus->read = fec_phy_read;
973 bus->write = fec_phy_write;
974 sprintf(bus->name, edev->name);
977 * The i.MX28 has two ethernet interfaces, but they are not equal.
978 * Only the first one can access the MDIO bus.
980 bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE;
982 bus->priv = fec->eth;
984 ret = mdio_register(bus);
986 printf("mdio_register failed\n");
994 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
995 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
996 memcpy(edev->enetaddr, ethaddr, 6);
999 fec_eth_phy_config(edev);
1010 #ifndef CONFIG_FEC_MXC_MULTI
1011 int fecmxc_initialize(bd_t *bd)
1015 debug("eth_init: fec_probe(bd)\n");
1016 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
1022 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1026 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1027 lout = fec_probe(bd, dev_id, phy_id, addr);
1032 #ifndef CONFIG_PHYLIB
1033 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1035 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1036 fec->mii_postcall = cb;