git.sur5r.net Git - u-boot/blob - drivers/net/fm/p4080.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  */
   5 #include <common.h>
   6 #include <phy.h>
   7 #include <fm_eth.h>
   8 #include <asm/io.h>
   9 #include <asm/immap_85xx.h>
  10 #include <asm/fsl_serdes.h>
  11
  12 static u32 port_to_devdisr[] = {
  13         [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  14         [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  15         [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  16         [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  17         [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
  18         [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
  19         [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
  20         [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
  21         [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
  22         [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
  23 };
  24
  25 static int is_device_disabled(enum fm_port port)
  26 {
  27         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  28         u32 devdisr2 = in_be32(&gur->devdisr2);
  29
  30         return port_to_devdisr[port] & devdisr2;
  31 }
  32
  33 void fman_disable_port(enum fm_port port)
  34 {
  35         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  36
  37         /* don't allow disabling of DTSEC1 as its needed for MDIO */
  38         if (port == FM1_DTSEC1)
  39                 return;
  40
  41         setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  42 }
  43
  44 void fman_enable_port(enum fm_port port)
  45 {
  46         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  47
  48         clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  49 }
  50
  51 phy_interface_t fman_port_enet_if(enum fm_port port)
  52 {
  53         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  54         u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  55
  56         if (is_device_disabled(port))
  57                 return PHY_INTERFACE_MODE_NONE;
  58
  59         if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
  60                 return PHY_INTERFACE_MODE_XGMII;
  61
  62         if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
  63                 return PHY_INTERFACE_MODE_XGMII;
  64
  65         /* handle RGMII first */
  66         if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  67                 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
  68                 return PHY_INTERFACE_MODE_RGMII;
  69
  70         if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  71                 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
  72                 return PHY_INTERFACE_MODE_RGMII;
  73
  74         if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  75                 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
  76                 return PHY_INTERFACE_MODE_RGMII;
  77
  78         switch (port) {
  79         case FM1_DTSEC1:
  80         case FM1_DTSEC2:
  81         case FM1_DTSEC3:
  82         case FM1_DTSEC4:
  83                 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  84                         return PHY_INTERFACE_MODE_SGMII;
  85                 break;
  86         case FM2_DTSEC1:
  87         case FM2_DTSEC2:
  88         case FM2_DTSEC3:
  89         case FM2_DTSEC4:
  90                 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
  91                         return PHY_INTERFACE_MODE_SGMII;
  92                 break;
  93         default:
  94                 return PHY_INTERFACE_MODE_NONE;
  95         }
  96
  97         return PHY_INTERFACE_MODE_NONE;
  98 }