]> git.sur5r.net Git - u-boot/blob - drivers/net/fm/p5020.c
Merge branch 'master' of git://git.denx.de/u-boot-ubi
[u-boot] / drivers / net / fm / p5020.c
1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of
7  * the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17  * MA 02111-1307 USA
18  */
19 #include <common.h>
20 #include <phy.h>
21 #include <fm_eth.h>
22 #include <asm/io.h>
23 #include <asm/immap_85xx.h>
24 #include <asm/fsl_serdes.h>
25
26 u32 port_to_devdisr[] = {
27         [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
28         [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
29         [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
30         [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
31         [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
32         [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
33 };
34
35 static int is_device_disabled(enum fm_port port)
36 {
37         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
38         u32 devdisr2 = in_be32(&gur->devdisr2);
39
40         return port_to_devdisr[port] & devdisr2;
41 }
42
43 void fman_disable_port(enum fm_port port)
44 {
45         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
46         setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
47 }
48
49 phy_interface_t fman_port_enet_if(enum fm_port port)
50 {
51         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
52         u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
53
54         if (is_device_disabled(port))
55                 return PHY_INTERFACE_MODE_NONE;
56
57         if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
58                 return PHY_INTERFACE_MODE_XGMII;
59
60         /* handle RGMII first */
61         if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
62                 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII))
63                 return PHY_INTERFACE_MODE_RGMII;
64
65         if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
66                 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII))
67                 return PHY_INTERFACE_MODE_MII;
68
69         if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
70                 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII))
71                 return PHY_INTERFACE_MODE_RGMII;
72
73         if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
74                 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII))
75                 return PHY_INTERFACE_MODE_MII;
76
77         switch (port) {
78         case FM1_DTSEC1:
79         case FM1_DTSEC2:
80         case FM1_DTSEC3:
81         case FM1_DTSEC4:
82         case FM1_DTSEC5:
83                 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
84                         return PHY_INTERFACE_MODE_SGMII;
85                 break;
86         default:
87                 return PHY_INTERFACE_MODE_NONE;
88         }
89
90         return PHY_INTERFACE_MODE_NONE;
91 }