1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011 Freescale Semiconductor, Inc.
9 #include <asm/immap_85xx.h>
10 #include <asm/fsl_serdes.h>
12 static u32 port_to_devdisr[] = {
13 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
14 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
15 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
16 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
17 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
18 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
21 static int is_device_disabled(enum fm_port port)
23 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
24 u32 devdisr2 = in_be32(&gur->devdisr2);
26 return port_to_devdisr[port] & devdisr2;
29 void fman_disable_port(enum fm_port port)
31 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33 /* don't allow disabling of DTSEC1 as its needed for MDIO */
34 if (port == FM1_DTSEC1)
37 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
40 void fman_enable_port(enum fm_port port)
42 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
44 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
47 phy_interface_t fman_port_enet_if(enum fm_port port)
49 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
52 if (is_device_disabled(port))
53 return PHY_INTERFACE_MODE_NONE;
55 if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
56 return PHY_INTERFACE_MODE_XGMII;
58 /* handle RGMII first */
59 if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
60 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII))
61 return PHY_INTERFACE_MODE_RGMII;
63 if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
64 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII))
65 return PHY_INTERFACE_MODE_MII;
67 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
68 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII))
69 return PHY_INTERFACE_MODE_RGMII;
71 if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
72 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII))
73 return PHY_INTERFACE_MODE_MII;
81 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
82 return PHY_INTERFACE_MODE_SGMII;
85 return PHY_INTERFACE_MODE_NONE;
88 return PHY_INTERFACE_MODE_NONE;